JP2003179506A - Turbo decoder and turbo decoding method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a turbo decoder and a turbo decoding method capable of reducing a bit error rate. <P>SOLUTION: A low reliability information storage memory 551 or 552 stores only d pieces of information in order from the lowest reliability out of reliability information M1 being an output of a first soft output decoder 501 and reliability information M2 being an output of a second soft output decoder 502 respectively, which are obtained in the last loop of turbo decoding processing. Storage memories 561 and 562 respecively store position information showing the time point of the reliability information. When a CRC (cyclic redundancy check) deciding device 505 decides that hard decision data are not acceptable, the memories 561 and 562 are referenced, and if there is a matching time point, bits of the hard decision data corresponding to the time point are inverted to perform CRC decision again. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a turbo decoder and a turbo decoding method, and more particularly to a turbo decoder and a turbo decoding method for reducing a bit error rate of decoded data.

[0002]

2. Description of the Related Art In recent years, turbo codes have been in the limelight as a decoding method approaching the limit of Shannon, and it has been decided that they will be adopted in W-CDMA and CDMA-2000, which are the standards for next-generation mobile communication. . FIG. 5 shows a general turbo code transmission system. The transmission system has a turbo encoder 200, a modulator 210, a transmission line 220, a demodulator 230, a received data memory 240, and a turbo decoder 600. The turbo encoder 200 and the modulator 210 are arranged on the transmission side, and the modulator 230, the reception data memory 240, and the turbo encoder 600 are arranged on the reception side.

The turbo encoder 200 has convolutional encoders 201 and 203, and an interleaver 202. The input data INF includes information data in which one frame has n bits and a k-bit CRC (Cyclic) added to the information data.
Redundancy Check) bits, including b bits (b
= N + k) binary data (hard data). The turbo encoder 200 receives 3 from the input data INF.
Two hard data INF_T, Parity1_T, and Parity2_T are generated. INF_T is the same data as the input data INF.
rity1_T is data obtained by encoding the input data INF with the convolutional encoder 201. Parity2_T is data in which the convolutional encoder 203 further encodes the input data INF whose bit positions are rearranged by an interleaver 202 according to a predetermined algorithm.

3 generated by the turbo encoder 200
The two data INF, Parity1_T, Parity2_T are the modulator 21
It is modulated with 0, propagates through the transmission path 220, and reaches the demodulator 230 on the receiving side. Since noise is added to the transmission path 220, a bit error occurs. Therefore, the demodulator 230 uses the three transmitted data INF, Parity1_
Soft decision data INF_R, Parity1_R, Parity2_R that is soft data without immediately demodulating T and Parity2_T as hard data
Demodulate as. Here, the soft data is data in which a binary bit value is converted into multivalued data in an analog manner. That is, bit information of "0" or "1" of hard data is set to a value of "0" to "7" in soft data.

The three soft-decision data INF_R, Parity1_R, and Parity2_R soft-decided by the demodulator 230 are sequentially written in the reception data memory 240. When all the data for one frame are gathered, decoding is started by the turbo decoder 600, and decoded data INF_D is obtained.

FIG. 5 shows the configuration of a conventional turbo decoder. The turbo decoder 600 includes a first soft output decoder 60.
1, second soft output decoder 602, interleaver processing unit 6
20, 621, deinterleaver processing units 630, 63
1, a hard decision processing unit 603, and a CRC decision unit 605. As the soft output decoding algorithm applied to the turbo decoder 600, the maximum posterior probability decoding method (Maximum A
Posterior Probability: Hereafter, it is said that the method using MAP) is the best. But,
Since the device scale and the processing amount are remarkably large, the implementation simplifies whether the path between the points is "1" or "0" by selecting the maximum value (MAX) of the likelihood calculation results.
The x-log-MAP algorithm is commonly used.

The first soft output decoder 601 uses INF_R and Par
ity1_R and the reliability information M1x, which is the output of the deinterleaver processing unit 631, are input to the interleaver processing unit 6
The reliability information M1 is output to 21. Here, the deinterleaver processing unit 631 is an algorithm reverse to that of the interleaver 202, and performs processing for rearranging the data series in the original arrangement order. Interleaver processing unit 621
Outputs the reliability information M1 to the second soft output decoder 602 as reliability information M2x by rearranging the reliability information M1 using the same algorithm as the interleaver 202.

The second soft-output decoder 602 inputs INF_Rx obtained by rearranging INF_R by the interleaver processing unit 620, reliability information M2x, and Parity2_R, and inputs the deinterleaver processing unit 631 and hard decision processing unit 603. Reliability information M
2 is output. The turbo decoder 600 repeats a series of decoding processes a predetermined number of times while updating the reliability information M1 and M2 obtained by the first soft output decoder and the second soft output decoder.

When the iterative process is completed, the hard decision processing unit 603 makes a hard decision on the reliability information M2 as binary data.
That is, the analog value between each time point corresponding to each bit of the hard data is determined to be "0" or "1". The obtained hard data is processed by the deinterleaver processing unit 630.
Then, the data is rearranged and input to the CRC determination unit 605. C
The RC decision unit 605 makes a CRC decision on the input hard data, and if the decision result is good (OK), it decides the decoded data.
Output as INF_D.

[0010]

As described above, the turbo decoder 600 obtains the decoded data INF_D by repeating the series of decoding processes a predetermined number of times. Since the probability that the input data INF will be correctly decoded is determined by the number of times the decoding process is repeated, the number of times of repetition is set in consideration of the maximum value of noise added on the transmission path 220. However, in this case, there is a problem that the decoding time is unnecessarily lengthened when the noise added on the transmission path 220 is small.

A method has been proposed in which the repetitive operation is stopped midway to shorten the decoding time. In this method, the CRC bit added to the data sequence before the turbo coding is used to stop the repetition when the CRC judgment is OK. As a result, the decoding time can be shortened when the noise added to the data is small. But CRC
Unless the judgment is OK, the repetitive processing does not stop,
Since it will be the decryption error as it is, the decrypted data IN
I couldn't get F_D.

There is also known a method of inverting a part of bit values of hard decision data to make a CRC decision. In this method, the position information at the time of low reliability information is stored,
The value of the bit (hard decision bit) of the hard decision data corresponding to that time point is inverted. By inverting the hard-decision bits that are expected to cause a decoding error, it is possible to increase the probability that the result of the CRC decision will be OK. According to this method, the decoding time can be further shortened by quickly identifying the hard-decision bit causing the decoding error. However, a method for efficiently identifying a hard decision bit that is expected to cause a decoding error has not been known so far.

The present invention increases the probability that the result of the CRC determination is OK, and obtains decoded data with a reduced bit error rate with a small number of repetitions even if the noise added on the transmission line is large. It is an object to provide a decoder and a turbo decoding method.

[0014]

To achieve the above object, a turbo decoder according to the present invention comprises a first soft output decoder and a second soft output decoder, and a first soft output decoder. The first reliability information output from the second soft output decoder is input to the second soft output decoder via the interleaver, and the second reliability information output from the second soft output decoder is input via the deinterleaver. The process of inputting to the first soft output decoder is repeatedly performed, and either the first reliability information or the second reliability information in the final iterative process is hard-decided, and the hard-decision data obtained by the hard-decision is CRC. A turbo decoder that outputs hard-decision data that has been judged to be good as a result of CRC judgment as decoded data, and stores the reliability of the first reliability information in the final iterative process at the time of low reliability. 1 low reliability storage means, and The first position information storage unit that stores the position information at the low reliability point stored in the low reliability storage unit and the reliability at the low reliability point of the second reliability information in the final iterative process The hard decision data of the hard decision data is provided with a second low reliability storage unit for storing and a second position information storage unit for storing the position information at the time of the low reliability stored in the second low reliability storage unit. If the CRC determination result is not good, the bit of the hard decision data corresponding to the time point when the position information stored in the first position information storage means and the position information stored in the second position information storage means match. It is characterized by inverting the logic of.

In the turbo decoding method of the present invention, the first soft output decoder generates the first reliability information, and the first reliability information is decoded by the second soft output decoder via the interleaver. To generate second reliability information, and input the second reliability information to the first soft output decoder through a deinterleaver to generate first reliability information. In a turbo decoding method for generating decoded data by iterative processing, a hard decision is made on the first or second reliability information obtained by the final iterative processing, and the first reliability information or the second reliability information is obtained.
Hard-decision is performed on any of the reliability information, and the hard-decision data obtained by the hard-decision is subjected to CRC judgment. When the CRC judgment result is not good, the reliability of the first reliability information in the final iterative process is low. The position information of the reliability at the time and the position information of the reliability at the time when the reliability of the second reliability information in the final iterative process is low are compared, and the hard decision corresponding to the time when the position information of the both matches. The bit logic of the data is inverted and the inverted hard decision data is converted into C
It is characterized in that RC judgment is performed.

In the turbo decoder and the turbo decoding method of the present invention, the reliability of the first reliability information and the reliability of the second reliability information are
A low value at the same time means that there is a high probability that the logical value of the bit of the hard decision data corresponding to that time point is high, so the logical value (bit value) of that bit
, 0 is inverted to 1 and 1 is inverted to 0. Thereby, the hard decision data can be corrected with higher probability. In other words, the result of the CRC determination is likely to be good, and the probability of obtaining decoded data in a short time is high.

In the turbo decoder of the present invention, the first low reliability storage means and the second low reliability storage means respectively store the reliability at a plurality of low reliability times,
It is preferable that the first position information storage means and the second position information storage means store position information at time points corresponding to the plurality of stored reliability levels. First reliability information and second
The reliability information and the probability of being the minimum at the same time are high,
Sometimes, for example, the reliability information at the same time point is the second lowest in the first reliability information and the third lowest in the second reliability information. By storing a plurality of low reliability information and its position information, bit inversion can be performed with a high probability when correcting hard decision data.

Further, in the turbo decoder of the present invention, the position information stored in the first position information storage means and the second position information are stored.
When there are a plurality of time points at which the position information stored in the position information storage means coincides, the logic inversion and non-inversion of the logic of a plurality of bits of the hard decision data corresponding to the coincident time points are made until the CRC judgment becomes good. It is preferable to judge the possible combinations of CRC. When there are a plurality of coincident time points, there is a high possibility that an error has occurred in a plurality of bits of the hard decision data. Therefore, for the bit values of the hard decision data corresponding to all the matching time points, the CRC determination is sequentially performed for possible combinations of inversion and non-inversion. CR
When the C determination is good, the bit operation is terminated and the decoded data is output. Even if an error occurs in multiple bits, there is a high possibility that the error can be corrected correctly.

Further, in the turbo decoder according to the present invention, the position corresponding to the lowest reliability of the reliability information stored in the first low reliability storage means and the second low reliability storage means is set to the first position. It is characterized in that the logic of the bit of the hard decision data corresponding to the position is read out from the position information storage means or the second position information storage means. First reliability information and second
It is highly possible that a bit error has occurred at the time when the reliability information is lowest among the reliability information. Therefore, the bit corresponding to that time point is inverted. This increases the probability that the hard decision data can be correctly corrected.

Further, in the turbo decoder according to the present invention, the first
A plurality of pieces of hard-decision data corresponding to a time point of low reliability until the CRC judgment becomes good in order from the one with the lowest reliability information stored in the low-reliability storage means and the second low-reliability storage means. It is preferable to carry out the CRC determination of possible combinations of the inversion and non-inversion of the logic of the bits. When the CRC determination is not good even if bit operation is performed at the time when the low reliability information of the first reliability information and the low reliability information of the second reliability information match, or when the bit operation is performed at the time of the lowest reliability information of both, With respect to all the reliability information stored in the first low reliability storage means and the second low reliability storage means, bits are operated in order from the one with the lowest reliability. Increasing the number of bits to be manipulated increases the probability that the hard decision data can be correctly corrected.

Also in the turbo decoding method of the present invention, the same advantages as those of these turbo decoders can be obtained by using the preferable turbo decoder.

[0022]

BEST MODE FOR CARRYING OUT THE INVENTION The present invention will be described in detail below based on the embodiments of the present invention with reference to the drawings. Figure 1
FIG. 3 shows the configuration of a turbo decoder according to an embodiment of the present invention. The turbo decoder 500 includes a first soft output decoder 50.
First and second soft output decoder 502, reliability information memory 51
1, 512, interleaver processing units 520, 521, deinterleaver processing units 530, 531, decision unit 541,
542, low reliability information storage memories 551 and 552, position information storage memories 561 and 562, hard decision processing unit 503,
It has a hard decision memory 504 and a CRC decision device 505.

The transmission system of the turbo code reaching the turbo decoder 500 is the same as the transmission system shown in FIG. The interleaver processing units 520 and 521 perform interleave processing with the same algorithm as the interleaver 202 of the turbo encoder 200 of FIG. In addition, the deinterleaver processing units 531 and 530 perform processing of returning the data series rearranged by the interleaver 202 to the original data series by an algorithm reverse to that of the interleaver 202.

FIG. 2 shows a data sequence for one frame of the turbo code, (a) shows the data sequence before the turbo coding, and (b) shows the data sequence after the turbo coding. When the input data INF shown in FIG. 5A is encoded by the turbo encoder 200 of FIG. 5, three data sequences INF_T, Parit
y1_T and Parity2_T are generated. Input data INF
Has a data sequence in which one frame has an n-bit information sequence and k-bit CRC bits added thereto.

The INF_T series is the same data series as the input data INF, and the Parity1_T series is the data series obtained by encoding the input data INF by the convolutional encoder 201 of FIG. The Parity2_T sequence is a data sequence in which the interleaver 202 replaces the bit string of the input data INF with a predetermined algorithm and encodes the replaced bit string by the convolutional encoder 203. The data sequence of INF, Parity1_T, and Parity2_T is a data sequence in which one frame has b bits (b = n + k). The outputs of these turbo encoders 200 are modulated by the modulator 210 and input to the demodulator 230 via the transmission line 220. The demodulator 230 demodulates the signal added with noise on the transmission path 220 into a soft-decision data sequence of INF_R, Parity1_R, and Parity2_R, and receives the received data memory 240.
Output to.

In FIG. 1, the turbo decoder 500 outputs INF_ which is soft decision data from the received data memory 240.
One frame of R, Parity1_R, and Parity2_R is read and decoding is started. The first soft output decoder 501 inputs soft decision data INF_R, Parity1_R, reliability information M1x stored in the reliability information memory 511, and external information (not shown). Here, the extrinsic information is a value determined by the signal-to-noise ratio in the transmission line 220 of FIG. 5 given in advance at each time point. Also,
The initial value of the reliability information M1x is “0”. The first soft output decoder 501 calculates the input data, and outputs the reliability information M1.
Is output. The output reliability information M1 is output to the interleaver processing unit 521, the determiner 541, the low reliability information storage memory 551, and the position information storage memory 561, respectively.

The interleaver processing unit 521 replaces the data series of the reliability information M1 and renews the reliability information M2.
x is generated and output to the reliability information memory 512. The reliability information memory 512 stores the input reliability information M2.
Remember x. The interleaver processing unit 520 inputs the soft decision data INF_R and replaces the data series INF_Rx.
Is output. The second soft output decoder 502 uses INF_Rx and Pa
rity2_R, reliability information M2x, and external information (not shown) are input. Here, the external information is the same information as the external information used by the first soft-output decoder 501.
The second soft output decoder 502 calculates the input data and outputs reliability information M2. The reliability information M2 output is
De-interleaver processing units 530 and 531, decision unit 54
2, the low reliability information storage memory 552, and the hard decision processing unit 503.

The deinterleaver processing section 531 replaces the data series of the reliability information M2 to generate reliability information M1x, and outputs it to the reliability information memory 511. The reliability information memory 511 stores the input reliability information M1x. The stored reliability information M1x is read from the first soft output decoder 501, and again the first soft output decoder 5
The decryption work of 01 is started. That is, the reliability information M1 generated by the first soft output decoder 501 is interleaved and input to the second soft output decoder 502, and the reliability information M2 generated by the second soft output decoder 502. Is
A loop is formed in which deinterleave processing is performed and the data is input to the first soft output decoder 501. The loop processing by the first soft output decoder 501 and the second soft output decoder 502 is repeatedly performed a set number of times.

The reliability information M1 and M2 in the final loop of the loop processing is determined by the determiners 541 and 542 and stored in the low reliability information storage memories 551 and 552. Regarding the reliability information M1, the determiner 541 refers to the low reliability information storage memory 561, and the reliability information M1 at a certain point in the data series is lower than the reliability information stored in the low reliability storage memory 561. Determine whether or not. At the beginning of the data series, the contents of the low reliability storage memory 551 are empty. If the reliability information M1 at the time point to be compared is lower than the reliability stored in the low reliability storage memory 551, the reliability information M1 at that time is stored in the low reliability information storage memory 551. .

The low reliability information storage memory 551 can store d pieces of reliability information M1. Further, the d pieces of reliability information M1 are arranged and stored in order of increasing reliability. When newly storing reliability information, if d pieces of reliability information are already stored in the low reliability information storage memory 551, the highest reliability among the stored d pieces. The information of the information is deleted, and the reliability information M1 having lower reliability is stored instead. When the reliability information M1 is stored in the low reliability information storage memory 551, the position information is stored in the position information storage memory 561 by associating the reliability information with the reliability at which time. To do.

Similarly, the reliability information M2 is also determined by the determiner 542, and the reliability information is stored in the low reliability storage memory 552 so as to be arranged in descending order by d. Also,
When stored in the low reliability information storage memory 552, the position information at that time is output to the deinterleaver processing unit 530, and the position information converted by the deinterleaver processing unit 530 is stored in the position information storage memory 562. To be done. At this time, the low reliability information storage memory 552 stores the order of position information corresponding to the low reliability information in association with the storage order.

At the time of the final iteration, the reliability information M2 at each time point, which is the output of the second soft output decoder 502, makes a hard decision in the hard decision processing section 503, and the obtained hard decision data is deinterleaved. The processing unit 530 rearranges the data sequence corresponding to the data sequence INF before turbo coding, and stores the data sequence in the hard decision memory 504. The output of the position information storage memory 561, the reliability information storage memory 551, the hard decision memory 504, the position information storage memory 562,
The output of the reliability information storage memory 552 is input to the CRC determiner 505.

When the loop processing is completed, the CRC decision unit 505 first reads the hard decision data from the hard decision memory 504 and makes a CRC decision. If the CRC decision result is OK, the hard decision data is output as it is as turbo decoded data INF_D. The first CRC judgment is negative (N
In the case of G), the CRC determiner 505 again reads the hard decision data stored in the hard decision memory 504, and performs an operation of inverting the bit of the hard decision data according to the following procedure. CRC judgment is performed for each bit operation,
When the CRC judgment is OK, the bit operation is finished,
The turbo decoded data INF_D is output.

First, the position information storage memory 561 and the position information storage memory 562 are referenced to check whether the same time points exist. If it exists, the hard decision bit at the position at the corresponding time point is inverted to perform the CRC decision. When there are a plurality of same time points, the possible combinations of inversion and non-inversion of hard decision bits are executed. For example, when there are p same time points, the CRC judgment is O.
CRC determination is performed for each of the 2 ^p combinations until K is reached.

If the same time point does not exist or if the CRC determination is not OK even by the above operation, the low reliability information storage memory 551 and the low reliability storage memory 55.
Among the 2d pieces of reliability information stored in 2, the lowest reliability information is searched. The time point corresponding to the reliability information is specified by referring to the position information storage memory 562 or 561. The bit of the hard decision data corresponding to the specified time point is inverted to perform the CRC decision.

When the CRC judgment is NG, the low reliability information storage memory 551 and the low reliability storage memory 552 are stored.
Then, the next lower reliability information is searched, and the time point corresponding to the reliability information is checked. CRC determination is performed on all possible combinations of inversion or non-inversion of the bits of the hard decision data corresponding to the time points at which all pieces of reliability information retrieved so far are low. If the CRC judgment is NG, the low reliability information is sequentially searched and the bit operation is performed. When the CRC decision is OK at any stage, the bit operation is terminated and the hard decision data at that time is turbo-decoded.
Output as INF_D. If the CRC judgment does not become OK even if the bit manipulation is executed for all the reliability information, the hard decision data stored in the hard decision memory 504 is output as it is as the turbo decoding data INF_D.

The processing of the turbo decoder will be further described with reference to the flowchart of FIG. In the turbo decoder, when the decoding process is started, the first soft output decoder calculates input data to obtain reliability information M1 (step S1). The reliability information M1 is rearranged by the interleaver 521 and input to the second soft output decoder to obtain reliability information M2 (step S2). The obtained reliability information 2 is the deinterleaver 5
The data is rearranged at 31 and input to the first soft output decoder.
The number of times the processes of step S1 and step S2 are repeated is counted. If the number of repetitions does not reach the specified number, the process returns to step S1.
4 (step S3).

When the iterative process is completed, the reliability information M1
Also, only d pieces of low reliability information M2 are stored (step S4). At that time, position information indicating at what time the reliability is low is stored correspondingly. The position information of the reliability information M2 is the position information when rearranged by the deinterleaver 630. Next, the reliability information M2 is hard-decided, and the hard-decision data rearranged by the deinterleaver 530 is stored in the hard-decision memory (step S5). CRC determiner 505
CRC-determines the hard decision data and obtains whether the decision result is OK (step S6). If the determination result is OK, the hard decision data is output as decoded data (step S8). If the result is NG, the process proceeds to bit inversion of hard decision data (step S7).

FIG. 4 shows details of the bit inversion process in step S7. The two pieces of position information stored in step S4 are compared with each other, and it is checked whether or not there is matching position information (step S701). If there is no match,
It proceeds to step S706. If there is a match, the hard decision bit corresponding to the time of the match is inverted (step S702), and the CRC decision is made (step S7).
03). If the CRC determination is OK, the bit inversion process is terminated and the process proceeds to step S8 in FIG. When it is not OK, it is determined whether or not all combinations of inversion and non-inversion of the hard-decision bits at the time point corresponding to the position information have been executed for a plurality of matching position information (step S704). If all combinations have not been completed, the process returns to step S702 to make a CRC determination for all combinations. Initially, since there is one bit to be inverted, the process proceeds to step S705.

Again, the position information stored in step S4 is compared, and it is checked whether or not there is another matching position information (step S705). If there is no other match, the process proceeds to step S706. If there is another matching item, the process returns to step S702, and the processes from step S702 to step S705 are repeated for all matching items.

If the determinations in steps S701 and S706 are negative, the reliability information M1 and the reliability information M
Of the two stored ones with low reliability, the one with the lowest reliability is selected (step S706). The hard decision bit corresponding to the selected position is inverted (step S7).
08), and CRC determination is performed (step S709). With respect to a plurality of selected hard-decision bits, it is judged whether or not all combinations of inversion and non-inversion have been executed (step S709). If all the combinations are not exhausted, the process returns to step S707 to perform the CRC determination for all the combinations. Initially, since the number of selected hard decision bits is one, the process proceeds to step S710.

The reliability information M1 and the reliability information M2 selected so far are selected with the lowest reliability information excluding those with low reliability (step S710). If there is one to be selected, the process returns to step S707, and the bit corresponding to the reliability is inverted. If there is no reliability to be selected, the bit inversion process ends (step S711). The processing of steps S707 to S711 is repeated, and the CRC determination is performed on the combination of inversion and non-inversion of the hard decision bits for all of the stored low reliability.

In the bit inversion process, the hard decision data having a good CRC decision is output as the output of the turbo decoder. However, in step S711, when the bit inversion processing is completed without the CRC determination being good, the hard decision data obtained in step S5 of FIG. 3 is output as the output of the turbo decoder.

In the turbo decoder 500 of the present embodiment, among the reliability information at each time point obtained in the decoding process of the first soft output decoder 501, only the reliability information M from the lowest reliability information is M.
1 and the position information indicating the time point are stored. Similarly, of the reliability information M2 at each time point obtained in the decoding process of the second soft output decoder 502, only the reliability information M1 from the lowest one is stored, and the reliability information M1 and the position information indicating the time point are stored. When the hard decision data is determined to be NG in the CRC decision, it is checked whether or not there is a time point at which the position information matches among the d pieces stored respectively, and if there is one or a plurality of time points at which the time points match, The operation of inverting some or all of the bits of the hard decision data corresponding to those times is performed, and CRC decision is performed on them.

If the CRC judgment does not become OK even by the operation, the low reliability storage memories 552 and 551.
For all the reliability information stored in, the bits of the hard decision data corresponding to that point in time from the lowest are performed for possible combinations of inversion or non-inversion, and they are
judge. This increases the possibility that the CRC judgment will be OK, and the bit error rate of decoded data can be reduced.

Although the present invention has been described above based on its preferred embodiment, the turbo decoder of the present invention is not limited to the above embodiment, and various configurations from the above embodiment are possible. The turbo decoder with the modifications and changes of
Within the scope of the present invention. For example, in the bit inversion method of the hard decision data, in addition to inverting the position information corresponding to the lowest reliability information bit by bit, adjacent 2-bit and 3-bit inversion may be combined. In that case, C
The probability that the RC judgment will be OK is further increased.

[0047]

As described above, according to the turbo decoder and the turbo decoding method of the present invention, the time when the reliability information is low is stored and the bit of the hard decision data is effectively inverted so that the CRC decision can be made. The probability that the result will be OK is increased, and correct decoded data can be obtained with a small number of iterations even when the noise added on the transmission path is large.

[Brief description of drawings]

FIG. 1 is a block diagram showing an overall configuration of a turbo decoder according to an embodiment of the present invention.

FIG. 2 is a diagram showing a data sequence of a turbo code, where (a) is a data sequence before the turbo code and (b) is a data sequence after the turbo code.

FIG. 3 is a flowchart showing a processing flow of a turbo decoding method of the present invention.

FIG. 4 is a flowchart showing a detailed processing flow of bit inversion processing of FIG.

FIG. 5 is a block diagram showing a transmission system of a turbo code.

FIG. 6 is a block diagram showing a configuration of a conventional turbo decoder.

[Explanation of symbols]

200: Turbo encoder 201, 203: fold-in encoder 202: Interleaver 210: Modulator 220: Transmission line 230: Demodulator 240: Received data memory unit 500: Turbo decoder 501: First soft output decoder 502: Second soft output decoder 503: Hard decision processing unit 504: Hard decision memory 505: CRC judging device 511, 512: Memory for reliability information 520, 521: Interleaver processing unit 530 and 531: Deinterleaver processing unit 541 and 542: judging device 551 and 552: low reliability information storage memories 562, 561: Position information storage memory 600: Turbo decoder 601: First soft output decoder 602: Second soft output decoder 603: Hard decision processing unit 605: CRC judging device 620, 621: Interleaver processing unit 630, 631: Deinterleaver processing unit

Front page continuation (51) Int.Cl. ⁷ Identification code FI theme code (reference) H04L 1/00 H04L 1/00 BF term (reference) 5J065 AA01 AB01 AC02 AD04 AD10 AE06 AF01 AG05 AG06 AH06 AH21 5K014 AA01 BA06 BA10 FA16 GA02 HA10 5K041 AA04 BB08 FF32 GG03 HH11 HH32

Claims (13)

[Claims] 1. A first soft output decoder and a second soft output decoder are provided, and the first reliability information output from the first soft output decoder is sent to a second soft output via an interleaver. The process of inputting to the output decoder and inputting the second reliability information, which is the output of the second soft output decoder, to the first soft output decoder via the deinterleaver is repeatedly performed. Hard decision is made on either the first reliability information or the second reliability information, and the hard decision data obtained by the hard decision is CRC.
A turbo decoder that outputs hard-decision data that has been judged to be good as a result of CRC judgment as decoded data, and stores a reliability at a time point when the reliability of the first reliability information in the final iterative process is low. Low reliability storage means,
First position information storage means for storing position information at the time point of low reliability stored in the first low reliability storage means, and reliability at time point of low reliability of the second reliability information in the final iterative process. A second low-reliability storage unit that stores a degree of reliability, and a second position-information storage unit that stores position information at a time when the reliability is low, which is stored in the second low-reliability storage unit. When the CRC judgment result of the data is not good,
The logic of the bit of the hard decision data corresponding to the time point at which the position information stored in the first position information storage means and the position information stored in the second position information storage means coincide with each other and is inverted. A turbo decoder characterized in that the hard decision data is subjected to CRC decision. 2. The first low reliability storage means and the second
Each of the low-reliability storage means stores a plurality of reliability at a time point when the reliability is low, and each of the first position information storage means and the second position information storage means corresponds to a plurality of stored reliability. The turbo decoder according to claim 1, characterized in that it stores the position information at the time of performing. 3. The CRC determination is good when there are a plurality of time points at which the position information stored in the first position information storage means and the position information stored in the second position information storage means coincide with each other. 3. The turbo decoder according to claim 2, wherein CRC determination is sequentially performed on possible combinations of logical inversion and non-inversion of a plurality of bits of the hard decision data corresponding to the coincident time. 4. The first low reliability storage means and the second
The position corresponding to the lowest reliability of the reliability information stored in the low reliability storage means is read from the first position information storage means or the second position information storage means, and the hard decision data corresponding to the read position is read. Turbo decoder according to any of claims 1 to 3, characterized in that the logic of the bits is inverted. 5. The first low reliability storage means and the second
The logic of a plurality of bits of the hard decision data corresponding to the time when the stored reliability information is low until the CRC judgment becomes good, in order from the lowest reliability information stored in the low reliability storage means. 5. The turbo decoder according to claim 4, characterized in that CRC determination is performed on possible combinations of inversion and non-inversion. 6. A first soft output decoder and a second soft output decoder are provided, and the first reliability information which is the output of the first soft output decoder is sent to a second soft output via an interleaver. The process of inputting to the output decoder and inputting the second reliability information, which is the output of the second soft output decoder, to the first soft output decoder via the deinterleaver is repeatedly performed. Hard decision is made on either the first reliability information or the second reliability information, and the hard decision data obtained by the hard decision is CRC.
A turbo decoder that outputs hard-decision data that has been judged to be good as a result of CRC judgment as decoded data, and stores a reliability at a time point when the reliability of the first reliability information in the final iterative process is low. Low reliability storage means,
First position information storage means for storing position information at the time point of low reliability stored in the first low reliability storage means, and reliability at time point of low reliability of the second reliability information in the final iterative process. And a second position information storage unit that stores position information at a time point when the reliability is low, which is stored in the second low reliability storage unit. When it is not good, the position corresponding to the lowest reliability of the reliability information stored in the first low reliability storage means and the second low reliability storage means is set to the first position information storage means or the second position information. A turbo decoder characterized by reading from a storage means and inverting the logic of the bits of the hard decision data corresponding to the read position. 7. The first low reliability storage means and the second
The logic of a plurality of bits of the hard decision data corresponding to the time when the stored reliability information is low until the CRC judgment becomes good, in order from the lowest reliability information stored in the low reliability storage means. 7. The turbo decoder according to claim 6, wherein CRC determination is performed on possible combinations of inversion and non-inversion. 8. A first soft-output decoder generates first reliability information, and the first reliability information is input to a second soft-output decoder via an interleaver to generate a second soft-output decoder. Decoding data is generated by iterative processing of generating reliability information and inputting the second reliability information to the first soft-output decoder through a deinterleaver to generate the first reliability information. In the turbo decoding method, a hard decision is made on the first or second reliability information obtained by the final iterative processing, and a hard decision is made on either the first reliability information or the second reliability information, and the hard decision is made. CRC determination is performed on the hard-decision data obtained by, and when the CRC determination result is not good, the reliability position information at the time of low reliability of the first reliability information in the final iterative process and the final repetitive process. Second confidence information Comparing with position information of reliability at a low time point, inverting the logic of the bit of the hard decision data corresponding to the time point when the both position information coincides, and performing CRC decision on the inverted hard decision data. A turbo decoding method characterized by: 9. When there are a plurality of time points at which the two pieces of position information match, until the CRC judgment becomes good, the inversion and non-inversion of the logic of a plurality of bits of the hard decision data corresponding to the coincident time points are taken. The turbo decoding method according to claim 8, wherein CRC determination is sequentially performed on the obtained combinations. 10. The logic of the bit of the hard decision data corresponding to the time point of the lowest reliability in both the first low reliability information and the second low reliability information is inverted. 8. The turbo decoding method according to 8 or 9. 11. C of the first low-reliability information and the second low-reliability information, in ascending order of reliability information,
The CRC determination is performed on possible combinations of inversion and non-inversion of logic of a plurality of bits of the hard decision data corresponding to the time point of the low reliability information until the RC decision becomes good. 11. The turbo decoding method according to any one of 10. 12. A first soft output decoder generates first reliability information, and the first reliability information is input to a second soft output decoder via an interleaver to generate a second soft output decoder. Decoding data is generated by iterative processing of generating reliability information and inputting the second reliability information to the first soft-output decoder through a deinterleaver to generate the first reliability information. In the turbo decoding method, a hard decision is made on the first or second reliability information obtained by the final iterative processing, and a hard decision is made on either the first reliability information or the second reliability information, and the hard decision is made. CRC determination is performed on the hard decision data obtained by, and when the CRC determination result is not good, the hard decision corresponding to the time point of the lowest reliability in both the first low reliability information and the second low reliability information. Inverting the logic of the bits of data Turbo decoding method according to claim. 13. C of the first low-reliability information and the second low-reliability information, in ascending order of reliability information,
13. The CRC determination of possible combinations of inversion and non-inversion of logic of a plurality of bits of the hard decision data corresponding to the time point of the low reliability information, until the RC decision becomes good. The described turbo decoding method.