JP2003178105A - Logic verification system of system lsi - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a logic verification system for a system LSI in which a software used as a device driver and/or check program is used to perform co-verification. <P>SOLUTION: A peripheral device interface 116 is prepared from the device driver and check program for controlling behavior models 110-112 of any peripheral device, and thereby the device driver and check program capable of operating on the actual chip can undergo a logic verification using the behavior models 110-112 of the peripheral device. <P>COPYRIGHT: (C)2003,JPO

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a logic verification method for a system LSI which is an integrated circuit. 2. Description of the Related Art Conventionally, a verification method using co-verification uses a software described in C language or the like to generate a transaction similar to that of a CPU in a behavior model so that a verification target can be identified. Test of the circuit. For example, there are the following methods. (1) Instruction set simulator Simulates software written in C language or the like,
A method of generating a transaction equivalent to a CPU via an instruction set simulator that analyzes an object in an executable form and inputs the analyzed object to a behavior model of the CPU. (2) Software-dedicated interface A CPU command for interfacing with a behavior model is defined in software described in C language or the like. When a CPU command is called in software, the CPU command is called through the interface with the behavior model. A method for generating a transaction equivalent to a CPU. However, in the above conventional example, software is often described on the assumption that it is executed by the CPU, so that only software that can be accessed from the CPU can be controlled. When executed on an actual chip, the chip is mounted on an electric circuit board, and further, peripheral devices and peripheral devices are connected, so that software can check the operation with those peripheral devices and peripheral devices. However, in the case of logic verification, since there is no peripheral device or peripheral device connected to the system LSI, a test is performed by connecting a virtual operation model. Since these virtual operation models are external devices and peripheral devices of the system LSI, they cannot be set from the CPU. Therefore, since these virtual operation models cannot be controlled from software, there is a disadvantage that it is difficult to verify a circuit based on the actual operation of the system LSI. An object of the present invention is to provide a mechanism capable of controlling a virtual operation model of an external device / peripheral device connected to a system LSI from software, thereby enabling verification under a real operation environment of the system LSI. And that the software can be used as a device driver / check pro on an actual chip. [0007] Therefore, the present invention is to achieve the above object by providing the following system LSI logic verification method. A central control circuit (hereinafter referred to as CPU) and the CP
An integrated circuit (hereinafter, referred to as a system LSI) having a built-in peripheral circuit electrically connected to the U; a virtual operation model (hereinafter, a behavior model) for verifying the system LSI; A logic verification environment (hereinafter referred to as a test bench) for verifying a system LSI using the behavior model, a test program for verifying the system LSI on the test bench, and a test program using the test program. A logic verification method for a system LSI for verifying a system LSI, comprising: a test bench using a behavior model of the CPU instead of the CPU; and a peripheral circuit control program (hereinafter referred to as a device driver) operable on an actual chip. ) And a peripheral circuit operation verification program (hereinafter referred to as “check pro”) through the CPU behavior model. In a logic verification environment including a method of performing verification by performing the verification (hereinafter referred to as co-verification) and a means for interfacing hardware and software of a system LSI in the co-verification, the device driver and the By preparing an interface for controlling the behavior model from the check pro, the device driver operable on an actual chip and the check pro can be logically verified using the behavior model. A logic verification method for system LSI. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS (First Embodiment) FIG. 1 is a diagram that best illustrates the features of the present invention. Reference numeral 101 denotes a system LSI, 102 denotes software for verifying a circuit of the system LSI 101, 103
Is a CPU behavior model, 104 is software 1
CPU interface between the CPU instruction 02 and the CPU behavior model 103; 105, a CPU bus to which the electrical signals of the CPU behavior model 103 are connected; 106, a bus arbiter for arbitrating the right to use the CPU bus 105; Is a memory controller connected to the CPU bus 105, and 108 is a memory controller 1
07 is a memory to be read / written, and 109 is a CPU bus 1
DMA controller 110 to 110-112
Are behavior models of peripheral devices, 113 to 115
Is a peripheral device controller that controls each of the peripheral devices 110 to 112, and 116 is a peripheral device interface from the software 102 to the behavior model of the peripheral device. By writing a CPU command in the software 102, the CPU command requests the CPU behavior model 103 to execute an instruction via the CPU interface 104. For example, when a CPU command for writing data D to an address A on the memory 108 is described in the software 102, the C
PU behavior viewer model 103 is a bus arbiter 10
A request to acquire the right to use the bus is issued to 6. As a result of the bus arbitration, the bus arbiter 106 becomes the CPU behavior model 103
Gives bus usage right to CPU behavior model 1
03 issues a request to the memory controller 107 to write the data D to the address A on the memory 108. Upon receiving the request, the memory controller 107 accesses the memory 108, writes data, and executes the CPU behavior model 1
03 is notified that writing has been completed. Then, the CPU behavior model 103 becomes the CPU interface 104
, The software 102 that has made a write request to the memory 108 is notified of the completion of writing. As described above, the software 102
By using the behavior model 103, it is possible to control a circuit in the system LSI 101. However, with this method alone, since the CPU behavior model 103 cannot control the behavior models 110 to 112 of the external peripheral devices, the peripheral device control program operating on the actual chip cannot be executed. For example, 111
Is a serial interface behavior model,
If the controller 114 is a controller of the serial interface model 111, if the behavior model cannot be set, such as a setting to operate the serial interface behavior model 111 at various transfer speeds and a setting to generate a transfer error, Verification that satisfies the specifications cannot be performed. Therefore, in such a case, the software 10
From 2, the provision of the peripheral device interface 116 for controlling the behavior model 111 of the serial interface enables verification in which the behavior models 110 to 112 of the peripheral device are set to various modes. When executed on an actual chip, the peripheral device can be used simply by deleting the set locations of the behavior models 110 to 112. FIG. 2 shows an example of the algorithm of the present invention. Reference numeral 201 denotes issuance of a command from the software 102 to the peripheral device, reference numeral 202 denotes selection of an interface, reference numeral 203 denotes issuance of a command from the peripheral device interface 116 to the peripheral device behavior models 110 to 112, and reference numeral 204 denotes selection of a corresponding peripheral device. , 205 are peripheral device behavior models 110 to 110
Waiting for a response of the execution result of 112, 206 is a response from the CPU interface 104 to the software 102, 20
7, a command issuance from the CPU interface 104 to the CPU behavior model 103;
Waiting for response of execution result of behavior model 103, 20
Reference numeral 9 denotes a response from the peripheral device interface 116 to the software 102, and reference numeral 210 denotes confirmation of termination of the software 102. For example, one of the serial controllers 114
When performing read logic verification at 1520 bps (bits per second), the software 102
To serial interface behavior model 1
11, it is necessary to make settings for expecting the behavior of transferring 11520 bps data. In that case, 201-
The setting is performed on the behavior model 111 of the serial interface via the algorithm 205. As a result, data is transferred at 11520 bps from the behavior model 111 of the serial interface, and an interrupt request from the serial controller 114 and processing of the software 102 for the interrupt can be logically verified. By using this method, setting of all transfer speeds and setting of intentionally generating an error are performed on the behavior models 110 to 112 of peripheral devices.
The logic verification of the system LSI 101 by the software 102 becomes possible. FIG. 3 shows an example of a program using the peripheral device interface 116 of the present invention. Reference numeral 301 denotes a behavior model setting program for a serial interface, reference numeral 302 denotes a peripheral device interface, reference numeral 303 denotes a behavior model for a serial interface, and an excerpt of an example of each source code. In the source code 301 of the behavior model setting program for the serial interface,
In this example, an interface is obtained by exchanging data of the structures on the first to fifth lines and the structures on the first to fifth lines of the source code 302 of the peripheral device interface. In an actual logic verification environment, an interface between a C program such as FLI and the logic verification environment is used. In this example, a method of using a serial interface as an example of a peripheral device behavior model and setting the transfer speed of the model to 11520 bps will be introduced. Software (source code of behavior model setting program for serial interface)
The following is agreed upon between the source code 301 and the source code 302 of the peripheral device interface. (1) When type is 1, the behavior model of the serial interface is selected. (2) When type is 1 and Param is 1, it is set to 11520 bps. First, when the values of the structures on the 10th to 12th lines of the software (source code of the behavior model setting program of the serial interface) 301 are set, the software (the behavior model setting of the serial interface) is set on the 13th line. The program source code) 301 waits until the value of stat becomes 1. In the seventh to eighth lines of the source code 302 of the peripheral device interface, the source code 303 of the behavior model of the serial interface is selected.
In the line, the source code 303 of the behavior model of the serial interface is set. Then, the task on the first line of the source code 303 of the behavior model of the serial interface is executed, and param becomes 1
In the case of, the transfer speed is set to 11520 bps in the fifth row. When the setting of the source code 301 of the behavior model setting program of the serial interface is completed, a response is returned from the source code 301 of the behavior model setting program of the serial interface to the tenth line of the source code 302 of the peripheral device interface, and Stat is set to 1 Is set to Then, a response is returned from the source code 302 of the peripheral device interface to the thirteenth line of the software (source code of the behavior model setting program of the serial interface) 301, and the setting is completed. (Second Embodiment) FIG. 4 shows an embodiment in which the CPU interface 104 in the embodiment of FIG. 1 is replaced with an instruction set simulator. Reference numeral 401 denotes an instruction set simulator. Other configurations are the same as those in FIG. 1, and the same reference numerals are given and the description is omitted. When the software 102 is compiled and executed, the instruction set simulator 4
01 interprets the executable code and sends it to the behavior model 103 of the CPU. The difference from the software 102 in FIG. 1 is that the software 102 in FIG. 1 requires a CPU command with a specially defined CPU interface 104, whereas the software 102 in FIG. The instruction set simulator 401 converts the
That is, it can be interpreted as a PU instruction and executed. Also in this case, the behavior models 110 to 112 of the peripheral devices are transmitted from the software 102.
Device interface 11 for controlling the
Providing 6 enables verification in which the behavior models 110 to 112 of peripheral devices are set to various modes. When it is executed on an actual chip, it can be used simply by deleting the setting points 110 to 112 in the behavior model of the peripheral device. As described above, according to the invention of the present application, the behavior model 11 of the peripheral device, which cannot be set by the device driver or the check pro, is used.
0 to 112 can be set, and the software 102
Can be used for logic verification.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 shows a system L according to a first embodiment of the present invention.
FIG. 2 is a diagram showing an SI verification method. FIG. 2 is an example of an algorithm according to the first embodiment of the present invention. FIG. 3 is a program using a peripheral device interface of the present invention according to the first embodiment of the present invention. Example (a) Excerpt of source code example of behavior model setting program of serial interface (b) Excerpt of source code example of peripheral device interface (c) Excerpt of source code example of behavior model of serial interface 4. System L according to the second embodiment of the present invention
[Description of Symbols] 101 System LSI 102 Software 103 for verifying the circuit of system LSI 101 CPU behavior model 104 CPU interface 105 between CPU instruction of software 102 and CPU behavior model 103 CPU behavior CPU bus 106 to which the electric signal of model 103 is connected Bus arbiter 107 for arbitrating the right to use the bus of CPU bus 105 Memory controller 108 connected to CPU bus 105 Memory 109 read and written by memory controller 107 CPU bus 105 Connected DMA controllers 110 to 112 Behavior models 113 to 115 of peripheral devices Peripheral device controllers that control behavior models 110 to 112 of each peripheral device Roller 116 Peripheral device interface 301 from software 102 to peripheral device behavior models 110 to 112 Extraction of source code example of behavior model setting program of serial interface 302 Extraction of source code example of peripheral device interface 303 Serial interface Source code excerpt of behavior model 401 Instruction set simulator

Claims (1)

Claims: 1. A central control circuit (hereinafter referred to as a CPU),
An integrated circuit (hereinafter, referred to as a system LSI) having a built-in peripheral circuit electrically connected to the PU, and a virtual operation model (hereinafter, referred to as a system operation) for verifying the system LSI.
A behavior model), a logic verification environment (hereinafter, referred to as a test bench) for verifying the system LSI using the behavior model, a test program for verifying the system LSI on the test bench, A logic verification method of a system LSI for verifying the system LSI by using a program, comprising: a test bench using a behavior model of the CPU instead of the CPU; and a peripheral circuit operable on a real chip. A method of performing verification by executing a control program (hereinafter, device driver) and a peripheral circuit operation verification program (hereinafter, check pro) through the CPU behavior model (hereinafter, co-verification);・ In verification, the interface between hardware and software of the system LSI An interface for controlling the behavior model from the device driver and the check pro in a logic verification environment having a means for taking the interface, the device driver and the check pro operable on an actual chip. Wherein a logic verification can be performed using the behavior model.