JP2003177959A - Memory control circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a memory control circuit which enables stable memory access by an automatic timing control circuit even in variation in temperature, a process, or source voltage. <P>SOLUTION: A plurality of clocks 35 to 38 are generated which are out of timing with a system clock 34, an enable signal 15 is latched with the clocks 35 to 38, and a comparator 30 compares a previously set AC timing value of a register 32 with a value obtained by latching the enable signal 15; and a counter capable of varying a buffer capacity when they do not match each other to vary the delay quantity of the enable signal 15 is incorporated in a timing adjustment circuit 31, which automatically adjusts the timing until the AC timing value is satisfied. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory control circuit incorporated in a semiconductor device, and more particularly, an automatic timing adjustment circuit even when the AC timing guarantee becomes strict due to variations in device temperature and power supply voltage. The memory access control timing automatic adjustment function that realizes the optimum memory access is provided.

[0002]

2. Description of the Related Art FIG. 5 shows a block diagram of a conventional memory control circuit. In the figure, the CPU circuit unit 11, the bus controller (BUSC) 12, and the IO terminal 13 are the address bus 1
4 and connected from the bus controller (BUSC) 12 to I
A memory read signal (read enable signal) NREEX15 is output to the O terminal 13, and a system clock signal SYSCLKEX16 is output from the CPU circuit unit 11 to the IO terminal 13.

An address A (23: 0) signal from the A (23: 0) terminal 17 of the IO terminal 13 is a memory read (read enable) N.
A memory read signal is output from the RE terminal 18, and a system clock signal is output from the system clock SYSCLK terminal 19.

A conventional memory control circuit having the above configuration will be described. BUSC12 accesses the external memory space and
A memory read signal NREEX15 is issued during AD. IO section 1
3 outputs the memory read signal from the memory read NRE terminal 18 after driving the memory read signal NREEX15 by the buffer. The system clock signal SYSCLKEX16 is driven by the buffer of the IO terminal 13, and then the system clock signal is output from the system clock SYSCLK terminal 19.

FIG. 6 is an AC timing chart in the temperature and power supply voltage range specified by the LSI. System clock
Address signal delay 20 and read enable signal delay 21 are specified from the rise of SYSCLK.

[0006]

However, in the above conventional configuration, the memory control signal defines the system clock reference or the AC specification relatively, but the operation of the LSI depends on the temperature condition, the power supply voltage, and the process variation. The margins are different and stable memory access cannot be performed.

In order to solve the above-mentioned problems, it is an object of the memory control circuit of the present invention to provide stable memory access by an automatic timing control circuit even if there are temperature, process and power supply voltage fluctuations.

[0008]

According to a first aspect of the present invention, there is provided a memory control circuit, wherein the memory control circuit generates a plurality of clocks whose timing is changed from a system clock, and a means for sampling a memory control signal at the plurality of clocks. A register that stores a preset AC timing value, a comparator that compares the sampled value of the memory control signal with the AC timing value, and a buffer capacity that can be changed to change the delay amount of the memory control signal And a timing adjustment circuit that incorporates a counter and automatically adjusts the timing until the sampled value does not satisfy the AC timing value until the AC timing value is satisfied.

According to the memory control circuit of the first aspect,
A stable memory access can be provided by the automatic timing control circuit even if there is a change in temperature, process, or power supply voltage.

According to a second aspect of the present invention, in the memory control circuit according to the first aspect, the dummy pulse is generated before the first access of the ROM by the CPU, and the timing adjustment circuit performs the timing adjustment during the timing adjustment period from that point. Is to have.

According to another aspect of the memory control circuit of the present invention,
It has the same effect as the first aspect.

[0012]

BEST MODE FOR CARRYING OUT THE INVENTION An embodiment of the present invention will be described below with reference to FIGS.

FIG. 1 is a block diagram of an embodiment of the present invention. CPU circuit section 11, bus controller (BUS
An address bus is connected to C) 12 and IO terminal 13, and a read enable signal NREEX is sent from the bus controller (BUSC) 12.
15 is output, and the system clock SYSCLKEX signal 34 is output from the CPU circuit unit 11 to the IO terminal 13. Address signal from IO terminal 13 to A (23: 0) terminal 17 is NRE
The read enable signal 15 is output from the terminal 18, and the system clock signal 34 is output from the SYSCLK terminal 19.

Further, the system clock SYSCLKEX signal 34
Are supplied to a plurality of cascaded buffers 39 and are delayed by a plurality of SYSYCLKEX1 35, SYSYCLKEX2 36, SYSYCLKEX3 37, S
YSYCLKEX4 38 is made, and read enable of the bus controller 12 is made by a plurality of latch circuits 33 by these signals.
The NREEX signal 15 is latched and sampled.

The AC timing storage register 32 presets the AC specifications determined by the specifications of the LSI. The comparator 30 latches the latched value and the AC timing storage register 32.
Compare the values set in.

FIG. 2 is a timing chart of the latch circuit 33 shown in FIG. A sampling clock obtained by delaying the system clock 34 obtained by dividing the external oscillation clock 41 by two.
NREEX signal 15 is latched at the rising edge of SYSCLKEX 1 to 4 (35-38), and the latched sampling value 48 is 0111.
Becomes The setting value of the AC timing storage register 32 is 0011.
In this case, the latched value 0111 is larger than the value 0011 of the AC timing storage register 32, and thus the AC spec is not guaranteed. If the AC specifications are not met, adjust the timing. That is, the output of the comparator 30 is given to the timing adjustment circuit 31.

The internal circuit of the timing adjusting circuit 31 is shown in FIG.
Shown in. Reference numeral 51 is a clock control circuit for selecting the buffer 52 for changing the driving capability of the NREEX 15 by a counter composed of, for example, a DFF. When the latched value is larger than the AC timing storage register 32,
The buffer 52 capable of changing the drive capacity of the NREEX 15 is sequentially turned on by the clock control circuit 51, and the buffer capacity is increased to repeat until the latched value becomes smaller than the AC timing storage register 32. When it becomes smaller, the clock enable signal of the clock control circuit 51 is disabled to determine the buffer capability.

If the latched value is smaller than the value of the AC timing storage register 32, the AC specifications are guaranteed, and the timing adjustment is not performed.

FIG. 4 is a timing chart of the automatic timing adjustment period.

Normally, after releasing the external reset NTGTRST61, after waiting for oscillation stabilization, the microcomputer internal reset NRST63
Is released and the address 64 is accessed at the address 80,000. At that time, the read enable signal 68 becomes active. At the time of automatic timing adjustment, the automatic timing adjustment reset NRST TST62 earlier than NRST63 is released, a dummy pulse 66 is generated in NREEX65 (15) before the IO pin output, and the automatic timing adjustment reset 6 described above is generated.
After the release of 2, after a predetermined period (can be set arbitrarily), from the fall of the dummy pulse 66 to the automatic timing adjustment period 6
Going through 7, address 64 starts accessing address 80,000. Since NREEX65 has already selected the optimum buffer that meets the AC specifications, stable memory access is possible.

[0021]

According to the memory control circuit of the first aspect of the present invention, stable memory access can be provided by the automatic timing control circuit even if there are temperature, process, and power supply voltage fluctuations.

According to another aspect of the memory control circuit of the present invention,
It has the same effect as the first aspect.

[Brief description of drawings]

FIG. 1 is a block diagram of a memory control circuit according to an embodiment of the present invention.

FIG. 2 is a timing chart of a latch circuit 33 shown in FIG.

FIG. 3 is a timing adjustment circuit diagram of FIG.

FIG. 4 is a timing chart of an automatic timing adjustment period.

FIG. 5 is a block diagram of a conventional memory control circuit.

FIG. 6 is an AC timing chart specified by a semiconductor.

[Explanation of symbols]

11 CPU circuit 12 Bus controller circuit 13 IO terminal 14 Address bus 15 Read enable signal 16 System clock signal 17 Address terminal 18 Read enable terminal 19 System clock terminal 20 Address signal delay from rising of system clock 21 Reading from rising of system clock Enable signal delay 30 Comparator 31 Timing adjustment circuit 32 AC timing storage register 33 Latch circuit 34 System clock signal 35 System clock delay signal 1 36 System clock delay signal 2 37 System clock delay signal 3 38 System clock delay signal 4 41 External oscillation clock 42 system clock (divided by 2 of external oscillation clock) 48 sampling value 51 clock control circuit 52 for switching buffer capacity Buffer enable signal for changing drive capability 61 External reset 62 Automatic timing adjustment reset 63 Microcomputer internal reset 64 Address signal 65 Read enable signal 66 when automatic timing is generated Dummy pulse 67 Automatic timing adjustment period 68 Read enable terminal for external output

Claims (2)

[Claims] 1. A means for generating a plurality of clocks whose timings are changed from a system clock, a means for sampling a memory control signal with the plurality of clocks, a register storing a preset AC timing value, and the memory. The value obtained by sampling the control signal is the AC
If the sampled value does not satisfy the AC timing value by incorporating a comparator for comparing with the timing value and a counter capable of changing the buffer capacity to change the delay amount of the memory control signal, the AC timing value is A memory control circuit having a timing adjustment circuit that automatically adjusts the timing until it is satisfied. 2. The memory control circuit according to claim 1, further comprising means for generating a dummy pulse before the first access of the ROM by the CPU, and performing timing adjustment by the timing adjustment circuit during the timing adjustment period from that point.