JP2003173631A - Apparatus and method for digital modulation - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To select an algorithm A or an algorithm B prepared for the purpose of controlling DSV in the case of controlling DSV of a code word string. <P>SOLUTION: When p-bit input data words Ds is converted to at least one code word Cd consisting of q-bits (q>p) by using a plurality of coding tables and the at least one code word is connected with a code word string coded before this in the state of meeting a run-length-limiting rule to generate at least one code word string, in the case of selecting a code word minimizing the absolute value of DSV to the at least one code word string by a DSV control part 19, the algorithm A and the algorithm B are prepared for the purpose of controlling DSV in the DSV control part and an algorithm selection signal As or Bs are inputted from outside and/or a peripheral circuit to a DSV control part to select a desired one of the algorithms A and B with the algorithm selection signal. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention converts a p-bit input data word into at least one code word of q bits (where q> p) using a plurality of encoding tables, and When at least one or more codeword strings are generated by connecting the one or more codewords to a codeword string previously encoded by satisfying a run length restriction rule, DS
A desired algorithm is selected from a plurality of algorithms prepared in advance for V control, and the desired algorithm is controlled so that the absolute value of DSV is minimized for one or more codeword strings. And a digital modulation method.

[0002]

2. Description of the Related Art CD-R / RW, DVD-R / RW, D
When an information signal is recorded on a recording medium such as an optical disk represented by VD-RAM or the like, the information signal to be recorded is recorded on the optical disk for the reason of generating a servo signal or a reference clock. It is necessary to modulate the data into a modulation signal suitable for recording and generally record at least one p-bit input data word using at least one q-bit (where q> p) using a plurality of encoding tables. When converting at least one or more codewords to each other and connecting one or more codewords to the codeword string encoded before this codeword by satisfying the run length restriction rule to generate at least one or more codeword strings, For at least one or more codeword strings, DSV (Dig
After selecting the code word having the smallest absolute value of ital Sum Value), the modulated signal obtained by modulating the code word string having the smallest absolute value of DSV is recorded on a recording medium such as an optical disk.

As a typical one of such modulation methods, a minimum run length (= also called a minimum inversion interval)
Is 3T (T = channel bit period), and the maximum run length (= maximum inversion interval is also referred to) is 11T. For example, EFM used for CD (compact disc) and MD (mini disc). (Eight to Fou
rteen Modulation: EF used for 8-14 modulation) and DVD (Digital Versatile Disc)
There are M + (8-16 modulation) system and the like.

First, in EFM modulation used in CDs (compact discs), the minimum run length of input 8-bit (1 byte) digital data is 3
T, the maximum run length is converted to a 14-bit run length limited code (code word) that satisfies the run length limit of 11T, and DS is provided between the converted code words.
An EFM-modulated signal is generated by adding a connection bit of 3 bits for V (Digital Sum Value) control and for holding the run-length limiting rule.

In this case, when the minimum run length is 3T, the number of "0" s between the logical values "1" and "1" in the code word is at least d = 2, while the maximum value is maximum. When the run length is 11T, a maximum of k = 10 "0" s are included between the logical values "1" and "1" in the codeword. And
Even if the connecting bits of 3 bits provided for DSV control and for maintaining the run length limiting rule in order to reduce the direct current component and low frequency component of the modulated signal are connected between the 14 bit code words, the EFM modulation is performed. The signal satisfies a run length limiting rule RLL (d, k) = RLL (2,10) with a minimum run length of 3T and a maximum run length of 11T.

Next, a DVD (digital versatile
In the EFM + system used for the disk), the input 8-bit digital data is converted into a 16-bit code word, and the code words are directly connected without using connection bits, and the minimum run length is 3T, Run length restriction rule RLL (2,1 with a maximum run length of 11T
It is a method of performing 8-16 modulation so as to satisfy 0).

Generally, according to the above-mentioned EFM (8-14 modulation) system or EFM + (8-16 modulation) system,
When generating a modulated signal for recording on an optical disc,
Controls low frequency components. When the low-frequency component is included in the modulation signal, in an optical disc in which data is recorded in a concavo-convex pit row, the low-frequency component leaks into the servo signal of the optical pickup during reproduction, which adversely affects the servo. Is.

At this time, the control of the low frequency component of the modulation signal is generally performed by the CD within one code word obtained by converting the input data word.
SV (Codeword Digital Sum) is calculated, and DSV (Digital Sum Valu
The absolute value of e) is controlled to be the minimum.

Here, FIGS. 3A and 3B are diagrams for explaining the calculation of the DSV. The above CDS (Codewor
d Digital Sum) is equivalent to DSV in one code word, and DSV (Digital Sum Value) is shown in FIG.
As shown in (b), when the waveform after the NRZI (Non Return Inverted) conversion from the start time of the code word string to the current time is H (high) level, it is set to “1” (positive polarity), and L
It is an integrated value integrated as "-1" (negative polarity) at the (low) level. Here, an example is shown in which the current codeword shown on the right side is encoded and connected to the codeword shown on the left side. At this time, in the NRZI conversion, since the polarity is inverted with the data bit “1”, even if the code word has the same bit pattern, the bit immediately before the connection is “1” as shown in FIG. 3A. And the case of Figure 3
As shown in (b), the waveform is inverted when "0".

Here, as an example of the conventional example, the modulation rule of the 8-16 modulation system will be briefly described.

FIG. 4 is a diagram for explaining a plurality of coding tables used in the 8-16 modulation system. (A) shows a main table, (b) shows a sub table, and FIG. 5 shows 6 is a flowchart for selecting a codeword that suppresses a low frequency component by using the plurality of encoding tables shown in FIG. 4.

As shown in FIGS. 4A and 4B, 8-1
A plurality of encoding tables used in the 6 modulation method are for converting p-bits = 8-bit data symbols (= input data words) to be recorded into q-bits = 16-bit code words (= code words). Is. In the following description, the input data word will be described as a data symbol and the code word will be described as a code word in accordance with the illustration of the encoding table.

The plurality of coding tables described above are shown in FIG.
The main table shown in FIG. 4A and the sub table shown in FIG. 4B are prepared. The main table is
It is composed of 0 to 255 data symbols represented by 8 bits and a 16-bit codeword corresponding to each data symbol. On the other hand, the sub-table is composed of 0 to 87 data symbols represented by 8 bits and a 16-bit codeword corresponding to each data symbol.

Further, in the main table and the sub-table, code words are present in each of the states St1, State St2, State St3 and State St4 which are the state information corresponding to each data symbol. Further, a code called a next state is added to the right of each codeword. This instructs to use the codeword specified in the next state after this codeword.

Next, the operation of selecting a codeword that suppresses the low frequency component using the main table and the sub-table shown in FIGS. 4A and 4B will be described with reference to FIGS. 5 will be described together.

As shown in FIG. 5, first, in step S1, immediately after the start of conversion, it is determined whether or not the area to be processed is the head of a sector (or the head of an ECC block). If processing is performed for each sector head, DVD-R
In the case of AM, DVD-R and DVD-RW are processed not for each sector but for every 16 sectors which are 1 ECC (error correction code) block.

Here, if it is the beginning of the sector (or the beginning of the ECC block) (in the case of YES), "0" is set as the initial value of DSV in step S2, and the process proceeds to step S3. On the other hand, when it is not the head of the sector (or the head of the ECC block) (in the case of NO), step S2 is skipped and the process proceeds to step S3.

Next, in step S3, it is determined whether or not the number of data symbols (= input data word) to be recorded is 87 or less. If the number of data symbols is 87 or less (in the case of YES), the process proceeds to step S4. On the other hand, if the data symbols are greater than 87 (in the case of NO), the process proceeds to step S9 described later.

Next, in step S4, since it is determined that the number of data symbols is 87 or less in step S3, each data symbol is converted into a codeword (= codeword) using the main table and the sub-table, and the step is performed. Proceed to S5. At this time, which of the states St1 to St4 to use in the main table and the sub table is determined based on the next state information determined at the previous codeword conversion. The next state is set to "1" at the first data selection after conversion is started.
Is set to.

Next, in step S5, NRZI conversion is performed on each codeword selected based on the next state information in the main table and the subtable for the data symbol. At this time, the least significant bit of the codeword before connecting to each selected codeword is “0”.
NRZI conversion is performed after confirming whether or not it is "1". Then, the CDS (DSV obtained for each codeword) is calculated from the NRZI-converted codeword converted in the main table, and this is designated as CDSmain. Similarly, the codeword converted by the sub table is converted into NRZI
From the converted data, CDS (DS obtained for each codeword
V) is calculated and this is designated as CDSsub. And the CD
After obtaining Smain and CDSsub, the process proceeds to step S6.

Next, in step S6, for each codeword converted using the main table and the sub-table, the current codeword and the codeword sequence (= code sequence) encoded before this are generated. The run length at the connection part is calculated, and the run length is a predetermined limit rule (2T or more and 11 or less), in other words, the run length limit rule RLL (d,
It is determined whether or not k) = RLL (2,10) is satisfied. Then, if the run length satisfies the predetermined limit rule (YES), the process proceeds to the next step S7, while if the run length does not meet the predetermined limit rule (NO), the step After discarding the current codeword in S8, the process proceeds to step S11.

Next, in step S7, the absolute value of the value obtained by adding CDSmain to the DSV value accumulated in the codeword string so far and the value obtained by adding CDSsub to the DSV accumulated in the codeword string so far Compare with the absolute value of. If the absolute value of the value obtained by adding CDSmain to the DSV so far is less than or equal to the absolute value of the value obtained by adding CDSsub to the previous DSV (in the case of YES), the process proceeds to step S11. The absolute value of the value obtained by adding CDSmain to DSV is the CDSsub to the existing DSV.
When it is larger than the absolute value of the value added with (when NO)
To proceed to step S13.

On the other hand, in step S9, since the data symbol is determined to be larger than 87 in step S3, the data symbol is converted into a codeword using the main table, and the process proceeds to step S10. In this case, which state St1 to St4 of the table to use in the main table is determined based on the next state information determined at the previous codeword conversion. The next state is set to "1" at the first data selection after the conversion is started.

Next, in step S10, the CDS (DSV obtained for each codeword) is calculated from the NRZI-converted codeword converted in the main table, and this is designated as CDSmain. In addition, NRZI conversion is performed here and C
When calculating DSmain, NRZI conversion is performed after checking whether the least significant bit of the codeword before connection is "0" or "1". And CDSmain
After obtaining, the process proceeds to step S11.

Next, step S11 and step S12
Is the case where the conversion is performed using the main table. In step S11, C is converted to the conventional DSV in step S7.
A new DSV is obtained by adding DSmain, or a new DSV is obtained by adding the previous DSV to the CDSmain calculated in step S10, and then the codeword converted in the main table is obtained in step S12. Select as a codeword to be recorded, step 1
Go to 5.

On the other hand, steps S13 and S14
Indicates a case where conversion is performed using a sub table. In step S13, the CD is converted to the DSV used in step S7.
A new DSV is obtained by adding Ssub, and thereafter, the codeword converted in the subtable is selected as the codeword to be recorded in step S14, and step 15
Proceed to.

Next, in step S15, step S1
After processing 2 or step S14, 1 sector (or 1
It is determined whether or not all the data symbols to be written in the ECC block) have been processed. And
The above processing (S1 to S1) is completed until processing is completed for all data symbols for one sector (or one ECC block)
By repeating S15), modulation is performed while suppressing the low frequency component of the NRZI signal.

[0028]

By the way, the codeword selection algorithm described in the conventional example with reference to FIG. 5 is merely an example, and there are actually a plurality of algorithms.

FIG. 6 is a diagram for explaining the algorithm A when the DSV control is simply performed, and FIG. 7 is a diagram for explaining the algorithm B when the DSV control is finely performed.

FIG. 6 shows an algorithm relating to only the codeword selection part in the above-mentioned conventional example. This is Algorithm A. The algorithm shown in FIG. 7 is a more complicated version of the above-mentioned algorithm, but it is intended to further suppress the DSV value than the above-mentioned algorithm. This is Algorithm B.

First, the algorithm A shown in FIG. 6 will be briefly described. It is asked whether the data symbol (= input data word) is 87 or less. If the data symbol is 87 or less, the main table (Main) and Data symbols are converted into codewords (= codewords) using the sub-table (Sub), and the absolute value of DSV is compared between the code word on the main table side and the code word on the sub-table side. And the absolute value of DSV is Main
If <Sub, the main table side code word is selected, if Main> Sub, the sub table side code word is selected, and if Main = Sub, the main table side code word is selected.

On the other hand, when the data symbol is larger than 87, the main table (Main) is used, and the state in the main table is St2orSt based on the information of the next state specified at the immediately preceding code conversion.
Ask whether it is 3 or the state is St1orSt4. When it is St2orSt3, the codeword of St2orSt3 in the main table is selected as it is. The state is St1orS.
If it is t4, the run length is inquired. If the run length is satisfied in the state St1, the code word of the state St1 is selected as it is, and the run length is not satisfied in the state St1 and the run length is satisfied in the state St4. If so, the code word of the state St4 is selected as it is, and if the run length is satisfied in both the states St1 and St4, the absolute value of DSV is compared. And the state St
If the run lengths of both 1 and St4 are satisfied and the absolute value of DSV is State St1 <State St4, the state S
The codeword of t1 is selected. If the state St1> state St4, the codeword of the state St4 is selected, and if the state St1 = state St4, the codeword of the state St1 is selected.

Next, the algorithm B shown in FIG. 7 will be briefly described. It is asked whether or not the data symbol (= input data word) is 87 or less. When the data symbol is 87 or less, the main table (Main). Then, the data symbol is converted into a codeword (= codeword) using the subtable (Sub), and the absolute value of the DSV is compared between the codeword on the main table side and the codeword on the subtable side. And the absolute value of DSV is Main
If <Sub, select the code word on the main table side, if Main> Sub, select the code word on the sub table side. Further, if Main = Sub, the DSV is the same, unlike the case shown in FIG. , Or the last D
The process branches when the SV is 0 and the DSV is different and the immediately preceding DSV is not 0. Here, in the case of the above term, the number of times of inversion when NRZI conversion is performed is asked,
If the number of inversions is Main> Sub, the codeword on the main table side is selected. If the number of inversions is Main <Sub, the codeword on the subtable side is selected. If the number of inversions is Main = Sub, the codeword on the main table side. Is selected. On the other hand, if it is the above item, DS
The polarity of V is queried. If the polarity is inverted by Main selection, the code word on the main table side is selected, and if the polarity is inverted by Sub selection, the code word on the sub table side is selected.

On the other hand, when the data symbol is larger than 87, the main table (Main) is used, and the state in the main table is St2orSt based on the information of the next state designated at the immediately preceding code conversion.
Ask whether it is 3 or the state is St1orSt4. When it is St2orSt3, the codeword of St2orSt3 in the main table is selected as it is. The state is St1orS.
If it is t4, the run length is inquired. If the run length is satisfied in the state St1, the code word of the state St1 is selected as it is, and the run length is not satisfied in the state St1 and the run length is satisfied in the state St4. If so, the code word in the state St4 is selected as it is, and if the run length is satisfied in both the states St1 and St4, the absolute value of DSV is compared. And the state St
If the run lengths of both 1 and St4 are satisfied and the absolute value of DSV is State St1 <State St4, the state S
When the codeword of t1 is selected and the state St1> the state St4, the codeword of the state St4 is selected, and when the state St1 = state St4, the state shown in FIG.
Different from the case shown in (1), the process branches into the case where the DSV is the same or the immediately preceding DSV is 0, and the case where the DSV is different and the immediately preceding DSV is not 0. Here, in the case of the above term, the codeword of the state St1 is selected, while in the case of the above term, the polarity of the DSV is queried.
If the code word of t1 is selected and the polarity is inverted by the selection of state St4, the code word of state St4 is selected.

Among the algorithms A and B described above, the algorithm A has the merit that it is simple and can be easily made into a circuit, but depending on the pattern of the input data symbol string (= input data word string), the DSV value May be larger than necessary in the positive or negative direction.

On the other hand, the algorithm B can finely control the DSV control as compared with the algorithm A, which is by far the most advantageous in terms of suppressing the DSV, but since the circuit becomes complicated, the overall power consumption etc. There is also a demerit such that

Therefore, the present invention has been made in view of the above-mentioned prior art, and DSV is applied to an optical disc such as a DVD-R or a DVD-RW that may be additionally recorded.
Suddenly changes, causing a momentary fluctuation of the DC component, making the servo unstable and suppressing the power consumption of the device as much as possible. The purpose is to provide. A code that can solve the problem that the auto slice cannot follow when the reproduced signal is binarized with the symbols "0" and "1" due to the rapid change of the DC component, and can record accurate data. An object of the present invention is to provide a digital modulation device and a digital modulation method for generating words.

[0038]

SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and the first invention uses a plurality of coding tables to convert a p-bit input data word into q bits (where q > P) to at least one or more codewords, and at least one of these codewords is connected to a codeword string encoded before this codeword satisfying a run length restriction rule. When the above code word strings are generated, DSV (Digital
In a digital modulation device configured to obtain a modulated signal by modulating the code word sequence having the minimum absolute value of DSV by selecting the code word having the minimum absolute value of Sum Value) by the DSV control unit, DSV in the DSV control unit
A plurality of algorithms are prepared in advance for control, and an algorithm selection signal is externally and / or peripherally supplied to the DS
A digital modulation device, characterized in that a desired algorithm is selected from the plurality of algorithms by inputting to a V control unit and by the algorithm selection signal.

A second aspect of the present invention is the digital modulation device according to the first aspect, wherein the algorithm selection signal is the characteristics and type of a recording medium for recording the modulation signal.
Alternatively, the digital modulation device is set based on power consumption of the digital modulation device or a preset reference value of the DSV.

Furthermore, the third invention converts a p-bit input data word into at least one code word consisting of q bits (where q> p) using a plurality of encoding tables, and The at least one or more codewords are generated when at least one or more codewords are connected by satisfying a run length restriction rule with a codeword string that is encoded before this at least one or more codewords. DSV (Digital S
(um Value), the code word string having the smallest absolute value is selected, and then the code word string having the smallest absolute value of DSV is modulated to obtain a modulated signal. A plurality of algorithms are prepared in advance for DSV control when controlling the DSV, and an algorithm selection signal is input from an external and / or peripheral circuit,
In the digital modulation method, a desired algorithm is selected from the plurality of algorithms by the algorithm selection signal.

[0041]

BEST MODE FOR CARRYING OUT THE INVENTION An embodiment of a digital modulation apparatus and a digital modulation method according to the present invention will be described in detail below with reference to new FIGS. 1 and 2 and FIGS. 3 to 7 used previously. explain.

FIG. 1 is a block diagram showing a digital modulator according to the present invention.

The digital modulator 10 according to the present invention shown in FIG. 1 comprises p-bit data symbols (= input data words) Ds of q bits (where q> p) using a plurality of encoding tables. At least one or more codewords (= codewords) Cd are converted into a codeword sequence (= codeword sequence) and a run length limiting rule, which are coded before the one or more codewords Cd. The code word Cd that minimizes the absolute value of DSV (Digital Sum Value) for at least one or more codeword strings when the connection is satisfied to generate at least one or more codeword strings. After selecting by DS
The modulation signal Mo obtained by modulating the codeword string having the minimum absolute value of V is used as the CD-R / RW, DVD-R / RW, D
When recording on a recording medium (not shown) such as an optical disk represented by VD-RAM or the like, a desired algorithm can be selected from a plurality of algorithms prepared in advance for DSV control. ing.

As shown in FIG. 1, the digital modulator 10
Controls the ROM 13 when a data symbol (= input data word) Ds to be converted is input, and at least one or more corresponding to the input data symbol Ds. The ROM controller 12 that reads out the code data (= code word) Cd from the plurality of encoding tables stored in the ROM 13 and the information of the next state Ns are input / output, and at least one or more code data Cd is D
A state / codeword selector 14 for selecting the final SV-controlled codeword Cd, and a run length determination circuit 1 for DSV controlling at least one or more code data Cd read from the ROM 13 during 8-16 modulation.
5, NRZI conversion / DSV operation circuit 16, DSV register 17, DSV comparison circuit 18 DSV control unit 1 having
9 and a DSV reference value determination circuit 2 provided as necessary
0 and N for NRZI conversion of the final codeword Cd selected by the state / codeword selector 14
An RZI conversion circuit 21 and a parallel / serial conversion circuit 22 that performs parallel / serial conversion of the NRZI converted NRZI signal Nr and outputs a modulation signal Mo.

In this embodiment, as shown in FIG.
Using the main table and the sub-table described using (b), the p-bit data symbol Ds is converted into at least one or more codewords Cd consisting of q bits, and one or more codewords Cd are converted. DSV of one or more codeword strings when at least one codeword string is generated by directly connecting the codeword string coded before this and satisfying the run length restriction rule.
The case of 8-16 modulation in which the absolute value of is controlled to be the minimum value will be described. However, the present invention is not limited to this.
Any modulation method can be applied as long as a desired algorithm can be selected from a plurality of algorithms for DSV control when converting to d.

The timing generation circuit 11 described above outputs the timing control signal Tm for controlling the processing timing of each block to the ROM according to the control command CTL from the outside.
Controller 12, state / codeword selector 1
4, NRZI conversion / DSV operation circuit 16, DSV register 17, NRZI conversion circuit 21, and parallel / serial conversion circuit 22 respectively.

The conversion work is started, and the ROM controller 12 stores the value of the data symbol (= input data word) Ds to be converted and the state / codeword selector 14 in the ROM controller 12.
Then, the information of the next state Ns determined at the previous conversion is input. At this time, the information of the next state Ns input from the state / codeword selector 14 to the ROM controller 12 is set to "1" at the time of the first data selection after the start of conversion.

The ROM controller 12 described above notifies the ROM 13 of the value of the data symbol Ds and the information of the next state Ns which are input here. This ROM1
Reference numeral 3 stores information on the main table and sub-table shown in FIGS. 4A and 4B, and the main table is stored according to the value of the data symbol Ds and the information of the next state Ns notified from the ROM controller 12. And / or at least one codeword (= codeword) Cd is selected from the sub-table, and the next state N added to the selected one or more codewords Cd is selected.
The information of s is also read and transmitted to the ROM controller 12.

The ROM controller 12 stores at least one codeword Cd selected from the ROM 13 in the state / codeword selector 14 and the DSV controller 1.
9 to the run length determination circuit 15 and the NRZI conversion / DSV operation circuit 16 and outputs the information of the next state Ns added to the selected one or more codewords Cd to the state / codeword selector 14. ing.

Next, the DSV control section 19 having the run length determination circuit 15, the NRZI conversion / DSV operation circuit 16, the DSV register 17, and the DSV comparison circuit 18 has at least one code input from the ROM controller 12. The control is performed so that the absolute value of DSV becomes the minimum with respect to the word Cd.

The algorithm selection signal As or Bs, which is the main part of the present invention, is input to the above-mentioned DSV control section 19 from an external controller (not shown) and / or a peripheral circuit.

The above-described algorithm selection signal As is a signal for selecting the algorithm A whose DSV control is simple as described above with reference to FIG. 6, while the algorithm selection signal Bs is described above with reference to FIG. As described above, the DSV control is a signal for selecting the complicated algorithm B, and the DSV control unit 1 selects one of the algorithms A and B by the algorithm selection signal As or Bs.
Switching inside 9. At this time, the algorithm A and the algorithm B are preliminarily prepared in hardware in the DSV control unit 19, but not limited to this, other algorithms may be considered. It is also possible to increase the number of selections so that the above algorithm can be selected. Further, the DSV control unit 19 may be configured not only as a hardware configuration using electronic circuit components but also as a software configuration using a part of a program.

When one of the algorithms A or B is selected by the algorithm selection signal As or Bs from the external controller, the selection of these algorithms is arbitrary and the digital modulation incorporating the circuit according to the present invention. It may be fixed in consideration of the power consumption of the device 10, or may be switched depending on the characteristics and type of the recording medium (not shown) mounted in the digital modulation device 10.

On the other hand, the algorithm selection signal As or Bs
In the case where is obtained from the peripheral circuit in the digital modulation device 10, the DSV reference value determination circuit 20 may be provided as necessary. The DSV reference value determination circuit 20 determines whether or not the DSV value of the final codeword sequence determined by the DSV comparison circuit 18 exceeds a preset DSV reference value,
By inputting the algorithm selection signal As or Bs to the DSV control unit 19 when the final DSV value exceeds the DSV reference value, either one of the algorithms A or B can be selected. At this time, which one is selected when the final DSV value exceeds the DSV reference value may be set in advance.

As described above, the algorithm selection signal As or Bs is the characteristic or type of the recording medium (not shown) for recording the modulation signal Mo described later, or the digital modulation device 1.
It is set based on the power consumption of 0 or a preset reference value of DSV.

Next, in the run length determination circuit 15 in the DSV control unit 19, at least one or more codewords Cd converted with respect to the data symbol Ds are connected to the codeword string encoded before this. At this time, the run length at the connection portion is calculated, it is determined whether or not the run length satisfies a predetermined limit (2 or more and 11 or less), and the run length determination signal Ru is output to the DSV comparison circuit 18.

Next, in the NRZI conversion / DSV operation circuit 16 in the DSV control section 19, at least one or more code words Cd converted from the data symbols Ds are NRZI converted and then at least one or more. The CDS value (DSV value obtained for each codeword) of each codeword Cd is calculated, and the CDS value and DSV are calculated.
The latest DSV value is calculated from the DSV integrated value up to the previous processing input from the register 17, and is output to the DSV comparison circuit 18. As a result, the data symbol Ds
At least one codeword C converted to
NRZI conversion / DSV operation circuit 16 is the result of calculating the DSV of at least one codeword string after NRZI conversion by connecting d to the codeword string encoded before this and satisfying the run length restriction rule. To D
It is output to the SV comparison circuit 18.

The operation of NRZI converting the codeword Cd by the NRZI converting / DSV calculating circuit 16 has a function substantially similar to that of the NRZI converting circuit 21 described later, but the circuit is NRZI converting circuit. Although it is configured a little different from 21, it may be configured as a DSV arithmetic circuit (16) when it is configured to also serve as the NRZI conversion circuit 21 described later herein.

Next, in the DSV comparison circuit 18, the run length determination signal Ru input from the run length determination circuit 15 and NR
The codeword Cd in the codeword sequence having the smallest absolute value of DSV is calculated from one or more DSV values calculated from at least one codeword sequence input from the ZI conversion / DSV calculation circuit 16. The selected codeword specifying signal CdT corresponding to the final codeword Cd selected here is output to the state / codeword selector 14. Further, the DSV comparison circuit 18 sets the final DSV value by the specified codeword Cd as the DSV register 17. DSV reference value determination circuit 2 provided as necessary
It outputs to 0.

Next, the DSV register 17 is a circuit that holds the DSV integrated value up to the previous processing. The DCC switching signal S or L is input to the DSV register 17 from an external controller. The DCC switching signal S described above is a signal for switching to the simple DCC system, while the DCC switching signal L is a signal for switching to the look ahead system.

Here, the simple DCC method resets the DSV value for each head of the sector (or the head of the ECC block). On the other hand, in the look-ahead method, the DSV value is not reset for each unit, but the selection of the codeword Cd is temporarily suspended during the DSV control and the absolute value of the DSV is reduced at the next time. In addition, the reset of the DSV value is suspended until an appropriate time.

The DSV initial value set in the DSV register 17 at the start of the conversion process is "0", which is the same in the simple DCC system and the look ahead system. When the conversion process is started, the DSV register 17 changes the final DS input from the DSV comparison circuit 18.
The V value is held as the DSV integrated value until the next codeword Cd is determined, and this DSV integrated value is output to the NRZI conversion / DSV operation circuit 16 described above.

Next, the state / codeword selector 1
4, at least one or more codewords Cd input from the ROM controller 12 according to the codeword specifying signal CdT input from the DSV comparison circuit 18,
One codeword Cd specified from at least one or more next state codes Ns corresponding to this
The ROM controller 12 selects 1 and outputs the code word Cd specified here to the NRZI conversion circuit 21, and outputs the next state code Ns added to the specified code word Cd at the time of inputting the next data symbol Ds. Output to.

Next, in the NRZI conversion circuit 21, the codeword Cd specified by the state / codeword selector 14 is converted into the NRZI signal Nr, and the parallel / parallel signal is converted.
Output to the serial conversion circuit 22.

Next, in the parallel / serial conversion circuit 22, the N input in parallel from the NRZI conversion circuit 21 is input.
The RZI signal Nr is converted to serial and output as a modulation signal Mo. After this, the parallel / serial conversion circuit 2
The modulated signal Mo output from the No. 2 is recorded on a recording medium (not shown) such as an optical disc.

Next, the operation of selecting algorithm A or B when performing 8-16 modulation using the digital modulation method according to the present invention will be described with reference to FIGS.

FIG. 2 is a flow chart for explaining the operation of selecting the algorithm A or B using the digital modulation method according to the present invention.

The digital modulation method according to the present invention is the same as the digital modulation apparatus 10 according to the present invention described above with reference to FIG.
Applied to.

In the digital modulation method according to the present invention shown in FIG. 2, conversion is started by the external control command CTL, and the area to be processed in step S21 is the head of the sector (or the head of the ECC block). Determine if there is. Here, the beginning of the sector (or ECC
If it is the beginning of the block (if YES), the process proceeds to step S22, while the beginning of the sector (or EC
If it is not (the beginning of the C block) (NO), steps S22 and S23 are skipped and the process proceeds to step 24.

Next, in step S22, step S2
Since it is determined in 1 that it is the head of the sector (or the head of the ECC block), whether the conversion process is performed by the simple DCC method or the look ahead method is performed.
It is determined by the DCC control signal S or L input from an external controller (not shown). Here, when the DCC switching signal S is input (in the case of S), the simple D
Since it is the CC system, "0" is set as the initial value of DSV in step S23, and the process proceeds to step S24.
On the other hand, when the DCC switching signal L is input (in the case of L)
Since the look-ahead method is used in the field, step S2
Skip 3 and go to step S24.

Next, in step S24, it is determined whether the algorithm A (FIG. 6) having a simple DSV control or the algorithm B (FIG. 7) having a complicated DSV control is selected by the external controller and / or the peripheral. It is determined by the algorithm selection signal As or Bs input from the circuit. Here, when the algorithm selection signal Aa is input (in the case of As), simple DSV control is performed on at least one or more codewords Cd obtained by converting the data symbols Ds by using the algorithm A in step S25. It is carried out. On the other hand, when the algorithm selection signal Bs is input (in the case of Bs), the algorithm B is used in step S26 to perform fine DSV control on at least one or more codewords Cd obtained by converting the data symbols Ds. Is going.

Next, in step S27, the DSV control is performed by the algorithm A or B to execute the codeword Cd.
After selecting, it is determined whether or not processing has been performed on all data symbols to be converted. Then, by repeating the above processing (S21 to S27) until the processing is completed for all the data symbols to be converted,
The modulation is performed while suppressing the low frequency component of the NRZI signal. Note that, as described above, the number of algorithms prepared in advance in the DSV control unit 19 is not limited to the two given in the embodiment, and the optimum one is selected from three or more algorithms by adding other algorithms. It is also possible to do so.

[0073]

According to the digital modulation apparatus and the digital modulation method according to the present invention, which have been described in detail above, the DSV is applied to at least one code word obtained by converting the input data word using a plurality of coding tables. At the time of control, a plurality of algorithms prepared in advance for DSV control are switched by an algorithm selection signal input from an external and / or peripheral circuit, so that a modulation signal optimal for the characteristics and type of recording medium, power consumption of the device, etc. Can be generated. Further, it is possible to minimize the instability of the servo caused by the sudden change of the DSV value and the instantaneous variation of the DC component. Also, due to a sudden change in the DC component, the reproduction signal is changed to the symbol "0" and "1"
It is possible to minimize the problem that the recorded correct data cannot be reproduced due to the fact that the auto slice cannot be followed when performing the binarization. For this reason, it is not necessary to strengthen the servo more than necessary, and it is effective in suppressing the power consumption of the entire apparatus.

[Brief description of drawings]

FIG. 1 is a block diagram showing a digital modulator according to the present invention.

FIG. 2 is a flow chart for explaining an operation of selecting algorithm A or B using the digital modulation method according to the present invention.

3A and 3B are diagrams for explaining the calculation of DSV.

[Fig. 4] Fig. 4 is a diagram for explaining a plurality of encoding tables used in the 8-16 modulation method, in which (a) is a main table and (b) is a sub-table.

FIG. 5 is a block diagram showing a plurality of encoding tables shown in FIG.
7 is a flowchart for selecting codewords that suppress low-frequency components.

FIG. 6 is a diagram for explaining an algorithm A when performing DSV control simply.

FIG. 7 is a diagram for explaining an algorithm B when performing DSV control finely.

[Explanation of symbols]

10 ... Digital modulator, 11 ... Timing generation circuit,
12 ... ROM controller, 13 ... ROM, 14 ... State / codeword selector, 15 ... Run length determination circuit,
16 ... NRZI conversion / DSV operation circuit, 17 ... DSV register, 18 ... DSV comparison circuit, 19 ... DSV control unit,
20 ... DSV reference value determination circuit, 21 ... NRZI conversion circuit, 22 ... Parallel / serial conversion circuit, Ds ... Input data word (data symbol), Cd ... Code word (code data), CdT ... Code word identification signal, Mo ... Modulation signal, Ns ... Next state, Nr ... NRZI signal, R
u ... Run length determination signal, Tm ... Timing control signal, A,
B ... Algorithm, As or Bs ... Algorithm selection signal, S or L ... DCCC switching signal, RLL ... Run length limiting rule.

Claims (3)

[Claims] 1. A p-bit input data word is converted into at least one or more code words of q bits (where q> p) using a plurality of coding tables, and the one or more codes are converted. When at least one or more codeword strings are generated by connecting words that have been encoded before this and satisfying the run-length restriction rule, DSV ( After selecting the code word with the minimum absolute value of (Digital Sum Value) by the DSV control unit,
In a digital modulator configured to obtain a modulated signal by modulating a code word string having a minimum absolute value of DSV, a plurality of algorithms for DSV control are prepared in advance in the DSV control unit, and external and / or A digital modulation device, characterized in that an algorithm selection signal is input from a peripheral circuit to the DSV control unit, and a desired algorithm is selected from the plurality of algorithms by the algorithm selection signal. 2. The digital modulation apparatus according to claim 1, wherein the algorithm selection signal is a characteristic or type of a recording medium for recording the modulation signal, power consumption of the digital modulation apparatus, or the preset value. A digital modulator characterized by being set on the basis of a DSV reference value. 3. A p-bit input data word is converted into at least one or more code words of q bits (where q> p) using a plurality of coding tables, and the one or more codes are converted. When at least one or more codeword strings are generated by connecting words that have been encoded before this and satisfying the run-length restriction rule, DSV ( Digital Sum Value), the code word having the minimum absolute value is selected, and then the code word string having the minimum absolute value of DSV is modulated to obtain a modulated signal. A plurality of algorithms are prepared in advance for DSV control when controlling the DSVs in a column, an algorithm selection signal is input from an external and / or peripheral circuit, and the plurality of algorithms are input by the algorithm selection signal. A digital modulation method characterized by selecting a desired algorithm from among rhythms.