JP2003167842A - Pci bus bridge circuit and transaction control method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To solve a problem that as the priority in performing the transaction is fixed, the transaction of low priority can not be performed when the processing of the transaction of high priority are frequently required. <P>SOLUTION: A PCI bus bridge circuit is composed of an arbitration block for arbitrating a bus to an agent, a transaction analyzing block for analyzing the contents of required transaction, a transaction holding block for accumulating the transaction, a first bus monitoring block for monitoring a use condition of a first bus, a transaction requiring block for outputting the transaction requirement order to the transaction holding block, and a priority changing block for counting the number of times of processing the transaction, and temporarily changing the priority, to perform the transaction control to the first bus. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a PCI bus bridge circuit and a transaction control method.

[0002]

2. Description of the Related Art In a PCI bus bridge circuit connected to two different buses, one of which is a PCI bus for controlling data communication between the buses, from an agent on the PCI bus to an agent on the other bus. The priority of transaction execution is fixed in the circuit that stores and executes transactions.

[0003]

However, since the priority of transaction execution is fixed, when high priority transaction processing is frequently generated, low priority transaction processing remains stored. It was in a state and processing was not executed.

It is an object of the present invention to provide a PCI bus bridge circuit and a transaction control method capable of executing a high priority transaction preferentially and effectively using the PCI bus.

[0005]

An arbitration block for performing bus arbitration for an agent on a PCI bus, a transaction analysis block for analyzing the contents of a requested transaction, and a transaction accumulation block for accumulating a transaction and the other. A bus monitoring block for observing the bus usage state of the other, a transaction request block for issuing a transaction request command to the transaction accumulation block, and a priority change block for changing the bus priority from the bus usage status The transaction execution is controlled by the priority determination based on the transaction contents from the PCI bus bridge circuit and the PCI bus agent and the priority temporarily changed from the status of each transaction processing. It is carried out.

[0006]

BEST MODE FOR CARRYING OUT THE INVENTION (Embodiment 1) PCI of the present invention
The bus bridge circuit will be described with reference to FIG. Figure 1
FIG. 3 is a system configuration diagram of the present invention, and the second bus is a PCI bus for explanation.

The PCI bus bridge circuit 100 of the present invention includes an arbitration block 104 for arbitrating bus requests from the agents 109, 110, 111 and 112 on the PCI bus 114, and a transaction from the agent. A transaction analysis block 103 for analyzing the contents, a transaction accumulation block 105 for accumulating an arbitrary number of transactions, a first bus monitoring block 101 for observing the usage status of the first bus 113, and the transaction accumulation. Transaction generation request for requesting block 105 to execute a transaction to agents 106, 107, 108 on the first bus 113 The lock 102, priority change block 1 which controls the arbitration priority change and transaction execution order of by counting the number of times execution of a transaction by each agent performed by the transaction generation request block 102
A configuration including 15 is adopted.

Next, the operation of this circuit having the above configuration will be described. Agent 1 on PCI bus 114
Arbitration block 1 when a bus right request is issued from 10, agent 111, or agent 112
04 performs arbitration, and the arbitration method at that time is performed according to the priority order arbitrarily assigned to the agent in advance.

Here, for the sake of explanation, it is assumed that the agent 109 has the highest priority, and the agent 110, the agent 111, and the agent 112 are assigned in this order.

The arbitration block 104 asserts a permission signal for the agent 110 based on the result of the arbitration, and gives the agent 110 the right to use the bus. Agent 110 given bus right
Sends a command and address information as an address phase to the PCI bus bridge circuit 100.

The PCI bus bridge circuit 100 receives this information by the transaction storage block 105. At this time, the usage status of the first bus 113 is observed by the first bus monitoring block 101, and when the transaction to the first bus 113 can be executed, the agent 1
The transaction from 10 is performed to the target agent on the first bus.

As a result of the observation by the first bus monitoring block,
When the first bus 113 is in use, the received information in the address phase is accumulated and is sent to the transaction analysis block 103 to newly receive byte enable and data information in the data phase. The transaction analysis block 103 is provided in the next stage of the arbitration block 104, holds information that the agent given the bus right by the arbitration block 104 is the agent 110 and information in the address phase, and adds the transaction execution order to the stored information. To do.

The transaction storage block 105 holds information on an arbitrary number of transactions until the transaction is completed. The first bus monitoring block 101 continues to observe the usage status of the first bus and sends the result to the transaction generation request block 102. When the transaction generation request block 102 recognizes that the first bus is released from the bus usage status information received from the first bus monitoring block when transactions are stored in the transaction storage block 105, the transaction generation block 102 1
05, a transaction execution command is issued to the target agent on the first bus 113 and the priority change block 115 is notified that the transaction processing of the agent 110 has been performed. Based on the notification information, the priority changing block 115 counts up the number of times the agent 110 processes the transaction. The upper limit of the number of times a transaction is processed can be arbitrarily changed, and the upper limit of the count is given such that the higher the priority is.

If a new transaction request is issued from the agent 109 while the transaction by the agent 110 is awaiting execution in the PCI bus bridge circuit 100, the first bus is not released yet, and the PCI bus bridge circuit 100 causes the agent 11 to execute a transaction request.
Transaction information is received as in the case of 0. At this time, the address phase information already accumulated in the transaction analysis block 103 is compared with the address phase information from the agent 109, and if the transaction from the agent 110 has a high priority, the agent 109 having a higher priority as an agent. So that the transactions in
The added execution order data is rewritten.

The transaction when the first bus is released is executed by the execution order data, and the number of transaction processes of each agent is counted up.
When the transaction processing count reaches the set upper limit, the priority changing block 115 sets the lowest priority to the agent whose processing count has reached the upper limit until the transaction processing from another agent already accumulated is executed. Change control to. When the processing by the agent, which has reached the upper limit of the number of processing due to the progress of transaction processing, is completed, the number of transaction processing is cleared to 0 and the priority order is returned to the original order.

By performing the above-mentioned configuration and control, it is possible to execute a transaction with a higher priority, and by temporarily changing the priority of a transaction that remains in an unexecuted state due to a low priority. Processing can be performed.

[0017]

As described above, by configuring the PCI bus bridge circuit and performing the above-mentioned transaction control, the PCI bus can be used efficiently, and the transaction to the first bus can be performed. By changing the execution order according to the priority order according to the usage status, it is possible to execute a transaction that is not processed due to a low priority while executing a more important transaction with priority.

[Brief description of drawings]

FIG. 1 PCI bus bridge circuit configuration diagram

FIG. 2 is a diagram showing a transaction control method.

[Explanation of symbols]

100 PCI bus bridge circuit 101 First Bus Monitoring Block 102 transaction generation request block 103 transaction analysis block 104 Arbitration Block 105 transaction accumulation block 106 Agent on the first bus 107 Agent on the first bus 108 Agent on the first bus 109 Agent on PCI bus 110 Agent on PCI bus 111 Agent on PCI bus 112 Agent on PCI Bus 113 First Bus 114 Second bus (PCI bus) 115 Priority change block 201 Transaction accumulation process 20 2nd transaction acceptance process 203 Transaction analysis / order determination process 204 Transaction execution process 205 Priority change process

Claims (2)

[Claims] 1. An arbitration block for performing bus arbitration for a bus request from an agent on a PCI bus, a transaction analysis block for analyzing contents of a requested transaction, and a transaction holding block for accumulating transactions. And a bus monitoring block for observing the usage status of the target bus, a transaction request block for issuing a transaction request command to the transaction holding block, and a priority for temporarily changing the priority from the usage status of the bus. A PCI bus bridge circuit comprising a rank changing block and functioning as a bridge function between buses having a PCI bus as a first bus or a second bus. 2. A transaction accumulation step of accumulating a transaction issued by an agent on the PCI bus, a next transaction acceptance step of accepting a transaction newly issued by another agent on the PCI bus, and priority of the agent or transaction. Transaction analysis and order determination process that analyzes the degree and transaction type and changes the transaction order according to the priority, and the transaction execution process and bus that executes from the transaction with the higher priority when the other bus is released A transaction control method characterized in that the transaction is performed by a priority order changing step of temporarily changing the priority order according to the situation.