JP2003167756A5 - - Google Patents

Description

[0008]
[Means for Solving the Problems]
The microcomputer logic development device of the present invention for achieving the above object is a device for developing the logic of a built-in microcomputer used by being incorporated in an electronic control unit, the first central processing unit performing logic processing, logic A first memory for storing data including the following programs, a first interface for communicating with an external device, and a first internal bus for connecting them:
Pseudo MCU peripheral device implementing peripheral devices of the microcomputer in the pseudo-software, a second block with at least a second interface for communicating with the outside, and a second internal bus for connecting these, An interface bus for connecting the first and second blocks is provided, and the first and second blocks and the interface bus are replaced with the embedded microcomputer to operate the logic.

[0009]
In addition, with this configuration as a first embodiment, the following two modifications are possible in which the electronic control unit controls the controlled object.
A first variant is an apparatus for developing the logic of a built-in microcomputer used by being incorporated in an electronic control unit for controlling a controlled object, the first central processing unit performing logic processing, a program of the logic A first block comprising at least a first memory for storing data including the first memory, a first interface for communicating with the outside, and a first internal bus for connecting the A second block comprising at least a pseudo microcomputer peripheral device realized by software in a pseudo manner, a second interface for communicating with the outside, and a second internal bus for connecting them; Interface bus that connects the blocks in the block, and control the operation timing of the simulated microcomputer peripheral device to realize the control status of the controlled object. The correction for the correction means comprises a second block is a logic development system of the microcomputer, characterized in that so as to operate the logic replaces the built-in microcomputer.
A second modification is an apparatus for developing the logic of an embedded microcomputer incorporated and used in an electronic control unit for controlling an object to be controlled, the first central processing unit performing logic processing, and a program of logic And a first block including at least a first memory for storing data including the first memory, a first interface for communicating with the outside, and a first internal bus for connecting them, A second block comprising at least a pseudo microcomputer peripheral device for simulating the device by software, a second interface for communicating with the outside, and a second internal bus for connecting them; And an interface bus for connecting the second block, and an interrupt for controlling interrupt processing to be performed to realize the control situation of the controlled object At least one of the control means first or second block comprises a logic development system of the microcomputer, characterized in that so as to operate the logic replaces the built-in microcomputer.
Also, based on these forms as a basic form, the second block has a processing capacity lower than that of the first central processing unit, and the second central processing unit for performing communication by the interface bus, and at least data used for communication. A second memory provided with a second memory for storing data, and a third block provided with an input / output circuit, the third block being connected to the second block, and A third form is possible that can be used in place of the control unit.

[0010]
Furthermore, the following forms are possible.
(1) A fourth mode in which a first timer is provided in the first block.
(2) A fifth mode in which the second memory includes a shared memory connected to the interface bus and an internal memory connected to the second internal bus.
(3) In the second block, the sixth embodiment is configured such that the pseudo microcomputer peripheral device can be added.
(4) The 7th form by which the 2nd block is further provided with the 2nd timer which performs time management.

[0033]
The microcomputer logic development device 20 of the present invention can be used by being directly connected to the vehicle 18 as described above, and operates under the control of the personal computer 24 to simulate various driving situations of the vehicle. By connecting to the driving condition generating device 23 of the vehicle that can be generated, it is possible to develop the logic of the built-in microcomputer for the electronically controlled engine even in the absence of the vehicle.

[0037]
The current performance of the microcomputer for engine control is about 64 MHz for CPU and about 1 Mbyte of memory, so it can be said that using a general-purpose one used for a personal computer etc. is a performance that is more than sufficient. It can be used any number of times over a period of time.

[0038]
Further, the core board 40 includes a CPU and a memory, and is a simulated microcomputer peripheral (FPGA: Field Programmable) corresponding to the PCI communication software 41 for communicating with the PCI bus 39 described above and the microcomputer peripheral resources 26 of the embedded microcomputer 2. And an internal bus 43 so that data can be exchanged with each other. The IF board 50 is provided with an ECU input / output circuit 51 corresponding to the ECU input / output circuit 28 of the ECU 1 and an ECU connector 29. The ECU input / output circuit 51 is made independent in units of standard circuit blocks and configured by a combination thereof, so that it is possible to flexibly cope with the change of the input / output circuit.

[0072]
In step 1520, a search is made to determine whether there is an interrupt C with the lowest interrupt priority. As a result of the search, if there is no interrupt C, the interrupt routine is ended, but if there is an interrupt C, the process proceeds to step 1521 to set an interrupt C clear request. Then, at step 1522, the routine of interrupt C is executed, and after this routine ends, the interrupt routine is ended.
(7) PCI communication processing load reduction method The processing of the ENG control application 31 can be coped with by improving the performance of the CPU board employed in the mother board 30, but the processing relating to PCI communication is restricted by the PCI protocol. , PCI communication processing load should be kept as low as possible. Here, when there is no interrupt event information, no accompanying interrupt processing occurs, so there is no need to transmit input information to the motherboard 30, and no new output request is generated, so the output request is made on the core board 40. There is no need to communicate to That is, PCI communication processing is not necessary.

[0076]
In step 1604, the output information is set, and in the next step 1605, the input information is set. In the next step 1606, it is determined whether there is any interrupt event. If there is no interrupt event, the value of the wait counter (waitcnt) is updated by 1 in step 1610 and this routine is ended. On the other hand, if there is any interrupt event, the process proceeds to step 1607. In this step 1607, the value of the wait counter (waitcnt) is cleared, and an interrupt request to the motherboard 30 is made in the subsequent step 1608. Then, in the next step 1609, the value (syncnt_m) of the communication synchronization counter monitor is updated by 1 and this routine is ended. The processing on the motherboard 30 side is the same as the processing described in FIG. 9 or FIG.
(8) Timer Processing Method In the ENG control application 31, in order to calculate the pulse output request using the compare function, the timer value is acquired in the arithmetic processing, and the pulse output request is calculated. Therefore, when making a timer value acquisition request, it is necessary to be able to refer to the correct timer value. On the other hand, in the present invention, the timer value information is in the core board 40 and needs to be acquired through the PCI bus 39 on the motherboard 30 side. However, since the PCI communication interval is 100 μs and longer than 1 μs, which is the timer counting interval, as described in the above-described embodiment, it is necessary to take measures to obtain an accurate timer value on the motherboard 30 side. It is.

Claims (25)

An apparatus for developing the logic of an embedded microcomputer to be used by being incorporated into an electronic control unit,
A first central processing unit that performs the logic processing, a first memory that stores data including a program of the logic, a first interface that communicates with the outside, and a first internal bus that connects these At least a first block provided;
Pseudo MCU peripheral device implementing peripheral devices of the microcomputer in the pseudo-software, a second block with at least a second interface for communicating with the outside, and a second internal bus for connecting these,
An interface bus connecting the first and second blocks;
A microcomputer logic development device characterized in that said logic is operated by replacing said microcomputer with said first and second blocks and an interface bus. An apparatus for developing a logic of a built-in microcomputer used by being incorporated in an electronic control unit for controlling a controlled object,
A first central processing unit that performs the logic processing, a first memory that stores data including a program of the logic, a first interface that communicates with the outside, and a first internal bus that connects these At least a first block provided;
A second block comprising at least a simulated microcomputer peripheral device for simulating the CPU peripheral device in the microcomputer by software, a second interface for communicating with the outside, and a second internal bus for connecting these. When,
An interface bus connecting the first and second blocks;
The second block includes correction means for controlling and correcting the operation timing of the simulated microcomputer peripheral device in order to realize the control situation of the controlled object;
A microcomputer logic development device, characterized in that the logic is operated by replacing the embedded microcomputer. An apparatus for developing a logic of a built-in microcomputer used by being incorporated in an electronic control unit for controlling a controlled object,
A first central processing unit that performs the logic processing, a first memory that stores data including a program of the logic, a first interface that communicates with the outside, and a first internal bus that connects these At least a first block provided;
A second microcomputer at least provided with a second microcomputer interface for communicating with an external, and a second internal bus for connecting the same. And the block
An interface bus connecting the first and second blocks;
At least one of the first and second blocks includes interrupt control means for controlling interrupt processing performed to realize the control situation of the controlled object,
A microcomputer logic development device, characterized in that the logic is operated by replacing the embedded microcomputer. The second block stores a second central processing unit having a processing capacity lower than that of the first central processing unit and performing communication by the interface bus, and at least data used for the communication. The microcomputer logic development device according to any one of claims 1 to 3, wherein the memory of (1) is provided. Furthermore, the electronic control unit is provided with a third block in which an input / output circuit is mounted, and the third block is connected to the second block, and can be used in place of the electronic control unit. The microcomputer logic development device according to any one of claims 1 to 4 . The microcomputer logic development device according to any one of claims 1 to 5, wherein a first timer is provided in the first block. It said second memory is a shared memory connected to the interface bus, according to any one of claims 4 to 6, characterized in that they are composed of an internal memory connected to said second internal bus Microcomputer logic development device. The microcomputer logic development device according to any one of claims 1 to 7 , wherein the pseudo microcomputer peripheral device is configured to be able to be added in the second block. The microcomputer logic development device according to any one of claims 1 to 8, further comprising a second timer for performing time management in the second block. The first memory is provided with a control application including a time-related processing application which is executed every predetermined time and a non-time-related processing application which is executed regardless of the time every occurrence of a predetermined event. ,
The first central processing unit is provided with a virtual interrupt controller function that performs at least time-based interrupt processing and non-time-based interrupt processing,
The first interface is equipped with communication software for transmitting and receiving at least data and interrupt event information through the interface bus,
The second central processing unit communicates with the first interface using the second memory and the second interface and with regard to the exchange of interrupt events and data through the interface bus,
5. The microcomputer logic development device according to claim 4 , wherein said pseudo microcomputer peripheral device is provided with an input function and an output function. 11. The microcomputer according to claim 10 , wherein said input function is an input port, a latch port, A / D conversion, and capture, and said output function is an output port, pulse output, compare, and serial. Logic development equipment. The second memory is provided with a shared memory connected to the interface bus,
11. The system according to claim 10, wherein said pseudo microcomputer peripheral device exchanges data between a time system processing application and a non-time system processing application of said first memory through said shared memory and said interface bus. Microcomputer logic development device described in. Wherein is provided a communication synchronization counter in the shared memory, this communication synchronization counter, claim 12, characterized in that taking the exchange of synchronization data between the pseudo microcomputer peripheral device and the non-time-based processing applications Microcomputer logic development device described in. The processing activation timing of the pseudo microcomputer peripheral device is arbitrary without fixing at a predetermined sampling cycle, and the next processing activation of the pseudo microcomputer peripheral device is completed when the processing of the non-time system processing application in the first block is completed. 14. The microcomputer logic development device according to claim 12 , wherein timing is used. If the time from the processing start timing of the pseudo microcomputer peripheral device to the end of the processing of the non-time system processing application in the first block exceeds the predetermined determination time, the pseudo microcomputer is forcibly The microcomputer logic development device according to claim 14 , wherein the processing of the peripheral device is started. The interrupt event generated in the pseudo microcomputer peripheral device is transmitted to the first block through the interface bus to perform the processing of the non-time system processing application, and the pseudo of the non-time system processing application is completed. The microcomputer logic development device according to claim 14 or 15 , wherein the processing start timing is next to that of the microcomputer peripheral device. The non-time system processing application sets priorities to interrupt events generated in the pseudo microcomputer peripheral device, and the interrupt events transmitted to the first block through the interface bus are in accordance with the priorities. The microcomputer logic development device according to any one of claims 14 to 16, wherein the non-time system processing application processes. The transmission of information to the first block through the interface bus may be omitted if there is no interrupt event generated in the pseudo microcomputer peripheral device . Microcomputer logic development device according to item 1 . In the non-time-based processing, when the timer value acquisition request, claim, wherein the timer value obtained at the interface bus, and correcting the timer value from the first timer in the first block The microcomputer logic development device according to any one of 14 to 18 . When the control application outputs a pulse output request using the compare function in the output function to the second block in response to an interrupt request from the second block, the control application outputs the compare function Select the general output port function provided on the pin and immediately output the immediate output, and select the compare output function provided on the output terminal of the compare function, set the output time and output level, and reserve the output 12. The microcomputer logic development device according to claim 11 , wherein at least one of timed outputs to be performed is output. With respect to the immediate output or the timed output from the control application, the pseudo microcomputer peripheral device in the second block can correspond to any combination of these outputs. 21. The microcomputer logic development device according to claim 20 . From the output request to the actual output by passing through the interface bus when the immediate output or the timed output from the control application is transmitted to the second block through the interface bus 22. The microcomputer logic development device according to claim 21 , wherein the delay time is corrected. It is determined whether the delay time from the output request to the actual output needs to be corrected or not according to the type of signal, and the correction is performed only in the case of the type of signal that needs correction. The microcomputer logic development device according to claim 22 , characterized in that The microcomputer logic development device according to any one of claims 5 to 23, wherein each of the first to third blocks comprises a general-purpose board. 25. The microcomputer logic development device according to any one of claims 1 to 24, wherein the microcomputer is for internal combustion engine control.