JP2003167730A - Instruction set variable microprocessor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a microprocessor provided with speed performance equal to that of a microprocessor and high flexibility that programmable logic has and capable of rewriting an instruction set to provide an SoC having such microprocessor. <P>SOLUTION: A control logic part of an instruction decoder and a part of a data path part are constituted by the programmable logic PL1 to rewrite the contents of the programmable logic in accordance with the instruction set. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a microprocessor capable of flexibly changing an instruction set on the user side, and a semiconductor integrated circuit in which such a microprocessor and peripheral circuits are integrated in one chip.

[0002]

2. Description of the Related Art Due to a great improvement in the degree of integration of semiconductor integrated circuits, a plurality of semiconductor chips (usually composed of a microprocessor chip and peripheral circuits such as interface circuits) have been formed on a printed circuit board. Integrate system into one chip (System-on-a
-Chip (SoC)) is now possible. Since the chip manufacturing cost is reduced and the printed circuit board can be downsized by the one-chip implementation, the system cost is reduced. In addition, since the inter-chip wiring on the printed circuit board is replaced by an intra-chip wiring that is orders of magnitude shorter than that, wiring capacitance is reduced, and as a result, low power consumption and high speed of the entire system can be achieved. Thus, So
C has many excellent features.

However, in the SoC, the combination of peripheral circuits required varies depending on the application used, so it is necessary to raise a dedicated mask pattern specialized for the application to manufacture the dedicated SoC. Therefore, (1) the design data in which the peripheral circuit to be integrated into one chip and the microprocessor are integrated is Ver.
A hardware description language (HDL: Hardware description) such as iHDL HDL or VHDL.
(Language) to perform logic synthesis to create circuit data, and (2) a step of creating a mask pattern from the circuit data and manufacturing a chip according to the mask pattern. The design process of (1) requires at least about one month, and the manufacturing process of (2) also requires about one month. Therefore, the period from the determination of the SoC specifications to the completion (TAT (Turn Round Time Tim)
e)) requires at least several months.

On the other hand, in a semiconductor chip typified by SoC, a significant reduction in TAT is an important theme as the product cycle is shortened due to fierce competition as typified by mobile phones and the like. Therefore, various methods have been proposed to reduce TAT.

The first method is IP (Intellecu).
reuse of the real property). Nikkei Electronics August 10, 1998, pp. 100
~ Pp. As shown in 109 (Reference 1), the interface specifications of the individual modules forming the SoC are made common, and the individual modules are designed in advance according to the common specifications. As a result, even when a combination of individual modules is changed and a new SoC is designed, most of the design data can be used and the design period can be shortened. However, this alone cannot shorten the period required for the manufacturing process.

The second method is the use of programmable logic that allows the user to change the circuit configuration of the chip. Programmable logic is FPGA (Field)
dProgrammable Gate Array),
PLD (Programmable Logic Device)
ce) etc., and there are several types. For the configuration of the programmable logic, for example, KLUWER
ACADEMIC CPUBLISHERS, ARCHI
TECHTURE AND CAD FOR DEEP
-SUBMICRON FPGAs, pp. 1-pp.
21 (Reference 2) and the like. LUT (Look
By rewriting the contents of the Up Table) and the configuration of the programmable wiring, it is possible to realize a logic circuit having various logic functions.

By integrating this programmable logic in the SoC, the user can program the peripheral circuits having various functions after the chip is manufactured. Thereby, the period required for the manufacturing process can be substantially shortened. For example, Nikkei Electronics January 15, 2001, p.
p. 153-pp. 160 (Reference 3) introduces an SoC in which an FPGA capable of realizing a logic circuit having a scale of hundreds of thousands of gates and a microprocessor core formed of a normal custom chip are integrated in one chip.

On the other hand, in a communication system application that uses a lot of digital signal processing in which SoC is expected to be widely used, there is a case where a general-purpose instruction set of a general-purpose processor core cannot obtain a sufficient processing capacity. Exists. For example, Nikkei Electronics March 2000 2000
7th issue, pp. 210-pp. 219 (reference 4),
An example has been introduced in which the processing speed can be improved 10 times or more by adding a special instruction that supports the rearrangement operation of the bit string used in the communication protocol processing. Similarly, as a processor whose instruction set can be changed, MORGANKAUFMANN PUBLISHE
RS, COMPUTER ARCHITECTURE
A QUANTITATIVE APPROACH, p
p. 238-pp. 245 (reference 5). In this conventional example, the control logic is composed of a kind of software called a microprogram, and the instruction set is changed by storing it in a rewritable RAM or the like.

[0009]

In the prior art disclosed in Document 3, only some peripheral circuits are programmable,
Since the processor core is composed of hard-wired logic, the user cannot change the instruction set. Document 4 suggests that a general-purpose instruction set may not provide sufficient performance depending on the application.

Of course, if the processor core itself is programmable, the instruction set can be changed freely.
Generally, when the same semiconductor process is used, the operation speed of an arithmetic unit formed on a programmable logic is said to be about three times as slow as the operation speed of a hard-wired arithmetic unit created with a dedicated mask pattern (Reference 2). ), Performance degradation is unavoidable. Further, in the conventional technique disclosed in Document 5, there is a problem that the operation speed is slow because the operation speed of the memory such as the ROM storing the microprogram is slow.

As described above, there has conventionally been a trade-off relationship between the operation speed of the processor and the flexibility of the processor (whether or not the instruction set can be freely changed).

An object of the present invention is to provide a user application with an instruction set with a short TAT as in the case of having a speed performance comparable to a full-customized processor core and being composed of a programmable device such as FPGA. Providing a microprocessor that can be modified accordingly, or a SoC with such a processor core.

Another object of the present invention is to have a microprocessor capable of switching to an optimized instruction set for each application and performing processing with the optimized instruction set, or a processor core having such a microprocessor. SoC
Is to provide.

[0014]

In order to achieve the above object, a preferred embodiment of the present invention has a data path section and a control section on the same chip, and the control section is configured by a programmable logic such as FPGA. The data path unit is a microprocessor configured by hard-wired logic rather than programmable logic.

Further, in the data processing device having such a microprocessor mounted, the programmable logic of the microprocessor is rewritten so that the processing is performed by the instruction set according to the application program.

[0016]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A variable instruction set microprocessor of the present invention will be described in detail below with reference to some embodiments shown in the drawings. In the following, those having the same reference number represent the same or similar items. <First Embodiment> FIG. 1 is a block diagram of a variable instruction set microprocessor of the present invention. The instruction set variable microprocessor C10 includes programmable logic PL1 and hardwired logic.

FIG. 20 shows a configuration example of the programmable logic PL1. The programmable logic PL1 includes a plurality of logic blocks LB1, LB2 ,. ． ． , Vertical wiring layers VL1, VL2 ,. ． ． , Lateral wiring layers HL1, H
L2 ,. ． ． , And a switch matrix C for setting the connection between the vertical / horizontal wiring layer and the logic block.
S1, CS2 ,. ． ． , MS1, MS2 ,. ． ． Composed of. The switch matrix is composed of a plurality of programmable switches. A configuration example of the programmable switch is shown in FIG. nMOS transistor T
The connection state of the wiring layer is set by controlling the conduction / non-conduction of 100 with the connection information holding memory M100.
The connection information holding memory M100 is a circuit configuration information holding unit C.
It belongs to M1 (FIG. 1) and is composed of a nonvolatile memory represented by SRAM, flash memory, or the like. The stored contents can be externally rewritten via the rewriting interface CI1, and the connection relation between the wirings can be arbitrarily changed by rewriting the stored contents. It should be noted that the signal voltage level on the wiring layer is the nMOS transistor T10.
In order to prevent the voltage drop by the threshold voltage due to 0, the switch is switched to nMO as shown in FIG.
It is effective to have a complementary structure of ST100 / pMOST110. Further, as shown in FIG. 22, a buffer (inverters IV200 + IV201, IV202 + I
V203, IV204 + IV205) may be inserted. This switch is effective when signal delay due to wiring becomes a problem due to the long wiring length of the vertical wiring and the horizontal wiring. In the switch having this configuration, the signal level is restored by the buffer, so that the wiring delay can be minimized.

On the other hand, the logical blocks LB1 and LB
2 ,. ． ． FIG. 23 shows a configuration example of the above. Logical block LB
Is a basic logic element LUT (Look Up Table) LU30
0, LU301, LU302, selectors S300 and S30 for selecting an arbitrary input from a plurality of input terminals
1 ,. ． ． , D-type flip-flop D300, and memories M300 to 303 that store circuit configuration information. The basic logic element LUT is a logic element that can realize an arbitrary logic function by rewriting the contents of the built-in memory. FIG. 24 shows a configuration example of the basic logic element LUT. The conduction / non-conduction of the transistors T400 to T441 are determined according to the logical values input to the inputs in1 to in4, and the values of the logical value holding memories M400 to M415 configured by SRAM or flash memory are output. The logical value holding memories M400 to M415 belong to the circuit configuration holding unit CM1 and have a rewrite interface CI1.
The stored contents can be rewritten from the outside via the via. In the basic logic element LUT, a logic circuit having an arbitrary logic function can be realized by rewriting the contents of the logic value holding memory. For example, four inputs in1
The logical value of the output of the logic circuit to be realized when in4 is the logical value “0000” is stored in the logical value holding memory M400. Similarly, the logic value of the output of the logic circuit to be realized when the input is "1000" is stored in the logic value holding memory M401. Similarly, by storing the logical value of the output corresponding to each input pattern in the logical value holding memories M402 to M415, a logical circuit having a desired logical function can be realized. By appropriately setting the contents of the logic value holding memory of the basic logic element LUT, it is possible to realize all the logical functions having four inputs or less, regardless of the kind of the logical function.

In this way, an arbitrary combinational logic circuit can be realized by the basic logic element LUT, and an arbitrary sequential circuit can be realized by having the flip-flop D300 in the logic block LB. Furthermore, a larger-scale logic function can be realized by appropriately setting the above-mentioned programmable switch and connecting a plurality of such logic blocks LB. In this way, by rewriting the contents of the connection information holding memory and the logic value holding memory in the circuit configuration holding unit CM1, the programmable logic PL1 can be rewritten to a logic circuit having a desired logic function.

In the hardwired logic, an external bus interface IB1 which is a circuit element forming a data path section, a program counter PC1, and an instruction register IR.
1, register file RF1, switch matrix S
1, S2, ALU (Arithmetic Logi)
c Unit) A1 and an arithmetic unit A2. ALUA1
Is addition, subtraction, logical operation (AND, OR, XOR
Etc.), various operations such as bit shift are mounted, and these operations are selectively executed by the control line CL11. The arithmetic unit A2 is equipped with an arithmetic operation of a type not implemented in the ALU, for example, arithmetic operation such as multiplication or floating point, and these arithmetic operations are selectively executed by the control line CL12. The register file RF1 is composed of a plurality of registers for storing data to be calculated or data of calculation results. Write to the register specified by the register selection terminal via the in terminal and out1 / ou
Reading is possible via the t2 terminal. The write destination register and the read destination register are
It is specified via the control line CL10. The switch matrices S1 and S2 are composed of a plurality of selectors controlled by control terminals, and the connection between their inputs and outputs can be set. Specifically, the switch matrix S1 includes the data lines DL10 to 13 from the register file RF1 or the input logic PC2 configured on the program logic described later.
One of the data lines DL14 to 17 from 0 is selected according to the control line CL13 and input to the ALUA1 and / or the arithmetic unit A2. Similarly, the switch matrix S
2 is a data line DL20, ALUA1 from the arithmetic unit A2
The data line DL22 from the data line DL22 and the data lines DL21 and DL23 from the output logic PC30 configured on the program logic described later are selected according to the control line CL14, and are written in the register file RF1 via the data line DL50. The program counter PC1 holds memory address information of an instruction to be executed next. This memory address information is stored in the control line CL1 every time an instruction is executed.
It is counted up via 5, and updated to the memory address of the next instruction to be executed. External interface IB
1 is a memory M designated by the program counter PC1
The instruction at the address on EM1 is read into the processor. In addition, the contents of the register file RF1 are stored in the memory
The operation of writing to M1 and delivering to the peripheral circuits PF1, PF2, etc. is performed. The instruction register IR1 holds the instruction read by the external interface IB1.

Each circuit of these hard-wired logics can be realized by a known circuit configuration. Further, these hard-wired logics are mere examples, and it is naturally allowable that the hardwired logic does not include the illustrated circuit elements or that it includes circuit elements other than the illustrated circuit elements.

The programmable logic PL1 is provided with a control circuit for controlling the circuit elements forming these data path sections. Specifically, the instruction decoder PC10,
Program counter control circuit PC11, register file control circuit PC12, ALU / arithmetic unit control circuit PC1
3. Includes a switch matrix control circuit PC14. However, each of these circuits is an example, and depending on the instruction set to be realized, it is naturally permissible not to include the illustrated circuit element or to include a circuit element other than the illustrated circuit element.

For example, in addition to these control circuits, the programmable logic PL1 is provided with an input logic circuit PC20 and / or an output between the register file and the ALU / arithmetic unit in order to perform simple arithmetic processing on the data of the register file RF1. The logic circuit PC30 may be provided. Further, an input / output logic control circuit PC15 for controlling these logic circuits PC20 / PC30 according to an instruction set is also included.

As will be described later, the variable instruction set microprocessor of the present invention can cope with various instruction sets by rewriting the circuit configurations of these various control circuits. The circuit configuration can be rewritten by the logic function of each LUT on the programmable logic and the contents of the circuit configuration holding unit CM1 that holds the connection information of the programmable switch that connects between the LUTs (in the case of the configuration example described in FIGS. Is realized by rewriting the connection information holding memory, the selection information holding memory, and the logical value holding memory). The contents of CM1 are the rewriting terminal CW0 and the circuit configuration rewriting interface CI.
It is rewritten from outside the chip via 1. The circuit configuration rewriting interface CI1 may be, for example, F
General JTAG interface for PGA (Reference 3)
Etc. can be used.

Further, the peripheral circuit PF1 of the microprocessor can be formed in an unused area on the programmable logic. The number of chips in the entire system can be reduced by integrating the peripheral circuits on one chip.

As described above, in the variable instruction set microprocessor C10 of the present invention, since the circuit configurations of the control circuit and the arithmetic processing circuit configured on the programmable logic can be rewritten, the instruction format of the corresponding instruction set is changed. It is possible to add a new instruction. On the other hand, since the ALUA1, the arithmetic unit A2, etc. are hard-wired logic, high-speed arithmetic processing is possible, and both high speed and flexibility of the processor can be achieved.

A method of implementing the defined instruction set in the variable instruction set microprocessor C10 of the present invention and the operation of each circuit element in that case will be described below. Here, the instruction set refers to a set of instructions executable by the microprocessor. (A) Processor that realizes a predetermined instruction set FIG. 2 is an example (IS1 to IS2) of an instruction set including an addition instruction ADD and a multiplication instruction MUL.

Each instruction is composed of a field indicating an instruction type called an opcode and a field indicating an identifier of a register to be operated (herein referred to as a register number). For example, the ADD instruction IE1 of adding the contents of the Rs register and the Rt register and writing the result to the Rd register is defined in a format such as IS1. Similarly, the MUL instruction IE2 of multiplying the contents of the Rs register and the Rt register and writing the result to the Rd register is defined in the format indicated by IS2. The upper 6 bits are assigned to the operation code. In the example of FIG. 2, the ADD instruction is “000001” and the MUL instruction is “000010”. Further, a 5-bit field is assigned to each of the register numbers of Rs, Rt, and Rd, which are calculation targets.

The control circuit analyzes these and controls what type of operation is performed for which number register in the register file. In the example of the instruction set in FIG. 2, the instruction length is 32 bits, of which 6 bits are assigned to the opcode, and 5 bits are assigned to the Rs, Rt, and Rd registers. Therefore, 2 6 =
It is possible to support 64 instructions, 2 to the fifth power = 32 registers. By increasing the bit width allocated to each area, the number of corresponding instructions and registers can be increased.

The instruction description method is not limited to the format shown in FIG. For example, it is possible to assign the operation code to the lower 6 bits or the like. There is also an instruction that directly specifies an address and performs an operation on the address on the memory. In such a case, it is necessary to write not only the register number but the address itself directly in the instruction. Even in such a case, the instruction set variable microprocessor of the present invention can be realized by a method similar to the method described below.

FIG. 3 shows an example in which the processor that executes the instruction set shown in FIG. 2 is realized by using the instruction set variable microprocessor C10. Note that FIG. 3 shows the minimum circuit elements required to execute the instruction set of FIG. An instruction decoder P on the programmable logic PL1
C10a, program counter control circuit PC11a, register file control circuit PC12a, ALU / arithmetic unit control circuit PC13a, switch matrix control circuit PC1
4a is configured to realize the ADD instruction and the MUL instruction of FIG.

Like an ordinary microprocessor, the processing is started by reading an instruction from the memory MEM1 via the external bus interface IB1. The instruction thus read is stored in the instruction register IR1 and analyzed by the instruction decoder PC10a configured on the programmable logic PL1.

Of the instructions transferred to the instruction register IR1, the instruction decoder PC10a separates the upper 6 bits corresponding to the operation code from the bits corresponding to the address of Rs / Rt / Rd, and the upper 6 bits are ALU / arithmetically operated. Control circuit PC13a, switch matrix control circuit PC14
Address data to a to register file control circuit PC
Output to 12a.

The register file control circuit PC12a is
The address data of Rs / Rt / Rd passed from the instruction decoder is analyzed, and the corresponding registers are selected from the register file RF1 via the control line CL10.

In the ALU / arithmetic unit control circuit PC13a, the 6-bit signal corresponding to the operation code is "000001".
Then, activate the control line CL11 of ALUA1,
Start the ALU in add mode. On the other hand, if the signal from the instruction decoder is "000010", the control line CL12 of the multiplier A2 is activated.

Switch matrix control circuit PC14a
Switch matrix S1 via the control line CL13
But register file RF1 and switch matrix S1
It is set to select the data lines (DL10, DL11) and (DL12, DL13) that directly connect and. The control line CL14 to the switch matrix S2 is AL if the signal from the instruction decoder is "000001".
Select the data line DL22 from U and select "000010"
If so, the data line DL20 from the multiplier is set to be selected.

Program counter control circuit PC11a
Indicates that the operation code from the instruction decoder is "00000
In both cases of "1" and "000010", the control line C
The program counter PC1 is incremented via L15 and set to the memory address of the next instruction to be executed.

With the above operation, the variable instruction set microprocessor of the present invention can realize the instruction set shown in FIG. In addition, each control circuit creates circuit data (referred to as a netlist here) so as to realize the above-described processing, and the netlist is programmed by the programmable logic P.
By writing to L1, a processor that executes the target instruction set can be realized. As a method of synthesizing a circuit on a programmable logic, a logic synthesizing tool used in ordinary LSI design can be used, and a known method can be used. In the variable instruction set microprocessor of the present invention, those methods may be applied as they are.

Another type of instruction that exists in the actual instruction set is an instruction of the type that specifies the address of the next instruction to be executed (for example, a jump instruction). The jump instruction describes the address of the next instruction to be executed in a specific field in the instruction format. To support such a jump instruction, the program counter control circuit PC11a may be configured to reset the address contents of the program counter PC1 to the jump destination address via the control line CL15.

By thus configuring the instruction decoder and other control circuits with programmable logic such as FPGA, the circuit configuration of the control circuit can be changed even after the chip is manufactured. Can be changed flexibly.

For example, the instruction set shown in FIG. 2 is ADD.
It is assumed that there is an instruction set that sets the ADD instruction to "100000" while the instruction is "000001". In general, if the type of microprocessor is different, the operation code is different even if the instruction has the same content as the arithmetic processing, and the program created for one processor cannot run on another processor. However, according to the processor of the present invention, the control circuit configured on the programmable logic may be modified as follows. First, if the 6-bit signal corresponding to the operation code of the ALU / arithmetic unit control circuit PC13a is "100000", A
The control line CL11 of LUA1 is activated and the ALU is modified to start in the addition mode. If the 6-bit signal corresponding to the operation code is "100000", the switch matrix control circuit PC14a is modified so that the control line CL14 to the switch matrix S2 selects the data line DL22 from the ALU.

In addition to the opcode, the instruction format itself may be different. For example, register Rd
And the data of the register Rs may be calculated and written back to the register Rd. In this case, it is corrected as follows. First, the instruction decoder PC10a separates the bit corresponding to the address of Rs / Rd in the instruction transferred to the instruction register IR1 and corrects it so as to output the address data to the register file control circuit PC12a. Further, the register file control circuit PC12a is
The address data of Rs / Rd passed from the instruction decoder is analyzed, and the corresponding registers are set to the control line CL.
Modify so as to select from the register file RF1 via 10.

In other words, it is not always necessary that the instruction set be fixed before the chip is designed. Therefore, it is possible to independently design the instruction set and design and manufacture the chip in parallel. further,
Even if there is a problem in the instruction set, it is not necessary to start over from the design and manufacturing of the chip as in a normal microprocessor chip, and the circuit configuration of the control circuit may be changed according to the corrected instruction set. (B) Pipeline Control Processor In general microprocessors, a pipeline operation in which processing is divided into blocks and executed in different clock cycles is widely adopted for speeding up. There are various methods for dividing the pipeline. In the example of FIG. 4, the instruction fetch IF and the instruction decode I are used.
It is divided into five stages of D, operation execution EX, memory access MEM, and register write WB. By dividing the processing into a plurality of stages, the contents to be processed per clock cycle are simplified, and the clock frequency can be increased to increase the processing speed.

FIG. 5 shows an example in which the instruction set variable microprocessor of the present invention is speeded up by such a pipeline operation, and shows circuit elements operating under each stage of IF / ID / EX / MEM / WB. ing. The processing contents of each circuit element are the same as those shown in FIG.

In the IF stage, the program counter P
The instruction is read from the memory address specified by C1 via the external bus interface IB1. The read instruction is held in the pipeline register PR10. The pipeline registers PR10 to PR13 are composed of storage elements such as latches and flip-flops, which are hard-wired logic, hold the data passed from the previous stage, and start operation from the next clock cycle. To pass data to the stage. For this pipeline register, it is possible to use the same configuration as that used in a normal microprocessor. The read instruction is the pipeline register PR1.
0 to the instruction decoder PC10 in the next ID stage
Input to a.

In the ID stage, by the instruction decoder and various control circuits constructed on the programmable logic,
A control signal for controlling a register, a computing unit, etc. is generated. In the ID stage, only the Rt / Rs selection signal generated by the register file control circuit PC12a is passed to the register file RF1. Rd selection signal, ALU / arithmetic unit control signal, and switch matrix control signal, which are other control signals, are E
Since it is required in the X stage and WB stage, it is necessary to retain information until the required clock cycle. Therefore, these control signals are output to the delay circuits LD10 to LD including storage elements such as latches and flip-flops.
14 is input and held. The same applies to the program counter control signal.

In the EX stage, the ALU / arithmetic unit executes the arithmetic. The control of the ALU / arithmetic unit is performed by the delay circuit LD1.
0 and the control signal held in LD11. The result of this operation is held in the pipeline register PR12. Also, the contents of the program counter PC1
It is updated according to the program control signal.

When writing the calculation result to the memory, M
It is written in the memory at the EM stage via the external bus interface IB1. Further, when writing to the register, in the WB stage, the target Rd register is selected based on the held control signal, and the calculation result is written. As described above, the pipeline operation is realized in the variable instruction set microprocessor of the present invention.

Here, in programmable logic represented by FPGA, when circuits having the same function are made by using the same semiconductor process, only circuits which are about three times slower than full-custom chips such as ASIC can be realized. What is said is as described above. The content of analysis of the pipeline control of FIG. 4 is shown in FIG. In the pipeline control of FIG. 4, processing by hard-wired logic (hard macro) is performed in each stage of IF / EX / MEM / WB, whereas processing by programmable logic is performed in the ID stage. . Therefore, there is a possibility that the delay time of the ID stage becomes larger than that of the other stages, and the clock frequency of this microprocessor is limited. This is because in the pipeline operation, the clock frequency needs to be adjusted to the stage having the longest delay time among the stages.

Therefore, the ID stage in which the program logic mainly operates is divided into the ID1 stage and the ID2 stage. This makes it possible to increase the clock frequency and eliminate dead time in other stages.

FIG. 7 shows the operation of the instruction set variable microprocessor corresponding to the subdivided pipeline control shown in FIG. In the example of FIG. 7, the ID stage shown in FIG. 5 is replaced by the ID1 stage in which the instruction decoder PC10a operates, a program counter control circuit PC11a, a register file control circuit PC12a, an ALU / arithmetic unit control circuit PC13a, and a switch matrix control circuit PC14a. Is divided into the ID2 stage in which is operated. 2 ID stages
By dividing, the delay time of the ID1 / ID2 stage can be reduced to about half. For this reason,
When the ID stage controls the clock frequency of the chip, the clock frequency can be increased to about double. For example, it may be further divided into three stages or more, and the division points may be changed appropriately according to the delay time of each circuit element.

When the number of stages of pipeline control is increased, high-speed operation becomes possible, but on the other hand, there is a possibility that the circuit scale becomes large due to the need for pipeline registers. However, in the present invention, the arithmetic unit and the like are realized by a hard macro, and the risk of rate limiting is limited to the stage for generating these control signals. Therefore, it is possible to minimize the stage division newly required due to the adoption of programmable logic. Even though there is a slight increase in area, full custom ASI
It is possible to obtain the same speed performance as C. (C) A processor that realizes a type of arithmetic instruction that is not implemented in an ALU or arithmetic unit In this example, a simple instruction set is taken up, and a processor of a type that is not implemented in an ALU or arithmetic unit configured by hardwired logic is used. It is shown that the instruction for the operation can also be realized by the variable instruction set microprocessor of the present invention. The implementation of the instruction set shown in FIG. 8 will be described below. The instruction set of FIG. 8 is an instruction set in which new instructions (IS3, IE3) are added to the instruction set of FIG. The added instruction IS3 is, as shown in IE3,
Upper 16 bits and lower 16 bits of the register specified by Rs
This is an instruction to add bits as 16-bit data and write the result to the register designated by Rd.

Such an instruction is normally realized by using the ALU / arithmetic unit a plurality of times when the built-in ALU or arithmetic unit does not support such an arithmetic mode. For example, (1) copy the contents of Rs to another register Rt (2) shift Rt 16 bits to the right (3) set the upper 16 bits of Rs to 0 (4) add Rs and Rt, and add the result to Rd The basic instruction is executed in four cycles such as writing to.
However, as described in the section of the prior art, in the modulation / demodulation processing of a digital signal required for a communication application, it is necessary to execute a high-speed instruction of the type that shifts the bit position of data to perform an operation ( For example, see Reference 4. Therefore, it is desirable that such bit manipulation can be executed at high speed with as few cycles as possible.

In the instruction set variable microprocessor shown in FIG. 1, between the register file and the ALU / arithmetic unit,
Input logic circuit PC2 composed of programmable logic
0 and an output logic circuit PC30. For this reason,
By causing the logic circuits to perform the above-described processing such as bit manipulation, it is possible to execute operations that are not supported by the ALU at high speed.

FIG. 9 shows an example in which the function described above is used to realize the instruction set of FIG. As shown in FIG. 9, the ALU /
It is realized by programming the arithmetic unit control circuit PC13d, the switch matrix control circuit PC14d, the input logic circuit PC20d, and the input / output logic control circuit PC15d. The operation of each circuit will be described below in the range related to the SADD instruction. Figure 3 for the ADD and MUL instructions
The circuit is configured to operate in the same manner as.

The ALU / arithmetic unit control circuit PC13d is S
The signal from the instruction decoder is "00" in response to the ADD instruction.
When 0100 ″, the circuit is configured to activate the control line CL11 and activate the ALU in the addition mode.

Switch matrix control circuit PC14d
Is a control line CL when the signal from the instruction decoder is "000100" corresponding to the operation code of the SADD instruction.
13 through the switch matrix S1 to the data line D
Select L14 and DL15. Further, the switch matrix S2 is connected to the data line DL through the control line CL14.
The circuit is configured to select 22.

The input / output logic control circuit PC15d controls the control line CL20 only when the signal from the instruction decoder PC10a is "000100" which is the operation code of the SADD instruction.
Through, the input logic circuit PC20d is activated.

In the input logic circuit PC20d, the control line CL
The 32-bit data line DL10 activated by 20 and input from in1 is distributed to the upper 16 bits and the lower 16 bits and output to the data lines DL14 / DL15 connected to out1 / out2. The switch matrix S1 selects these two data lines and inputs them to the ALU operating in the addition mode.

As a result, the result of adding the upper 16 bits and the lower 16 bits of the register designated by Rs is output to the output of the ALU, and the target SADD shown in FIG. 8 is output.
The operation is realized.

FIG. 10 shows how the data path is calculated when the SADD instruction is executed. The register of the register number designated by Rs is read out, and the input logic circuit P
The C20d separates the upper 16 bits and the lower 16 bits, and the two are added by the addition mode ALU. The input logic circuit PC20d shown in FIG.
An example of the equivalent circuit of is shown. As the input logic circuit PC20d, tristate buffers G100 to G132, G2
A circuit that realizes this desired operation can be provided by programming the logic circuit configured by 00 to G232.

FIG. 12 shows an example in which the circuit of FIG. 9 is pipelined. Here, the IF is the same as in FIGS.
This is an example in which / ID1 / ID2 / EX / MEM / WB is divided into stages and pipelined, but other division into stages is also possible.

In the EX stage, the input logic circuit P
Since the C20d executes the calculation, the delay time may increase. However, the processing contents performed by the input logic circuit PC20d are simple contents, and as shown in FIG. 11, can be constituted by a circuit having a shallow number of stages. Therefore, the increase in the delay time due to the input logic circuit PC20d is small, and the EX
The input logic circuit PC20d is operated in the stage. On the other hand, when implementing complicated processing in the input logic circuit PC20d, it is desirable to implement the control circuit as a multi-cycle instruction that executes the EX stage in a plurality of clock cycles only for the instruction using the input logic circuit PC20d. . For an instruction that does not use the input logic circuit PC20d, the switch matrix S1 allows the AL to be directly input without passing through the input logic circuit PC20d.
U / Connected to arithmetic units A1 and A2. Therefore, for the instruction that does not use the input logic circuit PC20d, the EX stage can be executed in one clock, and the decrease in operation speed can be limited to only the relevant instruction.

Even when the multi-cycle instruction is implemented as described above, it is often possible to execute it with a smaller number of clocks than to execute it by dividing it into a plurality of basic instructions. For example, in the example of FIG. 9, even if the SADD instruction is realized by a multi-cycle instruction that requires two clocks in the EX stage, the number of clocks required for processing is smaller than that required when the basic instruction is executed four times. As a result, high speed processing is possible.

As described above, in the variable instruction set microprocessor of the present invention, a part of arithmetic processing is performed by the input logic circuit formed by the programmable logic inserted between the register file and the ALU / arithmetic unit. , It is possible to execute at high speed an instruction corresponding to an operation not provided by the built-in ALU / operation unit.

Next, taking the instruction set of FIG. 13 as an example,
It will be described that more complicated instructions can be implemented by using the programmable logic connected to the output of the ALU / arithmetic unit. The instruction set of FIG. 13 is an instruction set in which new instructions (IS4, IE4) are added to the instruction set of FIG. As shown in IE4, the added instruction IS4 multiplies the upper 16 bits and the lower 16 bits of the register designated by Rs as 16-bit data, and further, the multiplication result and the register designated by Rt. Is added and the result is written to the register specified by Rd. As in the case of the third embodiment, when such an arithmetic mode is not supported by the ALU or arithmetic unit in the chip, it is usually necessary to use the ALU / arithmetic unit multiple times for implementation. . For example, (1) copy the contents of Rs to another register R2 (2) shift R2 16 bits to the right (3) set the upper 16 bits of Rs to 0 (4) read the data of Rs and R2, and multiply And the result is written to another R3 (5) The data of R3 and Rt are read, added by the ALU, and the result is written to Rd. It is necessary to execute the basic instruction five times. However, in the modulation / demodulation processing of the digital signal required in the communication system, such a product-sum operation (M
It is necessary to execute the AC calculation) at high speed. For this reason, many microprocessors and digital signal processors are equipped with dedicated arithmetic units.

On the other hand, in the variable instruction set microprocessor of the present invention shown in FIG. 1, an input logic circuit PC20 and an output logic circuit PC30, which are formed by programmable logic and are inserted between the register file and the arithmetic unit.
Thus, by sharing the simple arithmetic processing, it is possible to realize the MAC arithmetic instruction even in the ALU that does not support the MAC arithmetic.

FIG. 14 shows an example in which the instruction set variable microprocessor of the present invention realizes the instruction set of FIG. As shown in FIG. 14, the ALU / arithmetic unit control circuit PC13e, the switch matrix control circuit PC14e, and the input logic circuit P are arranged on the programmable logic.
It is realized by programming the C20e, the input / output logic control circuit PC15e, and the output logic circuit PC30e. The operation of each circuit will be described below in the range related to the SMAC instruction. Figure 3 for the ADD and MUL instructions
The circuit is configured to operate in the same manner as the above, and the circuit is configured to operate in the same manner as in FIG. 9 for the SADD instruction.

The ALU / arithmetic unit control circuit PC13e is S
The signal from the instruction decoder corresponds to the MAC instruction and is "00".
When 0101 ", the control line CL11 is activated,
Start ALUA1 in addition mode. In addition, the control line CL
12 is also activated to activate the multiplier A2.

Switch matrix control circuit PC14e
When the signal from the instruction decoder is "000101" corresponding to the operation code of the SMAC instruction, the control line C
The data lines DL16 and DL17 and the data lines DL14 and DL are provided to the switch matrix S1 through L14.
Select 11. Further, the switch matrix S2 is set to select DL22 through the control line CL13.

In the input / output logic control circuit, the signal from the instruction decoder of the PC 15e is "000100" and "000101" which are the operation codes of the SADD instruction and the SMAC instruction.
At the time of, the input logic circuit PC20e and the output logic circuit PC30e are activated through the control lines CL20 and CL30.

The input logic circuit PC20e has a control line CL2.
It is activated by 0. Unlike when the SADD instruction is executed,
At the time of SMAC instruction, first, in the first cycle, in
The 32-bit data of the Rs register input from 1 is distributed to upper 16 bits and lower 16 bits, output to the data lines DL16 and DL17, and input to the multiplier A2 via the switch matrix S1. The result of the multiplication is
It is held in the latch formed in the output logic circuit PC30e. The held operation result is the next clock cycle,
It is input to in3 of the input logic circuit via the data line DL100. In this clock cycle, the signal in3 is output as it is to out1 / out2,
The input logic circuit PC20e operates and is input to the addition mode ALUA1 via the switch matrix S1.
The content of the Rt register is output to the data line DL11, and the multiplication result output to the data line DL14 is ALUA1.
The result of multiplying the upper 16 bits and the lower 16 bits of the register specified by Rs is R
The result of adding the t registers "is output, and the target MAC
The arithmetic instruction is executed.

In this way, the SMAC instruction shown in FIG. 13 can be realized by the instruction variable microprocessor having the configuration of FIG. FIG. 15 shows how the data path is calculated when the SMAC instruction is executed. The register having the register number designated by Rs is read out and separated into upper 16 bits and lower 16 bits by the input logic circuit PC20e. Next, the two are multiplied by a multiplier. Further, after the multiplication result is latched by the output logic circuit PC30e, it is input to the ALU started in the addition mode via the input logic circuit PC20e, the addition result is obtained, and the MAC operation result is obtained.

A plurality of configuration examples of the input logic circuit PC20e and the output logic circuit PC30e are conceivable. As an example thereof, the tri-state buffer G5 shown in FIG.
An equivalent circuit composed of 00 to G732 and selectors S100 to S132 is shown. Further, also in the case of FIG. 14, it is possible to realize a high processing speed by pipeline processing. <Second Embodiment> As a second embodiment, a configuration in which the instruction set variable microprocessor of the present invention is used to execute a plurality of application programs stored in various servers on a computer network will be described. As shown in FIG. 17, the computer terminal PD1
Is connected to servers AS100-AS200 storing various application programs AP100-AP200 via a computer network N100.
The computer terminal PD1 receives an instruction from the user via the input / output interface IF1 such as the keyboard KY1 and downloads the designated application program to the storage device MS1 including a semiconductor memory or a magnetic disk device via the computer network N100. Then, the program is executed by the instruction set variable microprocessor C10 of the present invention. The execution result is provided to the user via the display device DS1 or the like as necessary. Note that the computer network N100 is schematically shown, and the connection method such as a wired line or a wireless line is not limited. Further, the terminal PD1 exemplifies a form in which independent chips are arranged on the board and they are connected by the bus BU1. For example, the instruction set variable processor C is used.
It is also possible to integrate 10 and the rewrite control circuit WC0 on one chip.

A computer terminal that does not have such an application program in its own storage device and can be downloaded from various servers and executed as necessary can have a small storage capacity of the storage device. Therefore, a portable terminal, a so-called PDA (Personal Di)
It is suitable for the digital assistant). Moreover, the user does not have to be forced to install application programs one by one. Furthermore, there are various merits such that the latest application can always be used by appropriately setting the download destination server. Therefore, such a terminal is expected to realize a next-generation distributed computing environment (for example, Nikkei Electronics 200
July 30, 1st issue, pp. 108-pp. 117 (reference 6)).

At present, however, there are various kinds of microprocessor instruction sets, and they are not compatible with each other. Therefore, in order to realize the distributed computing environment as shown in FIG. 17, the application programs stored in the servers AS100 to AS200 must be written in an instruction set specific to the processor C10 of the terminal PD1. It was Since the processor of the server and the processor of the terminal are usually different, the application program stored on the server needs to be prepared separately for the processor of the terminal PD1 and not a program that can be executed by the server processor. Therefore, it is necessary to prepare a dedicated application program written with a dedicated instruction set for each type of processor of the terminal PD1, and the management effort becomes enormous.

In order to deal with this problem, in the conventional technique disclosed in Document 6, an application program is described with an intermediate instruction set that does not depend on a processor such as Java, and the terminal of the download destination side There is disclosed a method of executing while converting to an instruction set of a processor configuring the terminal.

However, according to this method, it takes time to convert the intermediate instruction set into its own unique instruction set, so that it is necessary for the dedicated application program written in the processor-specific instruction set of the terminal PD1. ,
There is a risk that the operation speed will be inferior.

In the present embodiment, by using the variable instruction set microprocessor of the present invention in combination with the instruction set mapping program P10 described later, it is possible to download and execute application programs described in various instruction sets. And eliminate the need to store a dedicated program on the server.
Further, the circuit configuration itself is changed according to the instruction set of the application to be executed, and then the application is executed, so that the operation speed is significantly improved.
The operation of the instruction set mapping program P10 of the present invention will be described below with reference to FIGS. The instruction set mapping program can be implemented in two ways, that is, on the terminal and on the server. (1) When the instruction set mapping is performed on the terminal The instruction set mapping program P10 is the storage device MS.
1 (see FIG. 17). The instruction set mapping program P10 rewrites the circuit configuration of the program logic PL1 of the microprocessor C10 so that the instruction set corresponding to the downloaded application program AP10 can be executed.

Instruction set mapping program P10
Is the instruction set description file D1 as shown in FIG.
0, the circuit configuration of the program logic PL1 is determined from the resource information file R10. In the instruction set description file D10, the operation of the instruction to be realized as shown in FIG. 2, the instruction format, the operation code, etc. are described. On the other hand, in the resource information file R10, control information such as the types of arithmetic units mounted by the instruction set variable microprocessor C10 of the present invention and how to control them, and the scale of the mounted programmable logic are provided. Information such as is described.

Both the instruction set description file D10 and the resource information file R10 can be always held in the storage device MS1 on the terminal PD1. However, when the storage capacity of the storage device MS1 is limited, these files are stored in the server AS on the network.
It is desirable to have a configuration in which it is prepared in 200 and downloaded to the terminal PD1 as needed. The instruction set mapping program P10 analyzes the input information of the instruction set description file D10 and the resource information file D20, and determines the arithmetic unit to be used for each instruction to be realized (P11). Next, for each instruction, the control procedure of the arithmetic unit necessary for realizing the instruction is analyzed, and the specification of the control logic circuit configured on the programmable logic is determined (P12). From the control logic specifications determined in this way, logic synthesis is performed by a general method, a logic circuit that realizes the specifications is synthesized, and a programmable logic netlist N10 is created (P13). Finally, the created netlist N10 is written in the programmable logic PL1 via the circuit configuration rewriting interface.

As described above, by using the instruction set mapping program P10 and the instruction set variable microprocessor C10 of the present invention, it is possible to obtain a microprocessor which automatically realizes the instruction set when the instruction set is given. Become. As a result, various application programs existing on various servers on the network can be seamlessly executed on the terminal PD1.

Here, in each routine of the instruction set mapping program P10, the logic synthesis of the programmable logic of P13 does not necessarily have to be executed on the terminal PD1. Programmable logic P
It is also possible to execute up to the logic synthesis (P13) of L1 on the high-speed server AS100 or the like on the network and download only the netlist of the resulting programmable logic. With such a configuration, the storage capacity required for the storage device MS1 can be small. In addition, even if the scale of the control logic becomes large depending on the instruction set and relatively long time is required for logic synthesis, the time required for rewriting can be minimized by executing logic synthesis on a high-speed server. It is possible to limit it. Also, on the server AS200, for each instruction set required in advance, the logic synthesis of P13 of FIG. 18 is executed, a programmable logic netlist is prepared, and when switching the instruction set of the application, A configuration is also possible in which only the programmable logic netlist is downloaded to the terminal side.

A method of writing the netlist N10 into the programmable logic PL1 will be described with reference to FIGS.
Will be explained. FIG. 25 shows an example of the memory space map MA0 of the variable instruction set processor of the present invention. Figure 25
Of the circuit information holding unit CM1 written via the rewrite control circuit WC0.
It is assigned to F and the other addresses A0 to AC0 are used as a normal memory. Of course, the circuit information holding unit CM1 may be allocated to a predetermined address of the memory space map MA0, and the allocation method is not limited.

The rewriting is executed in the steps of WP100-130 in FIG. (A) WP100 Processor C10 is a network interface N
11. Access the server via the computer network N100, obtain the programmable logic netlist N10 corresponding to the desired instruction set, and expand it in the memory space specified by the addresses AS to AE. In addition,
In the embodiment in which the terminal PD1 logically synthesizes, the address AS ~
The generated netlist is stored in the memory space designated by AE. It is assumed that the memory space designated by the addresses AS to AE is on the memory MS1. The memory space map in this state is shown in FIG. (B) WP110 The processor C10 needs to transfer the netlist stored in the memory MS1 to the circuit configuration holding unit CM1.
Therefore, the processor C10 uses the DMA (DirectMemory Ac)
cess) The controller DMA0 is notified of the transfer source address (start address AS, end address AE) to the DMA controller DMA0, and the bus BU1 usage right is given to the DMA controller DMA0. (C) The WP120 DMA controller DMA0 temporarily stores the netlist stored in the memory MS1 in its own buffer memory, and through the rewrite control circuit WC0 and the circuit configuration rewrite interface C11, a circuit defined as addresses AC1 to AF. The information is transferred to the information holding unit CM1. The memory space map in this state is shown in FIG. Finally, the netlist is written in the circuit information holding unit CM1. The memory space map in this state is shown in FIG. (D) The WP130 DMA controller DMA0 passes the bus use right to the processor C10. Further, the processor C10 restarts the operation from an instruction (for example, a boot instruction) on a predetermined memory address (normal memory area).

As described above, the variable instruction set processor C10 of the present invention can rewrite the programmable logic PL1.

FIG. 19 shows how the application program written in a different instruction set is executed while rewriting the instruction set on the terminal PD1. First, the application program A (AP1) is downloaded. When the description file D1 of the instruction set A for executing the application program A does not exist in the storage device MS1, the description file of the instruction set A is also downloaded at the same time. Next, the instruction set mapping program generates the programmable logic netlist N1 for realizing the instruction set A. Finally, according to the programmable logic netlist N1, the instruction set variable microprocessor C10 of the present invention is
The circuit configuration is rewritten, and the target application program AP1 is executed. When executing the application program AP2 written with another instruction set B, the programmable logic netlist N2 corresponding to the instruction set B is generated, the instruction set variable microprocessor C10 is rewritten, and the application is executed by the same procedure. The program AP2 is executed. When the netlist N1 is generated on the server side, the application program AP1 and the corresponding netlist N
1 should be downloaded.

[0088]

According to the variable instruction set microprocessor of the present invention, it is possible to provide a microprocessor which can deal with various instruction sets having different instruction formats and in which the speed performance is less deteriorated.

[Brief description of drawings]

FIG. 1 is a diagram showing a configuration of a variable instruction set processor of the present invention.

FIG. 2 is a diagram illustrating a format of each instruction of an instruction set described in the first embodiment.

FIG. 3 is an example in which the instruction set of FIG. 2 is realized by a variable instruction set microprocessor.

FIG. 4 is a diagram showing an outline of processing for each stage when a variable instruction set microprocessor is pipelined.

5 is a diagram showing a processing flow when the variable instruction set microprocessor is realized by the pipeline operation shown in FIG. 4;

FIG. 6 is a diagram showing an outline of processing for each stage when a variable instruction set microprocessor is pipelined.

7 is a diagram showing a processing flow when the variable instruction set microprocessor is realized by the pipeline operation shown in FIG. 6;

FIG. 8 is a diagram illustrating a format of each instruction of the instruction set described in the first embodiment (C).

9 is an example in which the instruction set of FIG. 8 is realized by a variable instruction set microprocessor.

10 is a diagram illustrating a signal flow of a data path unit at the time of executing a SADD instruction in the instruction set variable microprocessor of the present invention shown in FIG. 9;

11 is an equivalent circuit of a configuration example of an input logic circuit PC20d of the instruction set variable microprocessor of FIG.

FIG. 12 is a diagram showing an outline of processing for each stage when a variable instruction set microprocessor is pipelined.

FIG. 13 is a diagram illustrating a format of each instruction of the instruction set described in the first embodiment (C).

FIG. 14 is an example in which the instruction set of FIG. 13 is implemented by a variable instruction set microprocessor.

FIG. 15 is a diagram for explaining the signal flow of the data path unit when the SMAC instruction is executed in the instruction set variable microprocessor of the present invention shown in FIG.

16 is an equivalent circuit of a configuration example of an input logic circuit PC20e and an output logic circuit PC30e of the instruction set variable microprocessor of the present invention shown in FIG.

FIG. 17 shows a variable instruction set microprocessor.
It is a figure showing the example of composition of the computer terminal which runs various application programs stored in various servers on a network.

FIG. 18 is a diagram showing a processing flow of an instruction set mapping program P10.

FIG. 19 is a diagram showing an outline of a processing flow when a plurality of programs written in different instruction sets are executed by a variable instruction set microprocessor.

FIG. 20 is a diagram showing a configuration example of a programmable logic PL1.

FIG. 21A shows a programmable logic P.
It is a figure which shows the structural example of the programmable switch of L1, and FIG.21 (b) is a figure which shows the modification.

FIG. 22 is a diagram showing a further modification of the programmable switch of the programmable logic PL1.

FIG. 23 is a diagram showing a configuration example of a logic block LB of the programmable logic PL1.

FIG. 24 is a diagram showing a configuration example of a basic logic element LUT of a logic block LB.

FIG. 25 is a diagram showing a memory space map of the instruction set variable processor of the present invention.

FIG. 26 is a diagram for explaining a procedure for rewriting the programmable logic PL1 of the variable instruction set processor of the present invention.

FIG. 27 is a diagram for explaining a procedure for rewriting the programmable logic PL1 of the variable instruction set processor of the present invention.

[Explanation of symbols]

C10 ... Processor, PL1 ... Programmable logic, IB1 ... External bus interface, IR1 ... Instruction register, PC1 ... Program counter, RF1 ... Register file, S1, S2 ... Switch matrix, A
1 ... ALU, A2 ... arithmetic unit.

Claims (10)

[Claims] 1. A register file composed of a plurality of registers, an arithmetic circuit composed of hard-wired logic, for executing a predetermined arithmetic operation based on data output from the register file, and a programmable logic. A microprocessor for forming an instruction decoder for decoding an instruction and a first control circuit for selecting a designated register from the register file according to the decoded instruction by the programmable logic. 2. The programmable logic according to claim 1, wherein the programmable logic includes a plurality of basic logic elements for realizing a predetermined logical function and a plurality of basic logic elements including a switching element and switching the switching element. A microprocessor having programmable wirings interconnected with each other and a storage element for storing switching information of the switching element. 3. The first switch circuit according to claim 1, comprising a hard-wired logic and connected to an input of the arithmetic circuit, wherein predetermined processing is performed on the data in accordance with the decoded instruction. The first logic circuit to be performed and the second control circuit for controlling the first switch circuit are formed by the programmable logic, and the output of the register file and the output of the first logic circuit are input to the first switch circuit. And a circuit in which the output of the register file and the output of the first logic circuit are selectively input to the arithmetic circuit by the second control circuit. 4. The operation circuit according to claim 1, further comprising a second switch circuit configured by hard-wired logic and connected to an output of the arithmetic circuit, the arithmetic result of the arithmetic circuit according to the decoded instruction. A second logic circuit that performs a predetermined process and a third control circuit that controls the second switch circuit are formed by the programmable logic, and the input of the second switch circuit is the output of the arithmetic circuit and the second circuit. A microprocessor which is connected to the output of the logic circuit, and in which the output of the arithmetic circuit and the output of the second logic circuit are selectively stored in the register file by the third control circuit. 5. A data path unit having a register file, an arithmetic circuit configured by hard-wired logic and performing a predetermined arithmetic operation based on data stored in the register file, and an arithmetic process in the data path unit is controlled. And a programmable logic in which a control circuit is formed. The control circuit divides the process from fetching an instruction to writing the processing result in the data path unit into the register file into a plurality of stages to perform pipeline processing. Processor. 6. The microprocessor according to claim 5, wherein the control circuit executes a stage for decoding the instruction and a stage for generating a control signal for the data path unit based on the decoded instruction in different stages. 7. The programmable logic according to claim 5 or 6, wherein the programmable logic includes a plurality of basic logic elements for realizing a predetermined logic function, and the plurality of basic logics including a switch element and switching the switch element. A microprocessor having a programmable wiring for connecting elements to each other and a storage element for storing switching information of the switching element. 8. A data path unit having a register file, a hard wired logic, and an arithmetic circuit for executing a predetermined arithmetic operation based on data stored in the register file, a programmable logic, and the programmable logic. A microprocessor having a rewrite interface for rewriting contents, and having a circuit configuration of an instruction decoder for decoding an instruction for executing an operation in the data path unit, written in the programmable logic from the rewrite interface. 9. The programmable logic device according to claim 8, wherein the programmable logic connects between a plurality of basic logic elements for realizing a predetermined logic function and the plurality of basic logic elements by including a switch element and switching the switch element. A microprocessor having programmable wirings connected to each other and a storage element for storing switching information of the switching element. 10. A data processing device having a processor for performing processing according to an instruction set according to an application.