JP2003163577A - Cutoff frequency variable filter - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a cutoff frequency variable filter that automatically controls cutoff frequency of a filter with high precision through a comparatively simple constitution. <P>SOLUTION: A reference signal generation circuit 14 comprises an oscillating circuit 12 that generates a vibration signal repeating level transition with predetermined recurrence frequency between a ground level and power supply level; and a clip circuit 13 that, by clipping the vibration signal into a first level higher by a predetermined levels than the ground level and a second level lower by a predetermined level than the power supply level, generates a reference signal repeating level transition between the first level and the second level. A reference signal generated in the reference signal generation circuit 14 is input into an LPF 11 and its outputs are monitored to control the cutoff frequency of the LPF 11. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a cutoff frequency variable filter having a function of automatically controlling a cutoff frequency.

[0002]

2. Description of the Related Art In recent years, it has become difficult to form an on-chip filter by incorporating a passive element such as an LCR in a chip and, in some cases, combining it with an active element such as a current source or a transconductor. However, the problem here is that LC is a passive element.
This is the variation in the absolute value of R. Pn on the substrate for the resistor R
Although diffusion or gate polysilicon is used, the resistance value depends on the diffusion concentration, and it is generally said that the maximum value is about ± 30%. The capacitance C is often formed between layers such as metal-metal (including MIM technology) or polysilicon-polysilicon, and the capacitance value is the thickness of the interlayer insulating oxide film (in terms of the process, the degree of shaving). It also depends on, and ± 30% also varies here. In addition, inductor L
Is rarely formed in a chip "for filter use", but if it is mounted, a spiral coil made of a metal layer or a bonding wire may be considered. However, these are very difficult to model, and it is difficult to match the target inductance value.

For the above reasons, the filter mounted on the chip has a weak point that its cutoff frequency (time constant) tends to vary. On the other hand, in recent years, there has been a great demand for wireless communication ICs, and a filter incorporated therein surely cuts undesired communication (a signal in a nearby frequency band) and surely passes a desired communication signal. There is a strong demand for performance.

Therefore, various measures are taken in order to suppress the variation of the cutoff frequency. As one of the means, the value of LCR (including the active element) is made variable, and the cutoff frequency is corrected inside the chip. The method of doing is possible. For example, JP-A-62-206915, "Time constant correction circuit for integrated circuit" and JP-A-4-105.
A technique for correcting the cutoff frequency by giving a reference frequency to the filter is proposed in Japanese Patent Laid-Open No. 410-410.

The technique proposed in [1] is to connect a high-precision RC to the outside of the chip, use the result of comparison of the time constant with the internal RC as a correction value, and apply it to all time constant circuits in the chip. is there. However, this method eventually requires an external element, and the variation in the ratio accuracy within the chip cannot be completely canceled, or the original path of the filter and the reference signal source built in the chip are provided at the filter input part. This is a technique of correcting the cutoff frequency by switching between and by a switch and monitoring the filter output level at the reference signal input. However, this proposal is premised on "if the oscillation frequency and level of the reference signal source are stable," and there is no description of its specificity or feasibility.

[0006]

SUMMARY OF THE INVENTION In view of the above circumstances, it is an object of the present invention to provide a cutoff frequency variable filter which can control the cutoff frequency of the filter with high accuracy by a relatively simple circuit.

[0007]

A cutoff frequency variable filter according to the present invention which achieves the above object, comprises a cutoff frequency variable filter circuit and a reference signal generation circuit for generating a predetermined reference signal and inputting it to the filter circuit. , A monitor circuit for monitoring the level of the output signal of the filter circuit when a reference signal is input to the filter circuit, and a monitor circuit for controlling the level of the output signal of the filter circuit to a predetermined level. A cutoff frequency control circuit for controlling the cutoff frequency of the filter circuit, the reference signal generation circuit,
An oscillation circuit that generates an oscillation signal in which the level repeatedly transits between a ground level and a power supply voltage level at a predetermined repetition frequency, and the oscillation signal is a first level and a power supply voltage higher than the ground level by a predetermined level. A clip circuit that generates a reference signal that repeatedly transits between the first level and the second level by clipping with a second level that is lower than the level by a predetermined level. It is characterized by being.

In most recent system LSIs, a PLL circuit based on a crystal oscillator has an accurate clock. In addition, the clock has multiple systems in one chip, and various frequencies can be created relatively easily by processing these clocks by frequency division and multiplication. Therefore, it is possible to generate a clock having a cutoff frequency of the filter.

The present invention pays attention to this point, and
The clock that the system has is used as a reference signal for adjusting the cutoff frequency of the filter. However, since the clock that the system has has a full swing between the ground level and the power supply level, it is too large as an input to the filter. Therefore, by providing the above-mentioned clip circuit and suppressing the swing width of the clock to a predetermined width,
A reference signal having a level and an accurate frequency and amplitude suitable for the input of the filter is easily generated. By using this reference signal, the cutoff frequency of the filter can be adjusted accurately.

Here, in the cutoff frequency variable filter of the present invention, the clip circuit includes an inverter composed of a PMOS transistor on the power supply side and an NMOS transistor on the ground side, which are connected in series, and a power supply more than the inverter. One or more diode-connected PMOS transistors arranged in series with the inverter, and a diode-connected NM arranged in series with the inverter on the ground side of the inverter
A structure including an OS transistor is preferable.

When the clip circuit having the above structure is provided, a reference signal having a predetermined swing width can be easily and accurately produced.

In the cutoff frequency variable filter of the present invention, the monitor circuit may generate a comparison voltage by using a diode-connected transistor and compare the peak voltage of the output signal of the filter circuit with the comparison voltage. Therefore, it is preferable to monitor whether or not the level of the output signal has reached a predetermined level.

If the monitor circuit having the above configuration is provided, the level of the output signal can be accurately monitored with a simple circuit, and therefore the cutoff frequency of the filter circuit can be accurately adjusted.

[0014]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below.

FIG. 1 is a circuit block diagram showing an embodiment of a cutoff frequency variable filter of the present invention.

Variable cutoff frequency filter 1 shown in FIG.
Reference numeral 0 denotes one mounted in a semiconductor integrated circuit (LSI), and this cutoff frequency variable filter 10 is provided with a cutoff frequency variable low-pass filter (LPF) 11 as an example of the filter circuit according to the present invention. ing. Further, on the input side of the LPF 11, the PLL circuit 121 and the frequency division /
An oscillator circuit 12 including a multiplication circuit 122 and a reference signal generation circuit 14 including a clipping circuit 13 are provided,
On the output side of the PF 11, a peak detector 15 as an example of a monitor circuit according to the present invention and a cutoff frequency control circuit 16 are provided.
And have been deployed.

In the PLL circuit 121 of the oscillation circuit 12 constituting the reference signal generation circuit 14, the vibration of the crystal oscillator outside the LSI is picked up and a signal of a predetermined frequency is generated. The output of the PLL circuit 121 is the frequency division / multiplication circuit 12
It is input to 2 and divided or multiplied to generate an oscillation signal of a predetermined frequency near the cutoff frequency of the LPF 11.

The oscillation signal generated by the frequency dividing / multiplying circuit 122 is input to the clipping circuit 13 and clipped to a signal of a predetermined amplitude level to generate a reference signal.

FIG. 2 is a circuit diagram of the clip circuit 13 shown as one block in FIG.

This clip circuit is arranged in series with the inverter 133 which is connected to each other in series and is composed of a PMOS transistor 131 on the power source side and an NMOS transistor 132 on the ground side, and an inverter 133 on the power source side of the inverter 133. And the diode-connected PMOS transistor 134 and the inverter 133
A diode-connected NMOS transistor 1 connected in series with the inverter 133 on the ground side of the
And 35.

Here, in the clip circuit 13 of FIG. 2, one PMOS transistor 134 is arranged on the power supply side of the inverter 133 and one NMOS transistor 135 is arranged on the ground side of the inverter 133. Depending on the level, a plurality of PMOS transistors and a plurality of NMOS transistors may be arranged.

An oscillation clock signal of a predetermined frequency generated by the oscillation circuit 12 of FIG. 1 is input to the clip circuit 13 of FIG. 2, and a diode-connected PMOS transistor 134 has a threshold voltage (V) of which the power source side is a PMOS.
_t-pmos ) and the diode-connected NMOS transistor 15 has an NMOS on the ground side.
Of the threshold voltage (V _t-nmos ) is generated, and a reference signal whose amplitude level is suppressed to a desired level as a whole is generated.

A reference signal generated from the clipping circuit 13 is input to the LPF 11 of FIG. 1 after the power is supplied to the LSI and before the LPF 11 is actually used, and the reference signal passes through the LPF 11 to The peak level of the output signal output from the LPF 11 is the peak detector 15
Detected in.

FIG. 3 is a circuit diagram of the peak detector shown in one block in FIG.

In the peak detector 15, the diode-connected PMOS transistor 151 generates a comparison voltage, and the comparator 152 compares the comparison voltage with the output (filter output) of the LPF 11 in FIG. Here, the PMOS transistor 151 is the P transistor shown in FIG.
The characteristics are slightly different from those of the MOS transistor 134 (for example, the dimensions are slightly different), and a reference voltage suitable for detecting the peak of the output of the LPF 11 is generated. Alternatively, instead of making the characteristics of the PMOS transistors different, the comparator may be provided with a slight offset.

By changing the cutoff frequency of the LPF 11 with the cutoff frequency control circuit 16 of FIG. 1 while observing the output of the peak detector 15, the LPF 11 can be controlled to an LPF having a predetermined frequency characteristic.

If a simple A / D converter is used instead of the comparator shown in FIG. 3, more accurate peak detection can be performed. These may be selected by the trade-off between the mounting area and the detection accuracy.

FIG. 4 shows the LP shown as one block in FIG.
It is a figure which shows the circuit structure of F.

As shown in FIG. 4A, the LPF 11 includes a variable resistor 111 arranged in series in a signal transmission line,
Capacitor 1 placed between the signal transmission line and ground
It is an RC filter composed of 12 and.

A variable resistor 111 which constitutes the LPF 11.
Has the configuration shown in FIG. 4B, and the resistance value is switched depending on which of the plurality of analog switches 111a is turned on. In this case, the cutoff frequency control circuit 16 of FIG. 1 is composed of a logic circuit that switches a plurality of analog switches 111a.

FIG. 5 is a diagram showing another example of the cutoff frequency variable filter circuit according to the present invention, which replaces the LPF 11 shown in FIGS. 1 and 4.

As shown in FIG. 5A, the filter circuit 21 includes an inductor 2 arranged in series in a signal transmission line.
11, and a pair of variable capacitance capacitors 212 and 213 arranged between both sides of the inductor 211 and the ground.
It is a π-type LC filter composed of and.

FIG. 5B shows an example of a voltage-controlled capacitance variable capacitor called a varactor, which is realized by a pn junction capacitance and the depletion layer expands and contracts by controlling the voltage value between pn. However, the capacitance value can be changed. In this case, the cutoff frequency control circuit 16 of FIG.
Is composed of a constant voltage generating circuit whose voltage value is variable.

In addition, when an active element is used in the filter circuit, the filter constant can be controlled by changing the current value of the circuit or the like, and a control circuit suitable for it can be assembled. Although no specific circuit is given, there are various methods of realizing a circuit for holding the constant when the correction is completed, such as a logic latch or an analog sample hold circuit.

When the cutoff frequency of the cutoff frequency variable filter of FIG. 1 is controlled to a predetermined value, the control value at that time (information on ON / OFF of the analog switch in the case of FIG. 4, or pn in the case of FIG. 5) is set. The control voltage value in between) is stored in the circuit, and the filter circuit is fixedly controlled based on the control value until the next adjustment.

Although not shown, both the clipping circuit and the circuit for outputting the input signal of the filter are preferably controlled so that their outputs are in a high impedance state. For example, the clocked inverter is configured so that the output stage of each circuit is a tri-state output. Also, the output of the clipping circuit and the filter input are switched by a switch so that either one is input to the LPF. By doing so, it becomes possible to appropriately adjust the cutoff frequency or input the filter without the mutual outputs interfering with each other.

[0037]

As described above, according to the present invention,
The cutoff frequency of the filter can be adjusted with high accuracy by a simple circuit.

[Brief description of drawings]

FIG. 1 is a circuit block diagram showing an embodiment of a cutoff frequency variable filter of the present invention.

FIG. 2 is a circuit diagram of a clip circuit shown by one block in FIG.

FIG. 3 is a circuit diagram of a peak detector in one block in FIG.

FIG. 4 is a diagram showing a circuit configuration of an LPF shown by one block in FIG.

FIG. 5 is a diagram showing another example of the filter circuit according to the present invention.

[Explanation of symbols]

10 Cut-off frequency variable filter 11 LPF 12 Oscillation circuit 13 clip circuit 14 Reference signal generation circuit 15 Peak detector 16 Cut-off frequency control circuit 21 Filter circuit 111 variable resistance 111a analog switch 112 capacitor 121 PLL circuit 122 frequency division / multiplication circuit 131 PMOS transistor 132 NMOS transistor 133 inverter 134 PMOS transistor 135 NMOS transistor 151 PMOS transistor 152 Comparator 211 inductor 212,213 Variable capacitance capacitors

Claims (3)

[Claims] 1. A cutoff frequency variable filter circuit, a reference signal generation circuit for generating a predetermined reference signal and inputting the reference signal to the filter circuit, and the filter when the reference signal is input to the filter circuit. A monitor circuit for monitoring the level of the output signal of the circuit; and a cutoff frequency control circuit for controlling the cutoff frequency of the filter circuit so that the level of the output signal of the filter circuit is controlled to a predetermined level. An oscillation circuit that generates an oscillation signal whose level repeatedly transits between a ground level and a power supply voltage level at a predetermined repetition frequency; and the oscillation signal is higher than the ground level by a predetermined level. By clipping at a level of 1 and a second level lower than the power supply voltage level by a predetermined level. And a clipping circuit that generates a reference signal that repeatedly makes a transition between the second level and the cutoff frequency variable filter. 2. The clip circuit is arranged in series with the inverter, which is connected to each other in series and is composed of a PMOS transistor on the power supply side and an NMOS transistor on the ground side, and an inverter on the power supply side of the inverter. 2. The variable cutoff frequency according to claim 1, further comprising one or more diode-connected PMOS transistors and a diode-connected NMOS transistor arranged in series with the inverter on the ground side of the inverter. filter. 3. The monitor circuit generates a comparison voltage by using a diode-connected transistor, and compares the peak voltage of the output signal of the filter circuit with the comparison voltage so that the level of the output signal is predetermined. 3. The cutoff frequency variable filter according to claim 1, wherein the cutoff frequency variable filter is for monitoring whether or not the level has reached.