JP2003162870A - Phase comparator circuit and pll circuit that uses it - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a phase comparator circuit and a PLL circuit incorporating it, which can correct LSB errors in code conversion of the wave data read from a magnetic recording medium, avoid increase in circuit scale and in delay, while realizing high speed phase difference calculations. <P>SOLUTION: A correction circuit 140 detects the state depending on the ternary conversion of the wave data when two consecutive wave data are code converted, and holds the data '1' in the first holding circuit to input to the carry input CI of an adder circuit 150 based on the detected result. It outputs the data '1' retained in the first holding circuit to input to the carry input CI of the adder circuit 150, when the ternary data of the inputted wave data takes a value other than '-1'. Thus, -1LSB errors made in adding are corrected, and the phase errors are corrected by integrating them in the following low-pass filter. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a phase comparison circuit, for example, PRML (Partial Response Maximum Likelihood).
The present invention relates to a PLL circuit that generates a clock signal for sampling a read signal and a phase comparison circuit that configures the PLL circuit in a read circuit such as a magnetic recording medium using the (2) method.

[0002]

2. Description of the Related Art In a read circuit for reading recorded information from a recording medium such as a magnetic storage medium, a signal waveform is sampled based on a clock signal having a predetermined frequency in order to digitize the read signal waveform. This clock signal is generated using a PLL circuit. Especially P
In the RML system, a PLL circuit extracts a clock timing based on a partial response (PR) signal which is a read signal read from a recording medium and reproduces the clock signal. Then, the read signal is sampled using this clock signal, converted into waveform data which is a digital signal, and the original data is reproduced by maximum likelihood decoding (ML) processing.

FIG. 1 is a block diagram showing an example of the configuration of a read circuit for reading recorded data from a magnetic recording medium such as a magnetic disk. As shown, the readout circuit
Gain control amplifier (GCA) 10, equalization filter 20, analog / digital converter (ADC) 30,
It is composed of a maximum likelihood decoder 40 and a decoder 50. The signal S _i read from the magnetic recording medium is the GCA10.
And the gain is controlled in the GCA 10 so that the amplitude of the output signal is always constant. Therefore, the amplified signal S1 whose amplitude is almost constant is output from the GCA 10.
0 is output.

The output signal S10 of the GCA 10 is input to the equalization filter 20, which is subjected to equalization (PR4 equalization) processing and output to the ADC 30.
The ADC 30 converts the input signal into, for example, 6-bit data. The 6-bit conversion data S30 output from the ADC 30 is supplied to the maximum likelihood decoder 40. The maximum likelihood decoder 40 performs a decoding process according to the input data, and outputs decoded data S40. The decoder 50 further performs a decoding process in accordance with the decoded data input from the maximum likelihood decoder 40, and outputs the restored data S _out obtained by restoring the original record data.

The above-mentioned read circuit reproduces the information data recorded on the recording medium according to the read signal S _i from the magnetic recording medium. In the signal reproduction process, the ADC 30 converts the output signal S20 of the equalization filter 20 into a digital signal. In this analog / digital conversion process, the output signal S2 of the equalization filter 20 is generated at the timing of the sampling clock signal CLK having a predetermined sampling frequency.
It is necessary to sample 0. The sampling clock signal CLK is usually generated by a PLL circuit.

FIG. 2 is a block diagram showing a configuration of a read circuit including the PLL circuit 60. PL as shown
The L circuit 60 includes a phase comparator 61, a current output DAC (digital / analog converter) 62, and a low pass filter (L
It is composed of a PF) 63 and a voltage controlled oscillator (VCO) 64. The configuration and operation of each partial circuit of the PLL circuit 60 will be described below.

The phase comparator 61 receives the 6-bit conversion data S30 output from the ADC 30, and compares the phases. As a result of the phase comparison, a 6-bit phase difference signal S61 is output. The current output DAC 62 converts the phase difference signal S61 into a current signal. Therefore, the current output D
A current signal S62 corresponding to the value of the phase difference signal S61 is output from the AC 62.

The current signal S62 output from the current output DAC 62 is input to the low pass filter 63. The low-pass filter 63 integrates the current signal S62,
The high frequency component is suppressed, and the control signal S63 including the low frequency component is output to the VCO 64 in the subsequent stage. VCO64
Outputs the oscillation signal while controlling the oscillation frequency according to the input control signal S63. This oscillation signal is supplied to the ADC 30 as the clock signal CLK, and the ADC 3
The sampling timing of 0 is controlled.

With the PLL circuit 60 thus constructed, the clock signal CL is reduced in the direction in which the phase error of the 6-bit conversion data S30 output from the ADC 30 becomes smaller.
The phase of K (that is, the oscillation frequency of the VCO) is controlled.
By this control, the sampling timing in the ADC 30 is accurately controlled according to the read signal, so that the occurrence of a read error can be suppressed.

Next, the phase comparison processing in the phase comparator 61 constituting the PLL circuit 60 will be described. The phase comparison is performed by the conversion data S30 output from the ADC 30,
That is, it is performed based on the digitized equalized waveform. Specifically, the digitized equalized waveform is divided into three values of (-1, 0, +1) by a preset threshold value,
Phase comparison is performed digital value of the equalized waveform at a certain time and {X _n} with the one sampling period before the digital values {X _n-1}. Generally, in the PR4 equalization method, the phase difference θ _{e of the} digitized equalized waveform is calculated by the following equation.

[0011]

[Number 1] _{θ e = Y n · X n} -1 -Y n-1 · X n ... (1)

In equation (1), Y_n And Y_n-1 Is it
Digital value X of each equalized readout waveform_n And X_n-1 
Is ternized into {-1, 0, +1}, and {Y
_n , Y _n-1 } Ε {-1,0, + 1}.

The ternarization process of the output signal S30 of the ADC 30 is performed based on a preset threshold value. For example, the range of values of the 6-bit conversion data S30 is −32 to +31 when expressed in decimal. Here, each threshold value for ternary + 10, when -10, when the waveform data X _n + 10 or more, Y _n are + 1, -9
When it is within the range of +9, Y _n is 0, and when it is -10 or less, Y _n is -1.

In the phase comparator 61, the conversion shown in FIG.
According to the table {X_n , X_n-1 } Is code-converted and
Phase difference is calculated by adding the results of code conversion by
To be done. For example, as an example, X_n = + 20, X_n-1 =
If it is +18, {Y_n , Y_n-1 } = {+ 1, + 1}
Therefore, according to the conversion table shown in FIG._n And X
_n-1 The signs are "-" and "+", respectively. others
Therefore, according to equation (1), the phase difference θ_e Is calculated as
And θ_e = [+ (+ 18)-(+ 20)] =-2
It

Here, the operation of multiplying X _n or X _n-1 by the code "-", that is, code conversion is realized by calculating the two's complement. Specifically, the 2's complement is calculated by inverting the value of each bit of data from 0 to 1 and from 1 to 0, and further adding "1" to LSB. If the work of adding "1" to the LSB is individually performed, the circuit scale and the calculation time are increased. Therefore, in the actual calculation circuit, the work of adding "1" to the LSB is individually performed when the code conversion is performed. X _n after the code conversion without the addition circuit of
In the adder used in the addition of X and X _n-1
Add "1" to. That is, the code-converted X _n and X _n-1 are added by a full adder (full adder) with carry input CI, and when the code conversion is performed on X _n or X _n-1 , the carry is carried. The input CI is set to "1", and "1" to be added to the LSB is added. For this reason, the input of the full adder becomes the value of each bit of the waveform data X _n and X _{n-1 on} which only the inversion processing of "0" and "1" is performed as necessary.

FIG. 4 shows an example of the configuration of a phase difference calculation circuit configured by using a bit inverting circuit 100 for code conversion and an adder circuit 110 including a full adder (FA). This phase difference calculation circuit is included in the phase comparator 61.
As shown in FIG. 4, the bit inversion circuit 100 inputs 6-bit waveform data X _n and X _n-1 respectively, and ternarizes these waveform data according to a predetermined threshold value, and then, FIG. The sign of the waveform data X _n and X _n-1 is obtained according to the conversion table shown in FIG. When the sign of X _n or X _n-1 is "-", bit inversion is performed on the waveform data, and as a result, 6-bit data is added to the addition circuit 1 respectively.
Output to 10.

In the adder circuit 110, the bits of the code-converted X _n and X _n-1 are added, respectively, and X
_{When the} sign inversion is performed on _n or X _n−1 , data “1” is input to the carry input CI and the LS of the operation result is input.
Add “1” to B. By performing the addition processing by the bit inverting and adding circuit 110 as described above, when the code conversion is performed on the waveform data X _n and X _n−1 , the respective L
The process of adding data “1” to SB can be realized by the adder circuit 110, the circuit configuration is simplified, and the reduction of the calculation speed is avoided.

[0018]

By the way, the above-mentioned phase difference calculation processing is effective when the code conversion of either _one of the waveform data X _n or X _n-1 is performed.
_When both _n and X _n-1 need to be code-converted, for example, in the conversion table of FIG. 3, {Y _n , Y _n-1
} = {-1, + 1}, the LSB of the adder circuit 110
It is necessary to add "2" to the adder circuit 110 shown in FIG.
Then, since only "1" can be added to the LSB of the calculation result by the carry input CI, there is a disadvantage that an error of -1 occurs in the LSB.

FIG. 5 shows that the addition result is -1L in the above-mentioned situation.
An example in which an SB error occurs is shown. As shown
Where, for example, X_n-1 = + 24, X_n = -18
It X _n-1 And X_n As a result of ternarizing Y_n-1 =
+1, Y_n = -1. According to the conversion table shown in FIG.
So in this case X_n-1 And X_n Are both "-"
Become. As shown in FIG._n-1 And X_n Is 0,
It is inverted by one and the result is added by the adder circuit 110.
Then, "1" is added to LSB. Adder circuit 11
The result of addition of 0 is "-7". However, originally (-2
4-(-18)) is expected to yield a result of -6,
Although "1" should be added to LSB twice, this circuit
Since the addition is executed only once, the result of the addition is-
An error of 1LSB will occur.

In order to avoid this, the addition circuit 1 is further added.
It suffices to provide another adder in the subsequent stage of 10 and add "1" to the addition result of the adder circuit 110, but the data "1" is added to the LSB.
It is not a good idea to provide a new adder just to add the above because it not only increases the circuit scale, but also causes a further gate delay and causes a reduction in the operation speed.

The present invention has been made in view of the above circumstances, and an object thereof is to correct an LSB error caused by code conversion of waveform data, avoid an increase in circuit scale and an increase in delay time, Phase comparison circuit capable of realizing high-speed phase difference calculation and digital P using the same
It is to provide an LL circuit.

[0022]

In order to achieve the above object, the phase comparison circuit of the present invention determines the phase difference according to two consecutive waveform data among the waveform data obtained by digitizing the read signal from the recording medium. A phase comparison circuit for obtaining, a ternarization circuit for ternarizing the first waveform data and the second waveform data of the two waveform data according to respective predetermined threshold values, and the ternarization circuit. A bit inversion circuit that inverts each bit of the first or second waveform data in accordance with the result of ternarization by the above, and bit-wise addition processing is performed on the output data of the bit inversion circuit to invert the bit. According to the processing result, the addition circuit that adds the data “1” to the LSB and outputs the addition result as the phase difference data, and the ternaryization result of the first waveform data and the second waveform data are predetermined. When it is combined, holding the data "1" a predetermined time of the addition circuit LSB
And a correction circuit for outputting to the carry input.

Further, the PLL circuit of the present invention obtains a phase difference according to the input digitized waveform data and outputs a phase difference signal, and a current signal corresponding to the phase difference signal. And a current output circuit that outputs the current signal, an integration circuit that integrates the current signal and outputs a voltage signal according to the integration result, and a voltage-controlled oscillator whose frequency is variable according to the voltage signal. A PLL circuit having an analog / digital conversion circuit for performing the above-mentioned digitization processing and outputting the above-mentioned waveform data in accordance with a clock signal output by the phase comparison circuit, wherein the phase comparison circuit is the above-mentioned digitized waveform data. A ternarization circuit for ternarizing the first waveform data and the second waveform data of the continuous two waveform data in 3) according to respective predetermined threshold values. A bit inverting circuit that inverts each bit of the first or second waveform data according to the result of the ternarization by the ternarization circuit, and a bit-by-bit addition process for the output data of the bit inverting circuit An addition circuit that adds data “1” to the LSB according to the result of the bit inversion process and outputs the addition result as phase difference data; and three values of the first waveform data and the second waveform data. And a correction circuit for holding the data "1" for a predetermined time and outputting it to the carry input of the LSB of the adder circuit when the result of the conversion is a predetermined combination.

Further, in the present invention, preferably, in the correction circuit, the ternarization result of the first and second waveform data output by the ternarization circuit is the predetermined combination. Of the input waveform data, a logic circuit that detects a signal and outputs a signal indicating data “1” according to the detection result, a first holding circuit that holds the output signal of the logic circuit,
A second holding circuit for holding the holding signal of the first holding circuit and applying it to the carry input of the LSB of the adding circuit when the valued result transits to data other than the data forming the predetermined combination; Have.

[0025]

FIG. 6 is a circuit diagram showing an embodiment of a phase comparison circuit according to the present invention. As illustrated, the phase comparison circuit of the present embodiment outputs the phase difference data PE by code conversion and addition processing according to the waveform data X _n-1 and X _n of the input read signal. This phase comparison circuit forms a part of the PLL circuit 60 shown in FIG. Although not shown, the phase comparator 6 shown in FIG.
In addition to the phase comparison circuit of the present embodiment, 1 also includes a latch circuit that holds the previous waveform data and outputs it to the phase comparison circuit at the next phase difference calculation. That is, two continuous waveform data are supplied to the phase comparison circuit.

As shown in FIG. 6, the phase comparison circuit of this embodiment has two ternary decision circuits 120-1, 120-2,
Code conversion circuit 130, correction circuit 140 and addition circuit 15
It is composed of 0s. The configuration and function of each partial circuit of the phase comparison circuit of this embodiment will be described below.

The three-value determination circuits 120-1 and 120-2 are
3 for each input waveform data X _{n- 1} and X _n
The value is judged, and as a result of the judgment, three-valued data {Y
_{n-1, Y n} =} {- 1,0, it outputs the + 1}. For example, the three-value determination circuits 120-1 and 120-2 divide the input waveform data according to the threshold values -10 and +10, and when the value of the waveform data is -10 or less, "-1" is obtained as the three-value determination result. Is output, and when the value of the waveform data is +10 or more, “+1” is output as the ternary determination result. When the value of the waveform data is within the range of -9 to +9, "0" is output as the result of the ternary determination.

FIG. 7 shows the three-value determination circuits 120-1 and 120.
2 shows a block diagram of -2. As shown in the figure, the three-value determination circuit 120-1 determines the value of the waveform data X _n−1 ,
Depending on the result of the determination, if +1 then P1, if 0 then Z1
If -1, the N1 is held in an active state, for example, a high level, and the other outputs are held in an inactive state, that is, a low level. Similarly, the three-value determination circuit 120-2
Determines the value of the waveform data X _n , and depending on the result of the determination, P0 if +1, Z0 if 0, N if -1.
Hold 0 in the active state and other outputs in the inactive state.

The code conversion circuit 130 is a three-value determination circuit 12.
Based on the determination results of 0-1 and 120-2, the waveform data X _n-1 and X _n are code-converted according to the conversion table of FIG. 3, and the conversion result is output to the adding circuit 150.

The correction circuit 140 uses the waveform data X _n-1 and X _n-1.
of the added value that occurs when both _n are code-converted
Correct 1 LSB error. Hereinafter, the configuration of the correction circuit 140 and the principle of correction will be described. As described above, when both of the waveform data X _n-1 and X _n are code-converted, it is necessary to add "2" to the addition result of the addition circuit 150 in total. However, when the adder circuit 150 uses a full adder, only 1 can be added to the LSB by the carry input CI, and the addition result is -1LS.
B error occurs. In order to correct this error, if an adder circuit is simply provided in the subsequent stage of the full adder and "1" is added, both the circuit scale and the delay time increase. In order to solve this, attention has been paid to the fact that the phase difference signal as the addition result is subjected to integration processing by a low-pass filter provided in the subsequent stage of the PLL circuit. That is, even if a situation where it is originally necessary to add "2" to the addition result, at that point in time, only "1" is added to the addition result, and the remaining " If "1" is added to the addition result, the total amount of integration when viewed on a long time scale becomes almost the same, and the -1LSB error is corrected.

Since the time required for the PLL circuit to reach the locked state is much longer than the time period for detecting the normal phase error, the operation of the PLL circuit is not so much unless the total integrated amount of the phase errors is incorrect. It is considered to have no effect. Further, by performing the correction processing in this way, it is possible to prevent an increase in circuit scale and a decrease in calculation speed without requiring a new addition circuit.

Next, based on the above-mentioned correction principle, the correction process will be described in more detail with reference to the circuit configuration of the correction circuit 140. FIG. 8 is a circuit diagram showing a configuration example of a partial circuit of the correction circuit 140. As shown, the partial circuit 140a of the correction circuit includes an AND gate 141, NO
R gate 142 and D flip-flops 143 and 144
It is composed by. The AND gate 141 outputs the plus signals P1 and 3 output from the three-value determination circuit 120-1.
Minus signal N output from the value determination circuit 120-2
0, the logical product of the three signals of the clock signal CLK is arranged side by side, and the result is applied to the clock input terminal (CLK) of the D flip-flop 143. NOR gate 142
Calculates an inverted logical sum of the minus signal N0 output from the ternary judgment circuit 120-2 and the inverted signal of the clock signal CLK, and outputs the result to the reset terminal (RST) of the D flip-flop 143 and the D flip-flop 144. Are applied to the respective clock input terminals (CLK).

In the D flip-flop 143, the data input terminal (D) is connected to the power supply voltage V _CC , and the output terminal (Q).
Are connected to the data input terminal (D) of the D flip-flop 144. The reset terminal (RST) of the D flip-flop 144 is grounded, and the output terminal (Q) is connected to the carry input CI of the adder circuit 150.

As described above, the waveform data X _n-1 and X _n
3 where the symbols Y _n-1 and Y _n are +1 and -1, respectively.
Waveform data X _n-1 and X _n according to the conversion table shown in
Since both of them are code-converted and added, it is necessary to add "2" in the adding circuit at this time. That is, when the waveform data X _n-1 and X _n are both code-converted, it is necessary to add "2" to the LSB in the adder circuit. In this case, for the time being, the addition circuit 150 temporarily sets the LSB to "1".
Add At this point, the output of the adder circuit 150 is -1L.
The SB error is included. However, such a condition is only when the result of the ternary determination changes from "+1" to "-1", that is, the code Yn _-1 of the waveform data _Xn-1 is "+1". , the sign Y _n of the waveform data X _n "-
This is only for 1 ". Such waveform data is" +
The transition from "1" to "-1" never occurs continuously, and the next possible state transition of the waveform data is "-1" to "-1", "-1" to "0", or It is one of the three "-1" to "+1".

In the transition from "-1" to "-1" among the three state transitions, since the waveform data _Xn-1 is code-converted according to the conversion table shown in FIG. 3, addition is performed. It is necessary to input "1" to the carry input CI of the circuit 150, but for the other two transition states, it is not necessary to perform the code conversion for both the waveform data X _n-1 and X _n , and therefore the adder circuit 150 is required. It is not necessary to input "1" to the carry input CI of. Here, "1" is input to the carry input CI of the adding circuit 150 only once in order to correct the error of -1LSB. By doing so, the integrated value of the phase error output by the low-pass filter of the PLL circuit 60 at the time when this correction is completed does not include an error.

Next, the correction circuit 140
The implementation method will be described. Ternary decision circuit 120-1
The determination result of 120-2 is the input waveform data X._n , X _n-1 
Is a predetermined threshold value, for example, +10 or more, plus
The signals P0 and P1 are held at a high level and a predetermined negative
When the threshold value, for example, -10 or less, the negative signal N
0 and N1 are held at high level. Also, the waveform data
Is within the range of -9 to +9, zero signals Z0 and Z1 are
Held at level

The ternary judgment circuit shown in FIG. 7 outputs a ternary judgment result according to the waveform data X _n-1 and X _n . The ternary decision result Y _n-1 of the waveform data X _n-1 is "+1", the ternary decision result Y _n of waveform data X _n "-
When it is 1 ", both the plus signal P1 and the minus signal N0 become high level. In response to this, in the partial circuit 140a of the correction circuit 140 shown in FIG.
When LK is at high level, the output signal of the AND gate 141 also becomes high level, so the D flip-flop 143
Output becomes high level. That is, the output data of the D flip-flop 143 is held at "1". The output data of the D flip-flop 143 is further input to the D flip-flop 144, held by the D flip-flop 144, and applied to the carry input CI of the adder circuit 150.

Next, with reference to the waveform diagram of the partial circuit 140a of the correction circuit 140 shown in FIG.
The operation of 40a will be described in more detail. As shown in FIG. 9, for example, at a certain time t ₁ , both the positive signal P1 output from the ternary value determining circuit 120-1 and the negative signal N0 output from the ternary value determining circuit 120-2 are held at a high level. Then, according to this, the correction circuit 14
The output S141 of the AND gate 141 of 0 is held at the high level. At the rising edge of the output S141 of the AND gate 141, the output signal S143 of the D flip-flop 143 is held at the high level.

As described above, when the ternary determination result of the waveform data changes from "+1" to "-1", both the waveform data _Xn-1 and _Xn are code-converted. An error of -1LSB occurs in the output data of 150. The state transition of the waveform data that can occur following this state transition is either "-1" to "-1", "-1" to "0", or "-1" to "+1". Among these, since the waveform data X _n-1 is code-converted in the state transition from “−1” to “−1”, the carry input CI of the adder circuit 150 is corrected to correct an error in the next addition cycle. You need to enter 1 ”.

In the partial circuit 140a of the correction circuit shown in FIG. 8, when the waveform data undergoes the state transition from "-1" to "-1", the minus signal N0 output from the three-value determination circuit 120-2 continues. Held at high level. During this period, the output of the NOR gate 142 is held at low level. Then, the ternary determination result of the waveform data X _n is “−
When it becomes a value other than 1 ”(time t ₂ in FIG. 9),
Negative signal N output from the three-value determination circuit 120-2
0 switches to low level. In response to this, the clock signal CLK is output from the output terminal of the NOR gate 142 and applied to the clock input terminal of the D flip-flop 144. Therefore, in the correction circuit 140, the output terminal of the D flip-flop 144 rises to the high level. By setting the carry input CI of the adder circuit 150 to "1" according to the output of the D flip-flop 144, "1" is added to the addition result, and -1LSB is added.
Error is corrected.

As shown in the waveform diagram of FIG. 9, the waveform data is sampled according to the clock signal CLK having a constant cycle. That is, the waveform data is updated every cycle of the clock signal CLK. At a certain time t ₁ , the ternary judgment value of the waveform data X _n-1 becomes +1 and the waveform data X _n-1
When the ternary judgment value of _n becomes -1, the correction circuit 140 holds the output S143 of the D flip-flop 143 at a high level. At this time, the waveform data X _n and X
_Since both _n-1 are code-converted, a -1LSB error occurs in the output result of the adder circuit 150. While “-1” continues as the ternary judgment result of the input waveform data, 3
Minus signal N0 output from the value determination circuit 120-2
Is held high. When the ternary decision result of the input waveform data is other values than "-1" (time t _2), output minus signal N0 from ternary decision circuit 120-1 falls to the low level. In response to this, the output signal S144 of the D flip-flop 144 is held at the high level. In response to this, the carry input CI of the adder circuit 150 is set to "1", so that "1" is added to the addition result, and the waveform data _Xn and _Xn-1 are converted by code conversion. An error of -1 LSB is corrected.

Next, the overall operation of the phase comparison circuit of this embodiment will be described with reference to the circuit diagram of the phase comparison circuit shown in FIG. As shown, waveform data X _n-1 and X
_n is input to the three-value determination circuits 120-1 and 120-2, respectively, and also to the code conversion circuit 130. By the three-value determination circuit 120-1, the waveform data X
_n-1 is determined to be any of the three-valued data {-1, 0, +1}, and either the plus signal P1, the zero signal Z1, or the minus signal N1 is held at the high level according to the result of the determination. It Similarly, the three-value determination circuit 120-2 determines the waveform data X _{n to} be any one of the three-value data {-1, 0, +1}, and depending on the result of the determination, the plus signal P0 and the zero signal Z0. Alternatively, either of the minus signals N0 is held at the high level.

The code conversion circuit 130 is the ternary judgment circuit 12
The code conversion is performed on the waveform data X _n-1 and X _n according to the plus, zero signal and the minus signal output from 0-1 and 120-2. For example, when the plus signal P0 output according to the waveform data _Xn is at low level, the waveform data _Xn-1 is code-converted. As shown in FIG. 6, in the code conversion circuit 130, each bit of the waveform data X _n-1 is logically inverted by the exclusive OR gate. When the minus signal N1 output according to the waveform data X _n-1 is at the low level, the exclusive OR gate in the code conversion circuit 130 logically inverts each bit of the waveform data X _n . Furthermore, when the zero signal Z1 output according to the waveform data _Xn-1 is at high level, the output of the inverter 131 becomes low level. As a result, each bit of the waveform data X _n input to the adder circuit 150 is held at “0”. Further, when the zero signal Z0 is at high level, the output of the inverter 132 is held at low level. As a result, each bit of the waveform data X _n-1 input to the adder circuit 150 is held at “0”.
The operation of the code conversion circuit 130 described above matches the conversion table shown in FIG.

Next, the operation of the correction circuit 140 will be described. The correction circuit 140 includes a partial circuit 140 shown in FIG.
In addition to a, NAND gate 145 and NOR gate 1 for generating carry input CI to adder circuit 150.
47 are provided. The minus signal N0 from the three-value determination circuit 120-2 is input to the NOR gate 147 together with the plus signal P1 from the three-value determination circuit 120-1. The output of the NOR gate 147 is applied to one input of the NAND gate 145, and the inverted output xq of the D flip-flop 144 is applied to the other input.

The correction circuit 140 configured as described above
In, when the ternary judgment result of the waveform data X _n-1 is positive or when the ternary judgment result of the waveform data X _n is negative, the output of the NOR gate 147 becomes low level, and accordingly the NAND The output of the gate 145 becomes high level. That is, at this time, the carry input CI input to the adding circuit 150 becomes "1". This matches the conversion table shown in FIG. That is, as shown in FIG. 3, ternary decision result Y _n-1 of the waveform data X _n-1 is "+1"
At this time, the waveform data X _n is code-converted, and at this time, “1” is added to the LSB of the addition result. Further, according to FIG. 3, when the ternary determination result of the waveform data _Xn is "-1", the waveform data _Xn-1 is code-converted, so that "1" is added to the LSB of the addition result. .

Further, when the three-value determination results of the waveform data X _n-1 and X _n are "+1" and "-1" respectively, both the waveform data X _n-1 and X _n are code-converted. At this time, since an error of −1LSB occurs in the output of the addition circuit 150,
As described above, in the partial circuit 140a of the correction circuit 140, when the output of the D flip-flop 143 is held at the high level and the minus signal N0 output from the ternary determination circuit 120-2 is switched to the low level, The output of the D flip-flop 144 is held at the high level, that is, the inverted output x of the D flip-flop 144.
Since q is held at the low level, the NAND gate 14
5 is held at a high level, the carry input CI becomes "1" in response to this, and the adder circuit 150 causes the LSB to change.
Is added to "1" to correct an error of -1LSB.

As described above, according to the present embodiment, the two waveform data X _n-1 input to the phase comparison circuit.
-1 caused by transcoding both X and X _n
A correction circuit 140 is provided to correct the LSB error, and the correction circuit 140 is provided when a -1 LSB error occurs.
Thus, the data "1" applied to the carry input CI of the adder circuit 150 is internally held. Then, when the ternary data of the input waveform data is other than “−1”, the data “1” held in the correction circuit 140 is output to the carry input CI of the addition circuit 150. The resulting −1LSB error is corrected, and the phase difference data output by the phase comparison circuit is integrated by the low-pass filter in the subsequent stage, resulting in almost no phase error.

[0048]

As described above, according to the phase comparison circuit of the present invention and the PLL circuit using the same, the -1LS generated in the phase difference calculation result due to the combination of the input waveform data.
The B error can be corrected, and the accuracy of phase comparison can be improved. Further, it is not necessary to additionally provide an adder circuit for error correction, that is, it is possible to avoid an increase in circuit scale, thereby reducing current consumption, further reducing delay time, and improving operation speed. There is.

[Brief description of drawings]

FIG. 1 is a block diagram showing a general configuration of a read circuit of a magnetic recording medium.

FIG. 2 is a block diagram showing a general configuration of a read circuit of a magnetic recording medium including a PLL circuit.

FIG. 3 is a conversion table showing code conversion of read waveform data.

FIG. 4 is a block diagram showing a bit inversion circuit and an addition circuit for realizing code conversion.

FIG. 5 is a diagram showing an example in which a −1LSB error occurs in the addition result.

FIG. 6 is a circuit diagram showing an embodiment of a phase comparison circuit according to the present invention.

FIG. 7 is a block diagram of a three-value determination circuit in the phase comparison circuit of this embodiment.

FIG. 8 is a circuit diagram showing a configuration of a partial circuit of a correction circuit in the phase comparison circuit of the present embodiment.

FIG. 9 is a waveform diagram showing the operation of the correction circuit.

[Explanation of symbols]

10 ... Gain control amplifier (GCA), 20 ... Equalization filter, 30 ... Digital / analog converter (AD)
C), 40 ... Maximum likelihood decoder, 50 ... Decoder, 60 ... PL
L circuit, 61 ... Phase comparator, 62 ... Current output DAC, 6
3 ... Low-pass filter (LPF), 64 ... Voltage controlled oscillation circuit (VCO), 120-1, 120-2 ... Tri-value determination circuit, 130 ... Code conversion circuit, 140 ... Correction circuit, 150
… Addition circuit.

Claims (3)

[Claims] 1. A phase comparison circuit for obtaining a phase difference according to two consecutive waveform data of waveform data obtained by digitizing a read signal from a recording medium, wherein the first of the two waveform data is Waveform data and second
Of the waveform data of 3) according to a predetermined threshold value, and each bit of the 1st or 2nd waveform data is inverted according to the result of the 3 value conversion by the 3 value conversion circuit. The bit inversion circuit and the output data of the bit inversion circuit are subjected to addition processing for each bit, and according to the result of the bit inversion processing,
When the data "1" is added to the LSB and the addition result is output as phase difference data, and when the ternaryization result of the first waveform data and the second waveform data is a predetermined combination, the data A phase comparison circuit having a correction circuit which holds "1" for a predetermined time and outputs it to the carry input of the LSB of the addition circuit. 2. The correction circuit detects that the ternarization result of the first and second waveform data output by the ternarization circuit is the predetermined combination, and responds to the detection result. A logic circuit that outputs a signal indicating data "1", a first holding circuit that holds the output signal of the logic circuit, and data other than the data in which the ternarization result of the input waveform data forms the predetermined combination. 2. The phase comparison circuit according to claim 1, further comprising a second holding circuit for holding the holding signal of the first holding circuit and applying it to the carry input of the LSB of the adder circuit when transitioning to data. 3. A phase comparison circuit which obtains a phase difference according to input digitized waveform data and outputs a phase difference signal, and a current output circuit which outputs a current signal corresponding to the phase difference signal. An integrating circuit that integrates the current signal and outputs a voltage signal according to the integration result, and a voltage-controlled oscillator whose frequency is variable according to the voltage signal, and uses a clock signal output by the voltage-controlled oscillator. In response to the digitalization processing, an analog / digital conversion circuit for outputting the waveform data is provided.
An LL circuit, wherein the phase comparison circuit comprises two consecutive signals in the digitized waveform data.
Of the two waveform data, the first waveform data and the second waveform data are ternarized according to predetermined threshold values. 3
A digitizing circuit, a bit inverting circuit that inverts each bit of the first or second waveform data according to the result of the ternarizing by the ternary circuit, and a bit for the output data of the bit inverting circuit. Performs addition processing for each, and according to the result of the above bit inversion processing,
When the data "1" is added to the LSB and the addition result is output as phase difference data, and when the ternaryization result of the first waveform data and the second waveform data is a predetermined combination, the data A PLL circuit having a correction circuit which holds "1" for a predetermined time and outputs it to the carry input of the LSB of the adder circuit.