JP2003162555A - Integrated circuit configuration determination device, and its method and program - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To permit easy selection of a device parameter and a source voltage optimal in lowering the power consumption and speeding the operation of an integrated circuit. <P>SOLUTION: Data are inputted (step S1) for determining the property of each circuit block composing the integrated circuit, and a performance evaluation function of the integrated circuit is calculated (step S4) with respect to a plurality of parameter/vector values based on the inputted data. A parameter/ vector value that makes the performance evaluation function maximum or minimum is selected (step S5), and the selected result is outputted (step S6). As a result, the optimal integrated circuit configuration can be automatically discriminated. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an integrated circuit configuration judging device, a method thereof, and a program, and particularly optimizes a design parameter of a transistor applied to the integrated circuit and its power supply voltage from the viewpoint of speed and power consumption of the integrated circuit. For integrated circuit configuration prediction.

In the present specification, "integrated circuit configuration"
Is not only the circuit configuration itself, but also how transistor design parameter values such as threshold values, power supply voltage values, and operating frequencies are selected within the integrated circuit.
When there are a plurality of blocks, it is assumed that this is a concept representing the state of the integrated circuit including what value is assigned to each block.

[0003]

2. Description of the Related Art In the design of integrated circuits composed of CMOS transistors, transistor design and circuit design have usually been performed separately. In other words, the transistor designer considers that the gate length, gate oxide film thickness,
Design the transistor by selecting design parameters such as threshold value. At this time, the power supply voltage applied to the transistor is also specified at the same time. The circuit designer designs a desired circuit component using the given transistor, and further combines these components to construct an integrated circuit system.

In order for a circuit designer to realize a higher performance integrated circuit, a transistor designer may prepare and provide a plurality of types of transistors having different design parameters. As an example, a low-threshold transistor that is fast but has a large leak current and a high-threshold transistor that is slow but has a small leak current are provided. Alternatively, it may provide multiple options regarding the power supply voltage used. The circuit designer tries to realize higher performance by appropriately selecting and using a transistor or a power supply voltage that is suitable for the purpose from the given transistors.

A circuit designer can simultaneously use a plurality of types of transistors or power supply voltages as described above in the same integrated circuit. This is because there may be a plurality of blocks having different functions in the same integrated circuit, and transistors or power supply voltages suitable for the respective blocks may be different. In this case, the transistor and the power supply voltage can be selected for each block.

When a plurality of types of transistors or power supply voltages are given, which transistor or power supply voltage is selected depends on experience, considering the configuration and characteristics of the integrated circuit to be created by the circuit designer. It was based on. Therefore, if the circuit designer is inexperienced, the optimum selection may be erroneously made, and as a result, the performance and cost of the completed integrated circuit may be deteriorated as compared with the ideal case. . Further, there is a problem that the time required for the work of determining the optimum selection increases due to the complexity of the integrated circuit.

Conventionally, transistor designers have determined the design parameters of transistors. However, the optimum transistor design parameters differ depending on the circuit configuration used. Therefore, if the circuit designer, on the contrary, can specify the optimum transistor design parameter according to the configuration of the integrated circuit to the transistor designer, the performance of the integrated circuit may be improved. However, a general method for determining the optimum transistor design parameter based on the configuration of the integrated circuit has not been known.

[0008]

The first problem is that the characteristics of the transistors used in the integrated circuit and the selection of the power supply voltage are not optimally selected in the conventional design method. The reason is that this type of rough design relies on the experience of the practitioner.

The second problem is that the design time required for selecting the characteristics of the transistors and the power supply voltage used in the integrated circuit in the conventional design method is long. The reason is that the integrated circuit is complicated by using plural kinds of transistors and plural kinds of power supply voltages, and the outline design of this kind depends on the experience and manual work of the practitioner.

The third problem is that the transistor design is conventionally done by the transistor designer, and therefore the transistor design parameters are not always optimally set for a specific circuit configuration.

A first object of the present invention is to provide a means for predicting the optimum transistor or power supply voltage for use in an integrated circuit in a short time without depending on the experience of the circuit designer. Especially when multiple types of transistors or multiple power supply voltage values are used in the same integrated circuit, the optimum transistor or power supply voltage allocation for each circuit block can be made in a short time without depending on the experience of the circuit designer. It is to provide a means to predict.

A second object of the present invention is to make it possible to calculate an optimum transistor design parameter value or power supply voltage value according to the configuration of the integrated circuit and provide this information to the transistor designer. That is.

[0013]

An integrated circuit configuration judging device according to the present invention is an integrated circuit structure judging device for judging the optimum parameter selection in the design of an integrated circuit, and each circuit constituting the integrated circuit. Means for inputting data for determining the properties of the block; means for calculating a performance evaluation function of the integrated circuit for a plurality of parameter vector values based on the data; and a maximum or minimum performance evaluation function. It is characterized by including means for selecting a parameter / vector value to be selected and means for outputting the selection result.

Another integrated circuit configuration judging device according to the present invention is an integrated circuit structure judging device for judging an optimum parameter selection in designing an integrated circuit, wherein the characteristics of each circuit block constituting the integrated circuit are determined. Means for inputting data for determining, means for inputting options of each element of the selection target parameter vector, and performance of the integrated circuit with respect to possible allocation of the selection target parameter vector based on the data It is characterized by including means for calculating an evaluation function, means for selecting a parameter vector value that minimizes or maximizes the performance evaluation function from the calculation results, and means for outputting the selection result.

Still another integrated circuit configuration determination device according to the present invention is an integrated circuit configuration determination device for determining the optimum parameter selection in the design of an integrated circuit, and the property of each circuit block forming the integrated circuit. Means for inputting data for determining, and the adjustment target parameter vector for minimizing or maximizing the performance evaluation function of the integrated circuit for possible allocation of the adjustment target parameter vector based on the data. Means for adjusting each element, a means for selecting a parameter vector value that minimizes the result of minimizing the performance evaluation function or maximizes the result of adjusting the performance evaluation function, and outputs the selection result. And means for doing so.

Another integrated circuit configuration judging device according to the present invention is an integrated circuit structure judging device for judging the optimum parameter selection in the design of an integrated circuit, wherein the characteristics of each circuit block constituting the integrated circuit are determined. Means for inputting data for determining, means for inputting options of each element of the selection target parameter vector, and possible allocation of the selection target parameter vector and the adjustment target parameter vector based on the data Means for adjusting each element of the adjustment target parameter vector so as to minimize or maximize the performance evaluation function of the integrated circuit, and the result of minimizing the performance evaluation function among the adjustment results is minimum or maximum. Includes means for selecting a parameter vector value that maximizes the digitized result, and means for outputting this selection result And wherein the door.

The data for determining the property of each circuit block includes a power consumption value of the circuit block under an appropriately designated condition, and
As an element that defines the properties of each of the circuit blocks, the operating power of the circuit block under appropriately specified conditions,
It is characterized in that it includes standby power of the circuit block under an appropriately designated condition.

Further, the performance evaluation function is a function of the total power consumption of each circuit block, and
The performance evaluation function is a function of a sum of operating power and standby power of each circuit block. Further, the performance evaluation function is a function of the maximum delay time of the respective circuit blocks, which is weighted according to the required speed of each circuit block.

The integrated circuit configuration determination method according to the present invention is an integrated circuit configuration determination method for determining the optimum parameter selection in the design of an integrated circuit, and determines the property of each circuit block forming the integrated circuit. Data for calculating the performance evaluation function of the integrated circuit for a plurality of parameter vector values based on the data, and a parameter vector value that maximizes or minimizes the performance evaluation function. It is characterized by including a step of selecting and a step of outputting the selection result.

Another integrated circuit configuration determining method according to the present invention is an integrated circuit configuration determining method for determining the optimum parameter selection in the design of an integrated circuit, wherein the characteristics of each circuit block constituting the integrated circuit are determined. Inputting data for determination, inputting options of each element of the selection target parameter vector, and performance of the integrated circuit with respect to possible allocation of the selection target parameter vector based on the data It is characterized by including a step of calculating an evaluation function, a step of selecting a parameter vector value that minimizes or maximizes the performance evaluation function among the calculation results, and a step of outputting the selection result.

Yet another integrated circuit configuration determining method according to the present invention is an integrated circuit configuration determining method for determining the optimum parameter selection in the design of an integrated circuit, wherein the property of each circuit block constituting the integrated circuit is determined. Inputting data for determining the adjustment target parameter vector to minimize or maximize the performance evaluation function of the integrated circuit for possible allocation of the adjustment target parameter vector based on the data. Of adjusting each element, selecting a parameter vector value that minimizes the result of minimizing the performance evaluation function or maximizes the result of adjusting the performance evaluation function, and outputs the selection result. And a step of performing.

Another integrated circuit configuration determining method according to the present invention is an integrated circuit configuration determining method for determining the optimum parameter selection in the design of an integrated circuit, wherein the characteristics of each circuit block constituting the integrated circuit are determined. For inputting data for determining, for inputting options of each element of the selection target parameter vector, and for possible allocation of the selection target parameter vector and the adjustment target parameter vector based on the data Adjusting each element of the parameter vector to be adjusted so as to minimize or maximize the performance evaluation function of the integrated circuit, and the result of minimizing the performance evaluation function is the minimum or maximum of the adjustment results. The parameter vector value that maximizes the result of
And a step of outputting the selection result.

A program according to the present invention is a program for causing a computer to execute an integrated circuit configuration determining method for determining the optimum parameter selection in the design of an integrated circuit, and is for each circuit block constituting the integrated circuit. The process of inputting data for determining the property,
A process of calculating a performance evaluation function of the integrated circuit for a plurality of parameter vector values based on the data; a process of selecting a parameter vector value that maximizes or minimizes the performance evaluation function; And output processing.

Another program according to the present invention is a program for causing a computer to execute an integrated circuit configuration judging method for judging an optimum parameter selection in designing an integrated circuit, each circuit constituting the integrated circuit. The process of inputting data for determining the property of the block, the process of inputting options of each element of the selection target parameter vector, and the method of assigning the selection target parameter vector based on the data It is characterized by including a process of calculating a performance evaluation function of an integrated circuit, a process of selecting a parameter vector value that minimizes or maximizes the performance evaluation function of the calculation result, and a process of outputting this selection result. And

Still another program according to the present invention is a program for causing a computer to execute an integrated circuit configuration judging method for judging optimum parameter selection in designing an integrated circuit, each of which constitutes the integrated circuit. Inputting data for determining the property of the circuit block, and adjusting the performance evaluation function of the integrated circuit to a minimum or a maximum with respect to possible allocation of a parameter vector to be adjusted based on the data The process of adjusting each element of the target parameter vector, and the result of minimizing the performance evaluation function among the adjustment results is the minimum,
Alternatively, it is characterized by including a process of selecting a parameter / vector value that maximizes the maximized result, and a process of outputting this selection result.

Another program according to the present invention is a program for causing a computer to execute an integrated circuit configuration judging method for judging optimum parameter selection in designing an integrated circuit, each circuit constituting the integrated circuit. A process of inputting data for determining the property of the block, a process of inputting options of each element of the selection target parameter vector, and possible selection of the selection target parameter vector and the adjustment target parameter vector based on the data. The parameters to be adjusted to minimize or maximize the performance evaluation function of the integrated circuit with respect to the allocation method.
The process of adjusting each element of the vector, the process of selecting a parameter vector value that maximizes the result of minimizing or maximizing the result of adjusting the performance evaluation function among the adjustment results, and the selection result And output processing.

[0027]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described in detail below. The integrated circuit to be designed using the present invention is assumed to be configured by combining N circuit blocks (components). However, N is an integer of 1 or more.
First, referring to FIG. 5, FIG. 5 is a conceptual diagram of an integrated circuit (in this figure, N = 4). Each block is identified by the number i (= 1, 2, ..., N). In general, certain circuit blocks have different properties.
The present invention derives an optimum design according to the combination of these properties. In the optimization, the operating power and standby power are important as the data that describes the property of the circuit block.

Various values that determine the performance of the integrated circuit, such as transistor design parameters (threshold value, gate insulating film thickness, etc.), power supply voltage, operating frequency, etc., will be simply referred to as "parameters". These parameters may have common values in all blocks in FIG. 5, or may differ in all blocks. Thus, there is a degree of freedom in the construction of possible integrated circuits. The optimum design in the present invention is to optimize the allocation of these parameters and the setting of values.

FIG. 1 shows the configuration of an optimum integrated circuit configuration judging device according to the present invention, which normally includes a central processing unit 1, an input device 2, an output device 3, a memory 4 and a file device 5. A program 41 for carrying out the present invention is loaded from the file device 5 into the memory 4, and the central processing unit 1 executes a series of processes according to the description. The program for carrying out the present invention loads the circuit block data 42, which describes the properties of the circuit block, onto the memory 4 and uses it, if necessary.

The characteristics of each circuit block can be described by the following data.

(1) Operating power of the circuit block i under a certain operating condition: Pi (Xi, Yi, Zi) = Pi (G) (2) Selection target parameter vector at the time of operating power evaluation: Xi (3) Above Parameter vector to be adjusted at the time of evaluating the operating power: Yi (4) Determined parameter vector at the time of evaluating the operating power: Zi (5) Standby power of the circuit block i under a certain operating condition: Qi (Xi ', Yi', Zi ') = Qi (G') (6) Selection target parameter vector in the above standby power evaluation: Xi '(7) Adjustment target parameter vector in the above standby power evaluation: Yi' (8) The above standby power evaluation Time-determined parameter vector: Zi '

Where Xi, Xi ', Yi, Yi', Z
i and Zi 'are vectors having 0 or more parameters as elements. Selection target parameters are multiple (n)
Is given, and the maximum number that can be selected (integer of 1 or more, n is the maximum value) is a fixed parameter. The parameter to be adjusted is a parameter in which the value to be used can be arbitrarily selected within a certain continuous range, and the maximum number (m) of the values that can be used is determined. The determined parameter is a parameter whose value to be used is previously determined. For brevity, a bundle of these selection objects, adjustment objects, and determined parameter vectors is expressed as G = (X, Y, Z), and is simply referred to as a parameter vector. Selection target, adjustment target,
Each determined parameter vector X, Y, Z becomes a partial parameter vector of G.

The input of the data Pi and Qi can be performed as follows, for example. First, in a certain G, when the power consumption when the circuit block i is normally operated is evaluated, this corresponds to Pi (G) + Qi (G). Next, when the power consumption when the clock of the circuit block i is stopped is evaluated, this corresponds to Qi (G '). However, here, G ′ is equal to G except that the operating frequency F (which is usually one element of the determined parameter vector) is zero. Since Qi does not depend on F, Qi (G)
= Qi (G '). From the above, if the power consumption during normal operation and the power consumption during clock stop are input, since Pi is equal to the former minus the latter and Qi is equal to the latter, the property data of the circuit block can be determined. it can.

However, the above is an example of the data input method. The element values of the parameter vectors G and G ′, including the determined parameter vector values, do not necessarily have to match the element values of the parameter vector that is supposed to be used. Also, G does not necessarily have to be equal for different i. Further, G ′ does not necessarily have to be equal in different i. This is because if P or Q at a certain parameter vector is known, P and Q at an arbitrary parameter vector can be estimated using the delay / power model described later.

A program for implementing the present invention includes a power / delay model. This is a power / delay model formula p (G), q that describes how the operating power Pi, the standby power Qi, and the delay time Ti in each block i change when the parameter vector G changes.
(G) and t (G). As an example, in an arbitrary block i, the operating power when the parameter vector changes from G to G ′ is Pi (G ′) = Pi (G) * p (G ′) / p (G) (Equation 1) is obtained. In addition, the standby power is expressed by the equation q (G) as follows: Qi (G ') = Qi (G) * q (G') / q (G) (Equation 2) Further, the delay time is given by the following equation t (G): Ti (G ') = Ti (G) * t (G') / t (G) (Equation 3)

As described above, based on the operating power, the standby power and the delay time at a certain reference point G, the operating power, the standby power and the delay time at another parameter / vector value G'can be calculated. ing.

The program for carrying out the present invention includes an evaluation function E that numerically represents the performance of the integrated circuit. E is defined to be smaller (or larger) as the performance of the integrated circuit based on a certain criterion is higher. Hereinafter, the description will be made assuming that the smaller E is, the better. However, the definition that the larger E is, the better may be used. E is Pi, Qi, Ti (i = 1, 2, ..., N)
Is a function of. A function suitable for E is: E (X) = (P1 (X) + Q1 (X) + ... + PN (X) + QN (X)) * max (T1 (X) / K1, ..., TN (X) / KN ) There is ^R (equation 4).

Here, max () is a function for selecting the maximum argument. The power consumption of E (X) is small, and the smaller the delay time, the smaller the value. Ki (i =
1, ..., N) are numerical values for setting the speed ratio required for each block i, and a larger circuit block may be slower. R is a constant, for example, 2.

In an integrated circuit having a plurality of circuit blocks mounted together, the speed required for each circuit block may be different. It is important that the evaluation function E is defined so that it can be handled even in such a case. For that purpose, as shown in Expression 4, Ti may be weighted by using the numerical value Ki representing the ratio of the required speeds. Ki
May be determined using the operating frequency Fi of each block. This is because it is rational to determine that the higher the operating frequency is, the higher the speed is required.
To do so, Ki = F1 / Fi (i = 1, ..., N) (Equation 5) may be used. Alternatively, Ki may be given as one element of the determined parameter vector.

Using the above data, model formula and definition of E, an arbitrary parameter vector G = (X, Y,
It is possible to calculate E for Z). That is, the performance of the integrated circuit can be expressed numerically for any parameter vector.

As a first embodiment, a case will be described in which a finite number of choices are given for a certain parameter, and the optimum parameter value is determined from among them. FIG. 2 is a flow chart in this case. The present embodiment corresponds to the case where the number of X elements is 1 or more and the number of Y elements is zero.

Data describing the properties of each circuit block constituting the integrated circuit to be optimized is input from the input device (step S1). Further, as the selection target parameter vector X, selectable options Xt1, ..., Xtn
(The number of choices = n) and the maximum number nmax that can be selected from the choices are input from the input device (step S
2). Also, the determined parameter vector Z at the time of use
t is input from the input device (step S3). Here, in addition to a keyboard or the like as the input device, a file device in which input data generated by another program is recorded may be used.

Next, the assignment of X to each circuit block that minimizes the evaluation function E under the above constraint is determined.
Specifically, it is performed as follows.

(1) E is calculated for all possible allocations of X to N circuit blocks (step S4). As an example of possible allocation methods, when the number of blocks N = 2, the number of choices n = 3, and the maximum number of selections nmax = 2, it is assumed that Xti is allocated to block 1 and Xtj is allocated to block 2 [i, j]. When expressed as [1, 1], [2,
2], [3,3], [1,2], [2,1], [1,
3], [3,1], [2,3], and [3,2].

(2) As a result of (1), a method that minimizes E is selected from all possible X allocation methods for N circuit blocks (step S5).

Next, the X selected above that minimizes E
The allocation method and allocation value for each block are output to an output device such as a CRT (display device) or a printer (step S6). Here, a file device may be selected as the output device, and the result may be output in the form of a file so that another program can use it.

As a second embodiment, a case will be described in which an optimum parameter value is determined when a certain parameter can be arbitrarily selected. FIG. 3 is a flow chart in this case. The present embodiment corresponds to the case where the number of Y elements is 1 or more and the number of X elements is zero.

Data describing the properties of each circuit block forming the integrated circuit to be optimized is input from the input device (step S11). Further, the maximum number n that can be selected from the adjustment target parameter vector Y is input from the input device (step S12). Further, the determined parameter vector Zt at the time of use is input from the input device (step S13). Here, the input device may be a file device in which input data generated by another program is recorded in addition to a keyboard or the like.

Next, the assignment of Y of each circuit block that minimizes the evaluation function E is determined under the above constraint. Specifically, it is performed as follows.

(1) Perform (2) for all possible Y allocation methods for N circuit blocks. However, the specific value of Yti (i = 1, ..., M) is undecided at the time of this allocation, and only the combination of which block to allocate the m kinds of values is determined. As an example of possible allocation methods, the number of blocks N = 3 and the maximum number of selections m = 2
In this case, when Yti is assigned to the block 1, Ytj is assigned to the block 2, and Ytk is assigned to the block 3, when written as [i, j, k], [1, 1, 1], [1, 1, 2] , [1,
2,1,], [2,1,1], [1,2,2], [2,1
There are eight ways of allocation, [1, 2], [2, 2, 1], and [2, 2, 2].

However, since the specific value of Yti is undecided, for example, in [1, 1, 2] and [2, 2, 1], the same Y is assigned to blocks 1 and 2 and a different Y is assigned to block 3. Are equivalent in terms. Therefore, in this example, there are four substantially different allocation methods. It suffices to include "all that are substantially different" from the above "how to allocate all Ys".

(2) The Y value Yt1, which has not been determined in (1),
.., Ytm are determined so as to minimize E for each Y allocation method. For this, a known maximum / minimum value search algorithm such as simulated annealing may be used. Further, the value of E minimized by this is determined (step S14).

(3) As a result of (1), the one that minimizes E is selected from all possible allocations of m Ys to N circuit blocks (step S15).

Next, the Y selected above and minimizing E
The method of allocating each block and the allocation value are output to an output device such as a CRT or a printer (step S16).
Here, a file device may be selected as the output device, and the result may be output in the form of a file so that another program can use it.

As a third embodiment, a case will be described in which an optimum parameter value is determined when a finite number of choices are given for a certain parameter and other certain parameters can be arbitrarily selected. FIG. 4 is a flow chart in this case. The present embodiment corresponds to the case where both the numbers of X and Y elements are 1 or more.

Data describing the properties of each circuit block forming the integrated circuit to be optimized is input from the input device (step S21). In addition, options Xt1, ..., Xtn that can be selected as the selection target parameter vector X
(The number of choices = n) and the maximum number nmax that can be selected from the choices are input from the input device (step S2).
2). Further, the maximum number m that can be selected from the adjustment target parameter vector Y is input from the input device (step S
23). Further, the determined parameter vector Zt at the time of use is input from the input device (step S24). Here, as the input device, input data generated by another program is recorded in addition to the keyboard and the like.
It may be a file device.

Next, the assignment of X and Y of each circuit block that minimizes the evaluation function E is determined under the above constraint.
Specifically, it is performed as follows.

(1) Perform (2) for all possible X and Y allocation methods for N circuit blocks. However, at this time, the specific value of Yti (i = 1, ..., M) is undecided, and only the allocation method is determined. Xti and Z
t is predetermined. As an example of a possible allocation method, the number of blocks N = 2, the number of choices of X n = 2, X
If the maximum number of selections nmax = 2 and the maximum number of Y selections m = 2, Xti and Ytj are in block 1 and Xtk and Y are in block 2.
When the assignment of tl is expressed as [i, k, j, l], [1,1,1,1], [1,2,1,1], [2,
[1,1,1], [2,2,1,1], [1,1,1,]
2], [1,2,1,2], [2,1,1,2],
[2, 2, 1, 2], [1, 1, 2, 1], [1, 2,
2,1,], [2,1,2,1], [2,2,2,1],
[1,1,2,2], [1,2,2,2], [2,1,
There are 16 ways of assigning [2, 2] and [2, 2, 2, 2].

However, since the specific value of Yti is undecided, for example, [1, 1, 1, 2] and [1, 1, 2, 1] are assigned different Ys in the block 1 and the block 2. Are equivalent in terms. Therefore, in this example, there are eight different allocation methods. As mentioned above, "All X and Y
"Allocation method" of "all substantially different" may be included (step S25).

(2) The Y value Yt1, which has not been determined in (1),
, Ytm is determined so as to minimize E for each X and Y allocation method. For this, a known maximum / minimum value search algorithm such as simulated annealing may be used. The value of E that is further minimized is determined.

(3) As a result of (1), a method that minimizes E is selected from all possible X and Y allocation methods for N circuit blocks (step S26). However,
Y is selected by (2) so as to minimize E for each allocation method.

Next, the X selected above and minimizing E
CR and how to allocate each block of Y and Y
T, output to an output device such as a printer (step S2
7). Here, a file device may be selected as the output device, and the result may be output in the form of a file so that another program can use it.

In the above first to third embodiments,
The order of inputting various data may be changed arbitrarily. Further, in the output of the result, in addition to the case where E is minimized, other cases such as the second case from the smallest case, the third case from the smallest case, and the like may be arranged and output in order of size. In this way, the user of the program can judge, for example, that the first to third configurations are selected as candidates and an arbitrary case is selected.
For example, assume that the first configuration has a minimal E and the second configuration has a slightly lower E than the first configuration, but at a significantly lower manufacturing cost than the first configuration.

Generally, the smaller the number of parameters used, the smaller the manufacturing cost. In this case, the program user can select the second configuration, placing importance on the manufacturing cost. By outputting a plurality of configurations in the order of E, it is possible to give the program user such freedom of judgment.

When deciding how to allocate Xti or Y that minimizes E, the resulting type of Xti or Yti value may fall below the available number nmax or m. This means that it is advantageous in performance to reduce the number of types of X or Y. Also, Y that minimizes E
When ti is determined, as a result, the values of Yti having different i may be equal. This means that it is advantageous in performance not to change the value of Yti.

Next, the reason why the parameter vector that maximizes the performance of the integrated circuit can be determined by the above method will be further described. In deriving the mathematical formula below, the CMO
An integrated circuit composed of S transistors is assumed. However, the present invention can be applied to an integrated circuit other than a CMOS if the mathematical formula is changed accordingly.

In general, focusing on a certain integrated circuit or circuit block, its performance is defined by two factors, delay time and power consumption. Further, power consumption is divided into operating power and standby power. The smaller the delay time T, the operating power P, and the standby power Q, the better. However, there is a trade-off between them in that trying to reduce one of them increases the others, so it is necessary to optimally balance these three in order to improve the performance of the integrated circuit. Will be needed. Since such optimization is complicated, it is difficult to rely on intuition.

The delay time T is determined by the time required to charge or discharge the charge accumulated in the load capacitance, and is roughly given by T∝CVdd / Ion (Equation 6).

The operating power P is the power consumed to charge and discharge the load capacity, and has the property of being proportional to the operating frequency. This is roughly given by P = aWFCVdd ² (Equation 7). The standby power Q is the power consumed by the leakage current and is the power consumed regardless of the operating frequency. This is roughly given by Q = WIoff Vdd (Equation 8). Here, Vdd is the power supply voltage, F is the operating frequency, W is the total channel width of the transistor, C is the average load capacitance per unit channel width of the transistor, and a is the operating rate.

Ion is a drive current per channel width. This is the maximum drive current when the transistor is on, and is the current value that can flow when a voltage equal to the power supply voltage is applied between the source electrode and the gate electrode of the transistor. This is roughly given by Ion∝ (Vdd−Vth) ^A / (Tox + Dox) (Equation 9). Here, Vdd is the power supply voltage, Vth is the threshold voltage, and Tox is the gate oxide film thickness. Dox is a constant determined by the process technology and is approximately 10 nm.
A is a constant of 1-2.

Ioff is a standby current per unit channel width. This is a leakage current that constantly flows even if the transistor does not switch, and is given by Ioff = k1 * 10 ^{(-Vth / S)} + k2 * 10 ^{(-Tox / Sox)} (Equation 10). Here, k1, k2, S, and Sox are constants determined by the transistor design and the process technology used.

W is proportional to the circuit scale. C is determined by the average number of fanouts and the average wiring length. a is the average number of switching transistors in the clock period. The above is determined by the details of the circuit configuration, and usually cannot be arbitrarily changed. Other than these, T,
The parameters that greatly affect P and Q are F, Vdd, Vth,
Tox. Thus, these are the elements of the parameter vector that are important in the optimization according to the invention.

If the gate oxide film was thick enough, the leakage current from the gate electrode of the MOS transistor could be ignored. However, in a MOS transistor having a gate length of 0.18 μm or less, since the gate oxide film is thinned to 3 nm or less, leakage current through the gate oxide film becomes a problem. In consideration of this point, in Equation 9 and Equation 10,
It also takes into account the dependence on Tox.

P (G), q (G) in equations 1 to 3,
It is clear that t (G) can be easily determined given physical model equations such as equations 6-10. Equation 6
As Expression 10, a simple expression is used for convenience of explanation. Although these are actually good approximations, more complicated parameter dependence may be assumed in order to describe T, P, and Q with higher accuracy. As an example, C also includes the capacitance of the transistor itself, and thus depends slightly on Tox. Therefore, C may be given as a function of Tox. More generally, the model expressions of Expressions 6 to 10 may be replaced with more complicated expressions with high accuracy. The formula that serves this purpose is:
Known circuit simulation transistor model formulas can be used.

For simplification of the explanation, in Expressions 6 to 10, it is neglected that the CMOS is composed of an nMOS transistor and a pMOS transistor. Since these simplifications do not relate to the essence of the present invention, simplified Equations 6 to 10 are shown above.

Normally, W, Ion, and Ioff have different values for nMOS and pMOS. Therefore, equations 6 to 12
W, Ion, Idff in (Equation shown below) are nMOS
And the value in pMOS can be defined as an effective average. Regarding W, for example, the total channel width Wn in the nMOS and the total channel width W in the pMOS are
The average of p may be defined as W = (Wn + Wp) / 2 (Equation 11).

Ion in the equations 6 and 9 can be defined as an effective average of the drive current Ion in the nMOS and the drive current Ion, p in the nMOS and the pMOS. That is, 1 / (IonW) = {1 / (Ion, nWn) + 1 / (Ion, pWp)} / 2 (Equation 12) may be defined. Here, the reason for taking the average of the reciprocal is
This is because the delay time in Equation 6 is proportional to the reciprocal of Ion, and the total delay time can be regarded as the average of the delay due to the nMOS and the delay due to the pMOS.

Ioff in equations 8, 10 and 12 is n
It can be defined as an effective average of the standby current Ioff, n in the MOS and the standby current Ioff, p in the pMOS. That is, Ioff W = (Ioff, n Wn + Ioff, p Wp) / 2 (Equation 13) may be defined.

The trade-off described above is expressed by equations 6-10.
In order to reduce T, Vdd should be raised or Vth should be lowered. However, increasing Vdd increases P and decreasing Vth increases Q. To reduce P, lower Vdd. However, if this is done, T will increase, and to prevent this, if Vth is lowered, Q will increase. Vth to reduce Q
Should be raised. However, if this is done, T will increase, and if Vdd is increased to prevent this, P will increase. Thus, there is a trade-off relationship between T, P, and Q.

Conventionally, while the transistor size is large and Vdd is high (for example, 5 to 2.5 V), even if Vth is set so that Q is sufficiently small (for example, 0.5 V), Vth
Was smaller than Vdd, so a sufficient Ion could be secured. From this state, miniaturize the transistor size,
Also, lowering Vdd reduces T primarily due to C reduction (due to size reduction). Focusing on P, N is increased because the degree of integration is increased by miniaturization, and F is increased due to the improvement in speed, but P is not increased due to the decrease in C and Vdd. If Vth is sufficiently high, Q can be ignored.

As described above, by simultaneously miniaturizing the transistor and lowering the power supply voltage, the speed and the degree of integration could be improved without increasing the power consumption. However, when miniaturization of the transistor progresses and Vdd falls below 2V, according to the equation 9, if Vth is made large enough to sufficiently suppress Q, the deterioration of Ion becomes large, and it becomes difficult to improve the performance even if miniaturized. To solve this problem, it is necessary to lower Vdd and Vth at the same time, but this increases Q, and Q cannot be ignored. Also, with miniaturization, Tox
However, this causes a gate leakage current, which also increases Q.

In such a situation, in order to optimize the integrated circuit configuration, it is necessary to consider the relationship among the three factors of T, P and Q, so it becomes difficult to intuitively determine the optimum parameters. .

In addition to the complexity described above, in recent years, with the improvement of the degree of integration, there is an increasing need to embed circuit blocks having different characteristics in the same integrated circuit. In this case, the performance of the integrated circuit as a whole may be improved by using different parameters for circuit blocks having different characteristics. Selecting the optimum parameters in such a case makes the determination of the optimum parameters much more difficult than in the case of a single circuit block because the number of parameters to be determined increases.

The present invention eliminates the above-mentioned difficulties by automatically executing the procedure already described by a computer so that the optimum integrated circuit configuration (or parameter) can be easily determined. An evaluation function E for expressing the performance of the entire integrated circuit by a simple one value is used. Evaluation function E is Ti, Pi, Qi
Given as a function of. i is a subscript for distinguishing circuit blocks. Furthermore, a power / delay model is used to reproduce how Ti, Pi, Qi change when the parameter vector is changed. further,
As data that defines the characteristics of each circuit block, T in each circuit block in a certain parameter vector
The data for inputting the values of i, Pi and Qi can be estimated.

As described above, the performance of the integrated circuit as a whole is directly expressed as a function of the value of the parameter vector in each block. By describing the performance of the integrated circuit as a function of the parameter vector, it becomes possible to automatically select the parameter vector that maximizes the performance by using a computer.

The input data is not necessarily T
It is not necessary to have all the data necessary to determine all of i, Pi, Qi. The performance of integrated circuits depends on power consumption and delay. In order to achieve the object of the present invention, it suffices to be able to determine which has relatively higher performance in different parameter vectors. Therefore, it suffices to know what ratio the power consumption and the delay time change with the change of the parameter vector, and it is not necessary to know all the absolute values of the power consumption and the delay time within the range where this condition is satisfied. Absent.

The most important parameters for adjusting P and Q are Vdd, Vth and Tox. So Vdd, Vth, T
Given that ox is an element of the parameter vector, the dependence of the delay time on the parameter vector is completely described by equations 6 and 9. That is, when the parameter vector changes from one value to another value, the multiplication factor of the delay time is completely determined by the equations 6 and 9. Furthermore, if Vdd, Vth, and Tox are equal, the delay time is often the same even if the circuit blocks are different. From the above, specific values T1, T2, ... In each block of T
It is not always necessary to input data for specifying such items.

On the other hand, the power consumption is the operating power P and the standby power Q.
Given by the sum of. The manner of dependence of P and Q on Vdd, Vth, and Tox is different from each other, as can be seen from Equations 7, 8, and 10. Therefore, even though the value of P + Q at a certain parameter vector value is known, it is not determined how many times P + Q will increase when the parameter vector changes to another value. In order to determine how many times P + Q is multiplied, the ratio of the magnitudes of P and Q at a certain parameter vector value needs to be known. Equation 1 shows how many times P and Q increase when the parameter vector changes.
And can be determined by Equation 2. In addition, if the initial ratio of P and Q is known, it is possible to determine how many times P + Q will increase when the parameter vector changes.

If there are a plurality of circuit blocks, then equation 4
To calculate the evaluation function of P1, Q1, P2
, Q2, ..., PN, QN data is needed to estimate the ratio between them. This is because unlike the case of T, the value of P or Q usually differs greatly between the circuit blocks mainly depending on the difference in the circuit scale. Such difference in value is the main factor that determines the property of the circuit block. Therefore, it is usually good to enter the values of P i and Q i for a certain parameter vector for all blocks.

In the above description of the embodiment, the power consumption is given as the input data, but Pi (G), Qi at a certain parameter vector value G is given.
The value of (G) or arbitrary data that can determine the ratio may be given as an input. For example, the value (Ci in each circuit block of C, a, W, and F in Expressions 6 to 8)
, Ai, Wi, Fi) may be used as the input data.

If the threshold value Vth to be used is sufficiently high and it is known that the leak current does not matter, Qi
The values of can be approximated to zero, and the input of data regarding Qi can be omitted. In this case, Vth should be the determined parameter.

When there are a plurality of circuit blocks, the power consumption of all the circuits is a simple sum of the power consumption of each circuit block. Therefore, it is desirable to select the evaluation function E so as to be a function of the total power consumption, as shown in the example of Expression 4.

When a plurality of circuit blocks are present and all blocks are required to operate with exactly the same delay, the delay time of all the circuits is determined by the slowest block. Or if the delay required in block i is Ki times the reference value,
The block having the maximum Ti / Ki determines the delay time of all circuits. Therefore, as the evaluation function E,
As shown in the example of equation (4), it is desirable to select it as a function of the maximum value of T1 / K1, ..., TN / KN.

Under the above conditions, E may be defined so as to increase (or decrease) as the power consumption increases and the delay time increases. Equation 4 is suitable as E, but the present invention is not limited to this, and E may be changed according to the purpose of optimization. For example, if it is desired to more emphasize the power consumption of the delay time and the power consumption, then M in Expression 4 may be reduced. Alternatively, in the case where it is sufficient that the total power consumption is less than or equal to a certain upper limit value, the evaluation function is constant when the total power consumption is less than or equal to the upper limit value, and the evaluation function sharply increases when the total power consumption exceeds the upper limit value. The function may be selected as E. Alternatively, in the case where Ti / Ki only needs to be less than or equal to a certain upper limit value, the evaluation function is constant and T
A function whose evaluation function sharply increases when the maximum value of i / Ki exceeds the upper limit value may be selected as E.

During the use of integrated circuits, the nature of circuit blocks is actually changing over time. For example, in the state where the calculation is being performed and the state where the input is waiting, the operating power Pi is generally large in the former case and small in the latter case. This is mainly due to the change of the operation rate a in the equation (7).
In the above description, the property of the circuit block is implicitly assumed to be an average of such time changes over a sufficiently long time. However, in order to suppress the power consumption of the integrated circuit, for example, when the load of the circuit block is heavy, the power supply voltage is increased to increase the processing capability, and when the load is light, the power supply voltage is reduced to suppress the power consumption. is there. That is, multiple operation modes (in the above example, high load mode and low load mode)
There is a case in which it is desired to change the parameter for each mode.

The present invention can also cope with the optimum parameter determination in such a case by the method described below. Since the property of the circuit block i differs depending on the mode, property data of the circuit block is required for each mode. Mode j of the circuit block i (j = 1, 2, ...,
The operating power and standby power in M) are Pij and Qij. The required speed ratio in mode j of the circuit block i is Kij. The appearance time ratio of mode j is Sj. As the property data of the circuit block, the above-mentioned information needs to be input. Some circuit blocks change their operation depending on the operation mode, while other circuit blocks may not change their operation. In order to handle such a block that is not distinguished by the operation mode, the property data of the circuit blocks may be set to be equal in different j as appropriate.

The evaluation function E corresponds to this: E (X) = (Si * P11 (X) + S1 * Q11 (X) + ... + S1 * PN1 (X) + S1 * QN1 (X) + ... + SM * P1M (X) + SM * Q1M (X) + ... + SM * PNM (X) + SM * QNM (X)) 'max (T11 (X) / K11, ..., TN1 (X) / KN1, ..., T1M (X) / K1M (X), ..., TNM (X) / KNM (X)) ^R (Equation 14) may be changed.

In the right-hand side of the equation 14, for the power, the sum weighted by the appearance time ratio of each operation mode is taken for all combinations of i and j. After all, this is nothing but the expected value of the total power consumption. Also, regarding delay, K
The R-th power of the maximum value weighted by ij is taken.

Normally, parameters such as threshold Vth and gate insulating film thickness Tox in the same circuit block, which are determined by the process, cannot be changed for each mode. In order to deal with this restriction, it is only necessary to exclude from the selection a configuration in which different process parameters are assigned to the same circuit block in the optimum configuration selection procedure.

Different power supply voltages Vdd can be assigned to different modes of the same circuit block. When the evaluation function becomes small in such a configuration,
This means that changing the power supply voltage for each operation mode is effective.

[0101]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS We want to realize an integrated circuit consisting of two blocks. The transistor used is Vth = 0.2
It is possible to select from three types of V, 0.3 V, and 0.5 V to two types. Vdd is determined to be 1.5V. Vdd = 2.0V, Vth = 0.5 based on past design data
When V and F = 100 MHz, P = in block 1
It was estimated that 1 W and Q = 1 mW. Also, Vdd = 1.5
When V, Vth = 0.3V and F = 100 MHz, it was estimated in the block 2 that P = 1W and Q = 10 mW. In addition, block 1 is 200MHz, block 2 is 100M
I plan to operate at Hz, block 1 is block 2
It needs to be twice as fast. At this time, Vth is an element of the parameter vector to be selected, and Vdd is an element of the determined parameter vector.

As circuit block data, G = (Vth, Vdd, F) = (0.5, 2.0, 100)
When, P1 = 1, Q1 = 0.001 G = (Vth, Vdd, F) = (0.3, 1.5, 100)
, P2 = 1, Q2 = 0.01 As the determined parameters at the time of use, Vdd = 1.5 F1 = 200 F2 = 100 K1 = 1 K2 = 2 is input, and the procedure of FIG. 4 is applied. Block 1
Vth = 0.2V and Vth = 0.5V in block 2 were optimal.

On the other hand, when the same procedure was performed assuming that only one type of Vth could be used, Vth = 0.3V was optimal, but at this time, the power consumption was 10% compared to the case of using two types of Vth. Increased. Therefore, it was determined to be effective to use two types of Vth. This is an example of the case where N = 2 in the first embodiment.

Suppose we want to realize an integrated circuit consisting of two blocks. The transistor used is Vth = 0.3
V has been determined. Vdd is undetermined, and up to two values can be freely selected. Vdd = based on past design data
When 2.0V, Vth = 0.5V, F = 100MHz,
It was estimated that P = 1 W and Q = 1 mW in block 1. Also, Vdd = 1.5V, Vth = 0.3V, F = 10
At 0 MHz, in block 2, P = 1W, Q = 1
It was estimated to be 0 mW. Block 1 is 200 MH
z, block 2 will operate at 100 MHz and block 1 needs to be twice as fast as block 2. At this time, Vdd becomes an element of the parameter vector to be adjusted, and Vth becomes an element of the determined parameter vector.

As circuit block data, G = (Vth, Vdd, F) = (0.5, 2.0, 100)
, P1 = 1 and Q2 = 0.001 G = (Vth, Vdd, F) = (0.3, 1.5, 100)
When, P1 = 1 and Q2 = 0.01 are used, Vth = 0.3 F1 = 200 F2 = 100 K1 = 1 K2 = 2 is input as a determined parameter and the procedure of FIG. 4 is applied. Block 1
It was optimal to set Vdd = 1.5V in the above and Vdd = 1.2V in the block 2.

On the other hand, when the same procedure was performed assuming that only one type of Vdd could be used, Vdd = 1.5V was optimal, but at this time, the power consumption was 20% compared to the case of using two types of Vdd. Increased. Therefore, it was judged to be effective to use two types of Vdd. This is an example of the case where N = 2 in the second embodiment.

Let us assume that we want to realize an integrated circuit consisting of two blocks. The transistor used is Vth = 0.2
It is possible to select from three types of V, 0.3 V, and 0.5 V to two types. Vdd is undecided, and only one value can be freely selected. Based on past design data, Vdd = 2.
At 0V, Vth = 0.5V, F = 100MHz, it was estimated that P = 1W and Q = 1mW in block 1. Also, Vdd = 1.5V, Vth = 0.3V, F = 100MH
When z, in block 2, P = 1 W, Q = 10 mW
Was estimated.

The block 1 is planned to operate at 200 MHz and the block 2 at 100 MHz, and the block 1 needs to be twice as fast as the block 2. At this time, Vth is an element of the parameter vector to be selected, and Vdd is an element of the parameter vector to be adjusted.

As circuit block data, G = (Vth, Vdd, F) = (0.5, 2.0, 100)
, P1 = 1, Q2 = 0.001 G = (Vth, Vdd, F) = (0.3, 1.5, 100)
When P1 = 1 and Q2 = 0.01 are used, K1 = 1 K2 = 2 F1 = 200 F2 = 100 are used as the determined parameters, and the procedure of FIG. = 0.2V, Vth = 0.5 in block 2
It was optimal to set V and Vdd = 1.3V in common.

On the other hand, when the same procedure is performed assuming that only one type of Vth can be used, Vth = 0.3V, Vdd =
1.5V was optimal, but at this time, power consumption increased by 30% compared to using two types of Vth. Therefore, it was determined that the use of two types of Vth had a great effect. This is an example of the case where N = 2 in the third embodiment.

An integrated circuit consisting of a single circuit block
Currently, power supply voltage Vdd = 2V, threshold voltage Vth = 0.5
Although it is used as V, it was unclear whether the use of Vdd and Vth is optimal for improving the performance. At this time, the operating power was 100 times the standby power. Therefore, let Vdd and Vth be two elements of the parameter / vector to be adjusted, and G = (Vdd, Vth) = (2.0,
In the case of 0.5), P (G) = 100 and Q (G) = 1 were used as input data. When the procedure of FIG. 3 was applied to this, the evaluation function became the minimum at Vdd = 1.8V and Vth = 0.3V. Therefore, Vdd = 1.8V, Vth = 0.
When I changed it to 3V, the operation speed hardly changed,
It was found that the power consumption was reduced by 20%. This is an example of the case where N = 1 in the second embodiment.

In a transistor for realizing a certain integrated circuit, it is desired to determine the optimum gate oxide film thickness. If the gate oxide film is too thick, Ion will be small, and if it is too thin, the leakage current of the gate will be large. Therefore, it is necessary to select an optimum value. Therefore, Vth and Tox are set as adjustable parameters, and Vdd = 2V is set as a determined parameter. V
Only one type of dd and Vth is used. As input data, G = (Vdd, Vth, Tox) = (2V, 0.4V,
P (G) = 1 W and Q (G) = 1 mW at 3 nm) were input.

When the procedure of FIG. 3 is applied,
The evaluation function became the minimum at Vth = 0.3 V and Tox = 2.2 nm. Based on this result, the thickness of the gate oxide film used for the transistor was determined to be 2.2 nm. This is the second
In the above embodiment, N = 1.

A high load mode (mode 1) and a low load mode (mode 2) are provided in an integrated circuit composed of a single block,
I want to use different power supply voltage for each. Since the clock frequency is reduced to 1/2 in the low load mode, the operating speed may be half of that in the high load mode. Both modes occur at equal time ratios. It is determined that the threshold voltage Vth = 0.3V. Vdd is a parameter to be adjusted. Under the above conditions, as circuit block data, when G = (Vdd, F) = (1.2,100), P11 = 1, Q12 = 0.01 G = (Vdd, F) = (1. 2100), P11 = 0.1, Q12 = 0.01 As determined parameters at the time of use, K11 = 1 K12 = 2 F1 = 200 F2 = 100 as input data, and the procedure of FIG. 3 was applied. However, the evaluation function became minimum at Vdd = 1.2V in mode 1 and Vdd = 0.9V in mode 2. Therefore, it is preferable to set the power supply voltage to 1.2 V in mode 1 and 0.7 V in mode 2, and it is possible to reduce the power consumption by 15% as compared with the case where Vdd is constant regardless of the mode.

[0115]

The first effect is that the optimum transistor or power supply voltage for use in an integrated circuit can be predicted in a short time without depending on the experience of the circuit designer. In particular, when a plurality of types of transistors or a plurality of power supply voltage values are used in the same integrated circuit, the optimum transistor or power supply voltage allocation for each circuit block can be made without relying on the experience of the circuit designer.
And it can be predicted in a short time. The reason is that the present invention expresses the property of the circuit or the circuit block and the performance of the circuit as a numerical value that does not depend on experience.
This is because the selection of the optimum transistor or the power supply voltage can be performed non-empirically and quickly by the computer.

The second effect is that an optimum transistor design parameter value or power supply voltage value according to the configuration of the integrated circuit can be calculated and this information can be provided to the transistor designer. The reason is that the present invention expresses the characteristics of the circuit or circuit block and the performance of the circuit as numerical values, so that the optimum transistor or power supply voltage can be determined by a mathematical procedure.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of an embodiment of the present invention.

FIG. 2 is a flowchart showing the operation of the first embodiment.

FIG. 3 is a flowchart showing the operation of the second embodiment.

FIG. 4 is a flowchart showing an operation of the third embodiment.

FIG. 5 is a conceptual diagram of an integrated circuit including a plurality of blocks.

[Explanation of symbols]

1 Central processing unit 2 input devices 3 output devices 4 memory 5 file devices 41 Control program 42 Circuit block data

Claims (30)

[Claims] 1. An integrated circuit configuration determination device for determining the optimum parameter selection in the design of an integrated circuit, comprising means for inputting data for determining the property of each circuit block forming the integrated circuit. , Means for calculating a performance evaluation function of the integrated circuit for a plurality of parameter vector values based on the data, means for selecting a parameter vector value that maximizes or minimizes the performance evaluation function, and the selection result An integrated circuit configuration determination device comprising: 2. An integrated circuit configuration determination device for determining the optimum parameter selection in the design of an integrated circuit, comprising means for inputting data for determining the property of each circuit block forming the integrated circuit. A means for inputting an option of each element of the selection target parameter vector, a means for calculating a performance evaluation function of the integrated circuit for a possible allocation of the selection target parameter vector based on the data, and this calculation An integrated circuit configuration judging device comprising: a means for selecting a parameter / vector value that minimizes or maximizes the performance evaluation function among the results; and a means for outputting the selection result. 3. An integrated circuit configuration determination device for determining the optimum parameter selection in the design of an integrated circuit, comprising means for inputting data for determining the properties of each circuit block forming the integrated circuit. Means for adjusting each element of the adjustment target parameter vector so as to minimize or maximize the performance evaluation function of the integrated circuit with respect to possible allocation of the adjustment target parameter vector based on the data; A means for selecting a parameter vector value that minimizes the result of minimizing the performance evaluation function among the results, or maximizes the result of maximizing the result.
An integrated circuit configuration determination device comprising: means for outputting the selection result. 4. An integrated circuit configuration determination device for determining the optimum parameter selection in the design of an integrated circuit, comprising means for inputting data for determining the property of each circuit block forming the integrated circuit. A means for inputting options of each element of the selection target parameter vector, and a minimum performance evaluation function of the integrated circuit for possible allocation of the selection target parameter vector and the adjustment target parameter vector based on the data. Means for adjusting each element of the adjustment target parameter vector so as to maximize or maximize, and a parameter vector that maximizes the result of minimizing or maximizing the result of the performance evaluation function among the adjustment results. An integrated circuit configuration judging device comprising means for selecting a value and means for outputting a result of the selection. 5. The integrated circuit according to claim 1, wherein the data for determining the property of each circuit block includes a power consumption value of the circuit block under an appropriately designated condition. Configuration determination device. 6. The element for defining the property of each circuit block includes an operating power of the circuit block under an appropriately designated condition and a standby power of the circuit block under an appropriately designated condition. Claim 1
5. The integrated circuit configuration determination device according to any one of 1 to 4. 7. The integrated circuit configuration determination device according to claim 1, wherein the performance evaluation function is a function of a sum of power consumption of each circuit block. 8. The integrated circuit configuration determination device according to claim 1, wherein the performance evaluation function is a function of a sum of operating power and standby power of each circuit block. 9. The performance evaluation function is a function of the maximum delay time of each circuit block, which is weighted according to a required speed of each circuit block. The integrated circuit configuration determination device according to any one of claims. 10. When at least one circuit block has a plurality of operation modes, data defining characteristics of the circuit block and parameters of the circuit block are independently assigned for each operation mode. The integrated circuit configuration determination device according to any one of claims 1 to 9. 11. An integrated circuit configuration determination method for determining the optimum parameter selection in the design of an integrated circuit, comprising the step of inputting data for determining the property of each circuit block forming the integrated circuit. Calculating a performance evaluation function of the integrated circuit for a plurality of parameter vector values based on the data; selecting a parameter vector value that maximizes or minimizes the performance evaluation function; And a step of outputting. 12. An integrated circuit configuration determination method for determining the optimum parameter selection in the design of an integrated circuit, comprising the step of inputting data for determining the property of each circuit block forming the integrated circuit. A step of inputting an option of each element of the selection target parameter vector, a step of calculating a performance evaluation function of the integrated circuit for possible allocation of the selection target parameter vector based on the data, and this calculation An integrated circuit configuration judging method comprising: a step of selecting a parameter vector value that minimizes or maximizes the performance evaluation function among the results; and a step of outputting the selection result. 13. An integrated circuit configuration determination method for determining the optimum parameter selection in the design of an integrated circuit, comprising the step of inputting data for determining the property of each circuit block forming the integrated circuit. Adjusting each element of the adjustment target parameter vector to minimize or maximize the performance evaluation function of the integrated circuit for possible allocation of the adjustment target parameter vector based on the data; Among the results, the step of selecting a parameter vector value that minimizes the result of minimizing the performance evaluation function, or maximizes the result of maximizing the result, and outputting the selection result are included. Circuit configuration determination method. 14. An integrated circuit configuration determination method for determining the optimum parameter selection in the design of an integrated circuit, comprising the step of inputting data for determining the property of each circuit block forming the integrated circuit. A step of inputting an option of each element of the selection target parameter vector, and a minimum performance evaluation function of the integrated circuit for the possible allocation of the selection target parameter vector and the adjustment target parameter vector based on the data. Adjusting each element of the adjustment target parameter vector so as to maximize or maximize, and a parameter vector that maximizes the result of minimizing or maximizing the result of the performance evaluation function among the adjustment results. A collection comprising the steps of selecting a value and outputting the result of this selection. Method for determining product circuit configuration. 15. The data for determining the property of each circuit block includes a power consumption value of the circuit block under an appropriately designated condition.
15. The integrated circuit configuration determination method according to any one of 1 to 14. 16. The element for defining the property of each circuit block includes an operating power of the circuit block under an appropriately designated condition and a standby power of the circuit block under an appropriately designated condition. The integrated circuit configuration determination method according to any one of claims 11 to 14. 17. The performance evaluation function is a function of a sum of power consumption of each circuit block.
15. The integrated circuit configuration determination method according to any one of 1 to 14. 18. The integrated circuit configuration judging method according to claim 11, wherein the performance evaluation function is a function of a sum of operating power and standby power of each circuit block. 19. The performance evaluation function is a function of a maximum delay time of each circuit block, which is weighted according to a required speed of each circuit block. Any one of the integrated circuit configuration determination methods. 20. When at least one circuit block has a plurality of operation modes, data defining characteristics of the circuit block and parameters of the circuit block are independently assigned for each operation mode. 20. The integrated circuit configuration judging method according to claim 11. 21. A program for causing a computer to execute an integrated circuit configuration determination method for determining an optimum parameter selection in designing an integrated circuit, wherein the property of each circuit block configuring the integrated circuit is determined. For inputting data for calculating the performance evaluation function of the integrated circuit for a plurality of parameter vector values based on the data, and a parameter vector value for maximizing or minimizing the performance evaluation function. A program including a process of selecting and a process of outputting the selection result. 22. A program for causing a computer to execute an integrated circuit configuration determination method for determining an optimum parameter selection in designing an integrated circuit, wherein the property of each circuit block configuring the integrated circuit is determined. For inputting data for the selection target parameter vector, processing for inputting options of each element of the selection target parameter vector, and a performance evaluation function of the integrated circuit for possible allocation of the selection target parameter vector based on the data. And a process of selecting a parameter vector value that minimizes or maximizes the performance evaluation function among the calculation results, and a process of outputting the selection result. 23. A program for causing a computer to execute an integrated circuit configuration determining method for determining an optimum parameter selection in designing an integrated circuit, the characteristic of each circuit block constituting the integrated circuit being determined. For inputting data for the adjustment, and each element of the adjustment target parameter vector so as to minimize or maximize the performance evaluation function of the integrated circuit with respect to possible allocation of the adjustment target parameter vector based on the data. Of the adjustment result, a process of selecting a parameter vector value that maximizes the result of minimizing or maximizing the result of the performance evaluation function among the adjustment results, and a process of outputting the selection result. A program characterized by including. 24. A program for causing a computer to execute an integrated circuit configuration determination method for determining an optimum parameter selection in designing an integrated circuit, wherein the property of each circuit block configuring the integrated circuit is determined. For inputting the data for the selection target parameter vector, processing for inputting the options of each element of the selection target parameter vector, and A process of adjusting each element of the parameter vector to be adjusted so as to minimize or maximize the performance evaluation function of the integrated circuit, and the result of minimizing the performance evaluation function of the adjustment results is minimized or maximized. The process of selecting the parameter vector value that maximizes the result and the process of outputting this selection result A program characterized by including. 25. The data for determining the property of each circuit block includes a power consumption value of the circuit block under an appropriately designated condition.
24. A program according to any of 24. 26. The element that defines the property of each circuit block includes an operating power of the circuit block under an appropriately designated condition and a standby power of the circuit block under an appropriately designated condition. The program according to any one of claims 21 to 24. 27. The performance evaluation function is a function of a total power consumption of each circuit block.
The program according to any one of 1 to 24. 28. The program according to claim 21, wherein the performance evaluation function is a function of a sum of operating power and standby power of each circuit block. 29. The performance evaluation function is a function of a maximum delay time of each circuit block, which is weighted according to a required speed of each circuit block. Any of the listed programs. 30. When at least one circuit block has a plurality of operation modes, data defining characteristics of the circuit block and parameters of the circuit block are independently assigned for each operation mode. The program according to any one of claims 21 to 29.