JP2003158523A - Packet communication apparatus - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a packet communication apparatus that can prevent overflow of a transfer purpose buffer means. SOLUTION: Buffers 100a, b store transmission packets generated by a CPU 1 and packets addressed to a communication apparatus 800 among the packets from the Ethernets (R) 820a, b. A transfer judgment circuit 200 transmits the packets to be sent to the Ethernet 820a or 820b via a MAC 300a or 300b. When the transfer circuit 200 discriminates that the packet from the Ethernet 820a is a packet addressed to another communication apparatus on the basis of a destination MAC address, the transfer circuit 200 transfers the packet to the Ethernet 820b via the MAC 300b. When the usage rate of transfer FIFO 130a, b exceeds a threshold value in a process of transmitting packets stored in the transmission FIFO 120a, b with priority, the priority of the transfer packet is set higher than that of the transmission packet and the transfer packet is transferred to the Ethernet 820a or 820b by taking precedence of the transfer packet over the transmission packet.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a packet communication device, and more particularly, it automatically transfers a transfer packet for transmitting / receiving packets to / from a plurality of communication targets and exchanging information between the plurality of communication targets. Relates to a packet communication device suitable for.

[0002]

2. Description of the Related Art As a communication device using a packet, there is known a device used for an IP telephone or the like which exchanges voice data using IP (Internet Protocol) based on Ethernet (registered trademark). . This type of packet communication device is a CP
U, two Ethernet controllers, transfer control circuit,
It is configured with memory etc., and one Ethernet controller is connected to HUB (hub) via Ethernet.
, The other Ethernet controller is connected to a PC (personal computer) via Ethernet, and the HUB and PC are connected via a communication device to reduce the number of Ethernet cables laid from the HUB. Has been done. In this packet communication device, when the destination of the packet received via each Ethernet is the communication device, the received packet is processed as it is, and for the packets of other destinations, the destination is judged and when necessary, It is designed to forward the packet to the other Ethernet. As a result, in this type of packet communication device, packets such as received mail addressed to the PC sent from the HUB and Internet information are transferred to the PC-side Ethernet, and
Sends e-mails from the user side or packets for Internet access to the HUB side, and also transmits the voice input from the handset as voice data and outputs the received voice data as voice from the speaker, thus providing a telephone function. Can be realized. In this case, there are two packets to be transmitted by the Ethernet controller connected to the HUB-side Ethernet, that is, a packet for voice data to be transmitted by the packet communication device as an IP telephone and a packet for transmission from the PC. , The HUB side Ethernet controller needs arbitration processing for arbitrating transmission packets and transfer packets.

In this case, since the IP telephone exchanges voice data requiring real-time processing, it is necessary to preferentially transmit a packet of voice data over a packet transmitted from the PC side. Therefore, the transmission packet is transmitted with priority over the transfer packet, but the IP telephone originally transmits only one packet every 10 to 20 ms, and the amount of packets to be transmitted is small, and the PC side which has relatively little real-time property. It does not interfere with forwarding packets from. However, when the amount of packets from the PC side becomes large, the transfer buffer for holding the transfer packets may overflow.

Therefore, as described in Japanese Unexamined Patent Publication No. 5-316147, a node is provided which holds a packet to be transmitted for each priority and transmits the packet held in each buffer in an arithmetic progression. By connecting packets in a ring shape, high-priority packets (transmission packets) are transmitted preferentially, and low-priority packets (transfer packets) are also given an opportunity to transmit, thereby overflowing the transmission buffer. It is also possible to adopt a configuration for preventing the above.

[0005]

DISCLOSURE OF THE INVENTION In the prior art,
Instead of an IP telephone, the packet communication device sends an image I
The case where the P-videophone is applied is not sufficiently considered, and when the packet communication device is applied to the IP videophone, the transfer buffer may overflow.

That is, in the IP videophone, the conventional I
In addition to voice data from the P telephone, video data having a large amount of data is transmitted and received, so that the amount of packets to be transmitted and received increases. However, in the IP videophone, the transmission packet transmitted from the IP videophone is transmitted with priority over the transmission of the packet from the PC side. Therefore, the packet transmission from the PC side is delayed, and the packet from the PC side is temporarily suspended. The transfer buffer that is temporarily stored overflows, causing packet loss. When a packet loss occurs, the packet is retransmitted in order to obtain accurate information, which leads to a decrease in communication efficiency of the Ethernet.

[0007] On the other hand, in recent years, in addition to Internet services that PCs exchange with no restrictions on access time such as e-mail and home page access, recently, communication such as video called streaming, Internet TV, and relay has been recently performed. The number of Internet services that require real time is increasing. In order to support such services, it is not possible to batch packets transmitted by PCs, and a QoS (Quality of Service) that manages priorities for each packet according to the real-time property required by each service is provided. Need to support.

However, as in the prior art, the packet loss due to the overflow of the buffer cannot be detected, and the fixed priority order is set for the packet. Cannot be allocated.

A first object of the present invention is to provide a packet communication device and a packet communication module capable of preventing the transfer buffer means from overflowing.

A second object of the present invention is to provide a packet communication device and a packet communication system capable of coping with the real-time property of services.

[0011]

In order to solve the first problem, the present invention provides a plurality of communication means for transmitting and receiving packets to and from a plurality of communication targets, and the plurality of communication means for transmitting. Packet generation processing means for generating a packet for processing and processing the packet received by the plurality of communication means, and a transfer buffer for holding a transfer packet for exchanging information between the plurality of communication targets. And a packet generated by the packet generation processing means and the transfer packet when the received packet received by the plurality of communication means is determined to be the transfer packet. One of the transfer packets held in the buffer means is designated communication corresponding to the communication target of the transmission destination or the transfer destination. And a transfer control unit for preferentially outputting to the stage, the transfer control unit increasing the priority of the transfer packet over the packet generated when the usage rate of the transfer buffer unit exceeds a threshold value. And a packet communication device configured to output the transfer packet to the designated communication means in preference to the generated packet.

In constructing the packet communication device, the transfer control means is instructed whether or not the packet received by the plurality of communication means is a packet to be processed by the packet generation processing means or the transfer packet. And a function of outputting the received packet to the packet generation processing means or the transfer packet means according to the result of the determination.

In constructing each of the packet communication devices, the following elements can be added.

(1) The transfer control means includes a priority order register that can be set by the packet generation processing means,
In the priority register, a priority changing threshold for the usage rate of the transfer buffer means is set.

(2) The transfer control means outputs a flow control packet to a designated communication means corresponding to a transfer source communication object when the usage rate of the transfer buffer means exceeds a flow control threshold value. I will do it.

(3) Receiving buffer means for temporarily holding a received packet received by the plurality of communication means,
The transfer control means outputs the flow control packet to the designated communication means corresponding to the communication target of the transmission source when the usage rate of the reception buffer means exceeds the flow control threshold value.

(4) A flow control register that can be set by the packet generation processing means is provided, and a flow control threshold value relating to the usage rate of the transfer buffer means or the reception buffer means is set in the flow control register. It will be done.

Further, in constructing the packet communication module, a plurality of communication means for transmitting and receiving packets to and from a plurality of communication objects and a transfer for exchanging information between the plurality of communication objects. Transfer buffer means for holding the packet; and when the received packet received by the plurality of communication means is determined to be the transfer packet, the received packet is output to the transfer buffer means, and the transmission packet and the transfer packet are transferred. A transfer control means for preferentially outputting one of the transfer packets held in the transfer buffer means to a designated communication means corresponding to a communication destination or a transfer destination, wherein the transfer control means When the usage rate of the transfer buffer means exceeds a threshold value, the priority for the transfer packet is set to the transmission packet. To be higher than, the transfer packet with priority to the transmission packet can be used which is formed by an output to the designated communication means.

In constructing the packet communication module, the following elements can be added.

(1) The transfer control means comprises a priority order register which can be set by the packet generation processing means,
In the priority register, a priority changing threshold for the usage rate of the transfer buffer means is set.

In order to solve the second problem, the present invention provides a plurality of communication means for transmitting and receiving a packet including an IP address and a port which is its auxiliary address to a plurality of communication targets, and the communication means for the packet. Priority determining means for determining a priority related to real-time property in accordance with the combination of the IP address and the port, a plurality of transmission buffer means for holding a transmission packet in association with the priority related to the real-time property, and the plurality of Among the packets for transmission held in the transmission buffer means, the packet with the highest priority is selected according to the judgment result of the priority judgment means and given priority to the designated communication means corresponding to the communication object of the transmission destination or the transfer destination. And a priority packet selecting means for selectively outputting the packet communication device.

In constructing the packet communication device, the transfer control means is instructed as to whether the packet received by the plurality of communication means is the packet to be processed by the packet generation processing means or the transfer packet. Judge,
It is possible to add a function of outputting the received packet to the packet generation processing means or the transfer buffer means according to the determination result.

In constructing each of the packet communication devices, the following elements can be added.

(1) The priority packet selecting means selects the packet held in the transmission buffer means when the usage rate of any one of the plurality of transmission buffer means exceeds a threshold value. It is output to the designated communication means in preference to other packets.

(2) The priority packet selection means includes a register that can be set by the packet generation processing means, and a threshold value relating to the usage rate of the transfer buffer means is set in the register.

Further, the present invention relates to a plurality of packet communication devices for transmitting and receiving packets including an IP address and a port which is its auxiliary address, and real-time property of packets transmitted and received between the plurality of packet communication devices. The packet communication system comprises a priority control unit that determines the priority order according to the combination of the IP address and the port, and the plurality of packet communication devices are connected in series with each other.

In constructing the packet communication system, as the plurality of packet communication devices, one of the packet communication devices that transmits and receives a packet including an IP address and a port which is its auxiliary address can be used.

According to the above-mentioned means, when the transmission packet is transmitted with priority over the transfer of the transfer packet,
When the usage rate of the transfer buffer means exceeds the threshold value, the priority of the transfer packet is set higher than that of the transmission packet (packet generated), and the transfer packet is given priority over the transmission packet to become the designated communication means. Since the data is output, overflow of the transfer buffer means can be prevented.

In this case, when the usage rate of the transfer buffer means becomes equal to or less than the threshold value, the transmission packet is preferentially transmitted, so that the transmission efficiency of the transmission packet can be prevented from being lowered.

When determining whether or not the received packet is a transfer packet, the load on the packet generation processing means is reduced by making a determination based on the address (MAC address) attached to the received packet. be able to.

On the other hand, when a packet including an IP address and a port which is its auxiliary address is transmitted / received, the priority order of the transmitted / received packet is set to the combination of the IP address and the port according to the real-time requirement of the packet. Because I am trying to decide according to
Packets can be transmitted and received in accordance with the contents of the service that change every moment, and real-time performance can be secured.

That is, the packet having the highest priority among the packets for transmission held in the plurality of transmission buffer means is selected according to the judgment result of the priority judgment means, and the selected packet is selected as the transmission destination or the transfer destination. By preferentially outputting to the designated communication means corresponding to the communication target,
Real-time property can be secured.

[0033]

BEST MODE FOR CARRYING OUT THE INVENTION An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a block configuration diagram of a packet communication device showing an embodiment of the present invention, and FIG. 2 shows a packet communication device according to the present invention as a 2-channel Ethernet (Ch
FIG. 3 is a block diagram of a packet communication system when it is adapted to an Ethernet network. In FIG. 2, a two-channel Ethernet communication device 800 as a packet communication device is provided with a communication path (communication means) for two channels, and the communication path of each channel is PH.
Y (Physical layer transcei
Ethernet) 82 via 810a and 810b
0a and 820b, respectively. Each of the Ethernets 820a and 820b has an Ethernet communication device 830 including a PC (personal computer) or the like.
a and 830b are connected. Each Ethernet 820
a and 820b are configured to operate independently of each other, and each Ethernet communication device 830a and 830b is connected to the standard IEEE through the Ethernet 820a and 820b.
By transmitting and receiving an Ethernet packet (hereinafter referred to as a packet) according to 802.3 and IEEE802.1Q / D, communication between devices can be performed. When packets are transmitted and received between the communication device 830a and the communication device 830b, the Ethernet 82
0a, Ethernet communication device 800, Ethernet 82
Via 0b. In this case, the two-channel Ethernet communication device 800 has a function of transmitting and receiving packets and transferring packets between the Ethernets 820a and 820b, which allows communication between the communication devices 830a and 830b. Communication can be performed via the channel Ethernet communication device 800.

When connecting a plurality of two-channel Ethernet communication devices 800 to each other, as shown in FIG.
If they are connected in series via the Ethernet, as shown in FIG. 4, the wiring length can be greatly reduced compared to the case where the communication devices 800 are connected via the HUB.

Hereinafter, the two-channel Ethernet communication device 8
A specific configuration of 00 will be described. As shown in FIG. 1, the 2-channel Ethernet communication device 800 has a CPU 1
A memory 2 and a 2-channel Ethernet communication module (hereinafter referred to as a 2-channel communication module) 4
And a bus 3 connecting them to each other. The 2-channel communication module 4 includes a bus I / F (interface) circuit 400, two buffers 100a,
100b, two Ethernet MACs (MediaAc
access control) 300a and 300b, and a transfer determination circuit 200.
a is connected to the Ethernet device 830a via the PHY 810a and the Ethernet 820a, and transmits and receives packets to and from the Ethernet device 830a.
That is, the MAC 300a is configured as a communication unit that transmits / receives a packet to / from the Ethernet device 830a as a communication target via the PHY 810a and the Ethernet 820a.

On the other hand, MAC 800b is PHY810b,
Ethernet device 830 via Ethernet 820b
It is connected to the wireless LAN device b, and sends and receives packets to and from the Ethernet device 830b. That is, MAC30
0b is configured as a communication unit that transmits / receives a packet to / from the Ethernet device 830b as a communication target via the PHY 810b and the Ethernet 820b.

In this case, the packets transmitted and received by the MACs 300a and 300b are classified into three types of packets of transmission, reception, and transfer in the 2-channel communication module 4 and 2-channel communication device 800. Therefore, in order to avoid confusion, the case where the two-channel communication device 800 and the two-channel communication module 4 transmit / receive a packet is hereinafter referred to as transmission (transmission), reception (reception), and transmission / reception.
Transmission and reception of packets by the ACs 300a and 300b will be referred to as packet transmission (transmission), reception (reception), and transmission / reception.

In the memory 2, as shown in FIG.
1 is a program 20a, a work area 20b that holds the execution state of the program 20a, and a transmission descriptor 2 that holds a packet for the two-channel communication device 800 to send to the Ethernet 820a, (820b).
1a, (21b), Ethernet 820a, (820
It is configured to include reception descriptors 22a and (22b) for holding the packet received from b).

On the other hand, the CPU 1 accesses the memory 2 and the 2-channel communication module 4 via the bus 3,
By executing the program 20a written in the memory 2,
The status (register) of the channel communication module 4 is accessed, and the reception descriptors 22a and 22b in the memory 2 are accessed.
The received packets stored in the memory 2 are read and processed, the transmitted packets are generated, and the generated transmitted packets are transmitted to the transmission descriptors 21a and 21b in the memory 2.
Is configured to write to. That is, CPU1
Generates a transmission packet for transmission by the MACs 300a and 300b, and at the same time, the MACs 300a and 300b
Is configured as a packet generation processing means for processing the packet received by.

FIG. 6 shows a specific configuration of the bus I / F circuit 400, the buffers 100a and 100b, and the transfer determination circuit 200. The bus I / F circuit 400 includes an input / output buffer 440, a selector 430, a control circuit 410 for controlling the input / output buffer 440 and the selector 430, and a register 4.
20. The selector 430 includes a reception FIFO (First FIFO) of the buffers 100a and 100b.
In First Out) 110a and 110b are selected, and the selected packet is output to the input / output buffer 440. The input / output buffer 440 stores the packet from the bus 3 in the buffer 100.
a, 100b of the transmission FIFOs 120a, 120b. That is, the control circuit 410
Is the transmission descriptors 21 a, 21 in the memory 2.
b, and the CPU 1 sends the transmission descriptor 21
When a packet is registered in a or 21b, the input / output buffer 440 is set to the input state and the transmission descriptor 2
The packets registered in 1a and (21b) are transferred to the transmission FIFOs 120a and (120b) via the bus 3. Similarly, the control circuit 410 controls the reception FIFOs 110a and 11a.
0b is monitored, and the reception FIFO is transmitted via the transfer determination circuit 200.
When a packet is written in the O 110a or 110b, the input / output buffer 440 is set to the output state and the selector 4
The packet is output to the reception FIFOs 110a and 110b by the selector 30, and the selected packet is transferred to the reception descriptors 22a and 22b in the memory 2 via the bus 3.

The buffers 100a and 100b are reception FIFOs 11 for temporarily holding the received packets, respectively.
0a, 110b, transmission FIFOs 120a, 120b for temporarily holding packets to be transmitted, and transfer FIFOs 130a, 13 used for transferring packets between the MAC 300a and the MAC 300b.
It is configured with 0b. That is, the transfer FIFO
130a and 130b are Ethernet devices 830a and 830
The transfer FIFO 130a is configured as a transfer buffer means for holding a transfer packet for exchanging information with each other.
0a holds a transfer packet for transfer to the Ethernet device 830b, and the transfer FIFO 130b stores the transfer packet.
Ethernet device 830b to Ethernet device 830
The transfer packet to be transferred to a is held.

The transfer determination circuit 200 includes a selector 210.
a, 210b, control circuits 220a, 220b for controlling the buffers 100a, 100b, and registers 230a, 230b for holding the states of the transfer determination circuit 200.
And a CA holding the determination information as to whether the packet received by the MAC 300a or 300b is received by the 2-channel communication device 800 and the 2-channel communication module 4 or is transferred to the other MAC 300a or 300b.
M (Content Addressable Mem)
ory) 240a and 240b, and the transmission FIFO 120a
Selector 210a for selecting any one of the packets from the transfer FIFO 130b and the output to the MAC 300a, the transmission FIFO 120b, and the transfer FIFO 1.
The selector 210b that selects one of the packets from the packet 30a and outputs it to the MAC 300b.

As shown in FIG. 7, the registers 230a and 230b are composed of six registers R2301 to 2306. Register R2301 is MAC300
This is a register for setting the processing (reception, transfer, reception & transfer, discard) when the destination MAC address of the packet received by a, 300b is not registered in the CAM 240a, 240b. The register 2302 is normally set to the MAC 300.
a, a packet sent by (300b) is transmitted FIFO1
20a, 120b or transfer FIFOs 130a, 130b is a register for setting which is prioritized, and normally the transmission FIFOs 120a, 120b are selected. Registers R2303 and R2304 are transmission FIFOs that perform priority switching.
O120a, 120b, transfer FIFO 130a, 130
This is a register for setting the threshold value of the usage rate of b (threshold value changing threshold value). The registers R2305 and R2306 are reception FIFOs 120a and 120b for activating the flow control.
This is a register for setting a threshold value (flow control threshold value) of the usage rate of the transfer FIFOs 130a and 130b. Register R
The threshold value in 2303 to R2306 can be selected from 0 to 100%, and when 0% is designated, it is invalidated. Further, each threshold is set by the CPU 1.

Each of the CAMs 240a and 240b is composed of a special memory called an associative memory, and as shown in FIG. 8, each entry has each MAC address and whether to receive, transfer, receive & transfer, or discard it. Processing information and work area are provided, MAC instead of address
The address is input, and the processing information of the entry having the MAC address that matches the input MAC address is output. The work area is CPU1.
Is used when updating an entry. In addition, if MAC addresses match in multiple entries, in
The processing number of the entry with the lowest dex number is output.
The setting and updating of the entries in the CAMs 240a and 240b are executed by the CPU 1.

The CAMs 240a and 240b having the above structure
Is used to determine whether the packet received by the MAC 300a or 300b is received, transferred, received & transferred, or discarded from the destination MAC address of the packet. That is, when the communication system shown in FIG. 2 is constructed, a MAC address is set as an address unique to each device for the Ethernet device 830a, the Ethernet device 830b, and the two-channel Ethernet communication device 800. Therefore, when the destination MAC address of the packet transmitted from the Ethernet device 830a is the destination MAC address of the Ethernet device 830b, the packet received by the 2-channel Ethernet device 800 is a transfer packet to be transferred to the Ethernet device 830b. . When the destination MAC address of the packet transmitted from the Ethernet device 830a is the destination MAC address for the 2-channel Ethernet communication device 800, it can be determined that the packet is to be received by the 2-channel Ethernet communication device 800.

For example, when the MAC address of index0 is input to the 2-channel Ethernet communication device 800, it is determined that this packet is a packet to be transferred to the Ethernet device 830a or the Ethernet device 830b, and the MAC address corresponding to indexN When a packet is received, it can be determined that the 2-channel Ethernet communication device 800 should receive the packet. At this time, if there is no entry having the matching MAC address, any of reception, transfer, reception & transfer, and discard is set by the register R2301.

In the transfer determination circuit 200 having the above-mentioned configuration, the control circuits 220a and 220b have the reception FIFO 11
0a, 110b, the transmission FIFOs 120a, 120b and the transfer FIFOs 130a, 130b are constantly checked for use, flow control is activated, and as shown in FIG. 9, selectors 210a, 210b are switched and MACs 300a, 3b are used.
00b determines whether to receive, transfer, receive & transfer, or discard the received packet.

First, when activating the flow control,
The usage rate of the reception FIFOs 110a and 110b is registered in the register R.
When the threshold specified in 2305 is exceeded or the transfer FI
The usage rates of the FOs 130a and 130b are the same in the register R2.
If the threshold value specified in 306 is exceeded, the MAC 300
A packet for flow control is transmitted to a and 300b. When the flow control packet is transmitted, the number of packets received by the MACs 300a and 300b exceeds the number of packets that can be received and transferred by the two-channel communication device 800, and the packet received by the MAC 300 cannot be processed and is discarded. prevent. That is, when the number of packets that the two-channel communication device 800 can receive and transfer exceeds the number of packets that the MAC 300a 300b receives, the packet source is temporarily suspended from transmitting the packet. It can prevent destruction.

Next, the control circuits 220a and 220b have the transmission FIFOs 220a and 220b and the transfer FIFO 130.
a, 130b usage rate is monitored, selectors 210a, 2
Control switching of 10b. Normal time, that is, transmission FIFO
When the usage rates of the O120a and 120b are less than or equal to the threshold value specified by the register R2303, and the transfer FIFO 130
If the usage rates of a and 130b are less than or equal to the threshold value specified by the register R2304, F specified by the register R2302
Packets output from the IFO are selectors 210a, 21
Selected by 0b. On the other hand, the transmission FIFO 120
If only the usage rates of a and 120b exceed the threshold value specified in the register R2303, the transmission FIFOs 120a and 12b
0b output packets are selectors 210a, 210
selected by b. Conversely, the transfer FIFO 130a,
If only the usage rate of 130b exceeds the threshold value specified by the register R2304, the transfer FIFOs 130a, 130b
The packet output by is selected by the selectors 210a and 210b. As a result, when the register R2302 is set to give priority to the transmission FIFOs 120a and 120b, transmission packets are transferred from the transmission descriptors 21a and 21b to the transmission FIFOs 120a and 120b frequently, that is, the transmission packets are transmitted with priority. Therefore, the transmission of the transfer packet is delayed, and the transfer FIFO 13
It is possible to prevent overflow of 0a and 130b.

Further, the control circuits 220a and (220b)
Is the destination MAC address CAN 240a, (240b) of the packet received by the MAC 300a, (300b).
Inquire, receive, transfer, receive & transfer, and determine whether to discard. When receiving, the reception FIFO 110
a, (110b), when transferring, transfer FIFO
130a, (130b) receive and transfer to receive FIFO 110a, (110b) and transfer FIFO 13
0a and (130b) for both MAC 300a,
The packet received by (300b) is written. When discarding, the packet is not written in any of the reception FIFOs 110a and (110b) and the transfer FIFOs 130a and (130b) and is discarded as it is.

Next, the packet transmission process will be described with reference to FIG. When performing packet transmission in the 2-channel communication device 800 and the 2-channel communication module 4, the 2-channel communication module 4 uses the CPU 1
When a start packet is received, the transmission packet is read from the transmission descriptors 21a and (21b) in the memory 2 under the control of the control circuit 410 of the bus I / F circuit 400,
Write to the transmission FIFO 120a, (120b), and transmit the packet data to the transmission FIFO 120a, (120b).
And sends it to the Ethernet 820a, (820b).

Next, packet reception and transfer processing will be described.
As shown in FIG. 11, when the MAC 300a, (300b) receives a packet, the transfer determination circuit 200 checks the destination MAC address of the packet and determines whether it is a packet to be received or a packet to be transferred. When it is determined that the packet should be received, the packet is received in the FIFO.
Write to 110a and (110b). In response to this, the bus I / F circuit 400 causes the reception FIFO 110a, (110
The packet is read from b), and this packet is received via the bus 3 in the reception descriptor 22a in the memory 2,
Write to (22b).

On the other hand, when transferring a packet, the transfer determination circuit 200 transfers the packet received by the MAC 300a, (300b) to the transfer FIFO 130a, (130).
Write to b). In response to that, MAC 300b, (3
00a) reads the packet from the transfer FIFOs 130a and (130b), and reads the packet from the Ethernet 820b and (82).
0a) respectively.

Here, the packets transmitted by the MACs 300a, (300b) are transmitted by the transmission FIFOs 120a, (120).
b) and transfer FIFOs 130b and (130a).
Arbitration is performed to determine whether or not the O packet is transmitted with priority. Normally, the packets in the transmission FIFOs 120a and 120b are preferentially transmitted, but when the packets are sequentially transferred from the transmission descriptors 21a and 21b to the transmission FIFOs 120a and 120b, the transmission FIFOs 120a and 120b are transmitted.
Since the packets in a and 120b are transmitted with priority,
The output of the packets in the transfer FIFOs 130a and 130b is delayed, flow control is activated, and the transfer buffer overflows, so that the communication efficiency of the Ethernets 820a and 820b is reduced.

Therefore, the transfer control circuit 200 according to the present embodiment uses the transmission FIFOs 120a and 120b and the transfer FI.
The usage rate of the FOs 130a and 130b is constantly monitored, and if the usage rate of the transfer FIFOs 130a and 130b exceeds a predetermined threshold value (priority change threshold value), the transfer FI
FO130b, packet in (130a) is transmitted FIFO
By sending the packets in the O120a and (120b) with priority, the transfer FIFOs 130a and 130b are prevented from overflowing and the communication efficiency of the Ethernets 820a and 820b is prevented from being lowered.

That is, the transfer determination circuit 200 and the bus I /
When the usage rate of the transfer FIFOs 130a and 130b exceeds a threshold value (priority order changing threshold value), the F circuit 400 sets the priority order of the transfer FIFOs 130a and 130b to CP.
MAC 300 that specifies the transfer packet with a higher priority than the transmission packet generated by U1 and prioritizes the transmission packet.
a or a transfer control means for outputting to the MAC 300b.

Thus, according to this embodiment, the transfer F
When the usage rates of the IFOs 130a and 130b exceed the threshold value, the priority of the transfer packet is set higher than that of the transmission packet, and the transfer packet is output to the designated communication means in preference to the transmission packet. F
Avoid overflow of IFOs 130a, 130b,
It is possible to prevent a decrease in communication efficiency of the Ethernets 820a and 820b.

Through the above processing, the two-channel communication module 4 can realize packet transmission, reception, and transfer processing.

Next, the packet communication device according to the present invention will be described with reference to FIG.
An embodiment of a packet communication system applied to a P telephone will be described with reference to FIG.

The IP telephone 8000a is connected to two Ethernets 820a and 820b, one Ethernet 820a is connected to a HUB 8100 connected to the Internet or an intranet, and the other Ethernet 820b is a PC as an Ethernet communication device 830. It is connected to the. The HUB8100 is a WAN (Wide Area) such as the Internet or an intranet.
IP phone 8000b via Network),
Data sensor 820 holding homepage data
It is connected to 0.

The IP telephone 8000 has a two-channel communication device 800, two PHYs 810a and 810b, inside.
A receiver 8010, an A / D converter 8020 for converting an analog voice input signal into a digital signal, and a D / A converter 8030 for converting a digital signal into an analog voice output signal are provided. There is.
The handset 8010 includes a microphone 8011 that converts voice into an analog signal and a speaker 8012 that converts a voice output signal that is an analog signal into voice.

IP phone 8000a and IP phone 8000b
Calls to and from are made as follows. IP phone 8
The voice input from the microphone 8011 of the 000a is A /
2 after being converted into a digital signal by the D converter 8020
It is input to the channel communication device 800. The CPU 1 in the two-channel communication device 800 converts the digital signal into a voice packet and transmits it as a transmission packet from the MAC 300a to the Ethernet 820a. Ethernet 82
The packet sent to 0a is sent from HUB8100a to W
It is sent to the other party's IP telephone 8000b through the AN.
Upon receiving the voice packet transmitted by IP telephone 8000a, the other party's IP telephone 8000b converts the received voice packet into voice data and outputs it to D / A converter 8030 by CPU 1 in two-channel communication device 800. . This voice data is converted into a voice signal which is an analog signal by the D / A converter 8030, and is output as voice from the speaker 8012. Communication processing from IP phone 8000b to IP phone 8000a is similarly performed, and a call is realized between IP phone 8000a and IP phone 8000b.

Next, the process of reading the home page in the data center 8200 by the PC 830 connected via the IP telephone 8000a is performed as follows. PC83
When 0 uses a web browser to display a home page, a packet having URL information of the home page to be displayed is transmitted to the Ethernet 820b. This packet is transmitted to the MAC 300b of the 2-channel communication device 800.
When the packet is received, since the destination MAC address of this packet is not addressed to the IP telephone 8000, it is transferred from the MAC 300a to the Ethernet 820a. The transferred packet passes through the HUB 8100 and arrives at the data center 8200 via the WAN. P at the data center 8200
The URL information is read from the packet transmitted by the C830, and the corresponding homepage information is packetized and transmitted. The packet transmitted from the data center 8200 arrives at the HUB 8100 via the WAN, and then is received by the MAC 300a in the two-channel communication device 800 via the Ethernet 820a. At this time, when the transfer determination circuit 200 in the two-channel communication device 800 searches the destination MAC address of the packet transmitted from the data center 8200 and determines that it is addressed to the PC 830, it transfers this packet to the Ethernet 820b. PC8
When 30 receives the packet, the PC 830 extracts homepage data from the received packet and displays it on the web browser. With the above processing, the IP telephone 800
0 and the PC 830 will be communicated.

Next, another embodiment of the present invention will be described with reference to FIG. In this embodiment, a 2-channel Ethernet communication device 850 is used as a packet communication device instead of the 2-channel Ethernet communication device 800 shown in FIG. In this embodiment, the two-channel Ethernet communication device 850 and the Ethernet communication device 8
Regarding the packets transmitted / received to / from the packets 30a and 830b, considering that the degree of real-time requirement varies depending on the service to which the packet belongs, the priority order of the transmitted packets is decided according to this service. That is, since services can be distinguished by a combination of an IP address and a port which is its auxiliary address, in the present embodiment, priorities are assigned according to the combination of an IP address and a port, in descending order of real-time requirement. I have decided. 2-channel communication device 850
Determines the order of packets to be transmitted and transferred according to this priority order to realize the real-time property (QoS) required by each service.

Two-channel Ethernet communication device 850
Is provided with a CPU 1 as a packet generation processing means, a memory 2 for storing programs and the like, and a two-channel communication module 4, and the respective units are connected via a bus 3.

The two-channel communication module 4 has a bus I / F circuit 450 for exchanging data with the CPU 1 and the memory 2 via the bus 3, buffers 150a, 150b for holding transmission, reception and transfer packets, and packet transmission / reception. MACs 300a and 300b for sending and receiving, and M
A transfer determination circuit 250 that determines whether to receive or transfer the packet received by the AC 300a or 300b, and the MA.
When C300a and 300b send a packet,
The priority order determination circuit 500 determines the priority order of the transmission and transfer packets held in the buffers 150a and 150b from the combination of the IP address and the port.

2-channel Ethernet communication device 850,
When determining the priorities for the Ethernet communication devices 830a and 830b, for example, one of the communication devices is used as a priority control unit, and this priority control unit provides the priority service according to the combination of the IP address and the port. Each communication device is determined at any time and the priority order according to this determination is transmitted to each communication device.

As shown in FIG. 14, the buffers 150a and 150b include a reception FIFO 160, a transfer FIFO 165 for temporarily holding a packet to be transferred, and a transmission FIFO 170-1 for holding N pieces of transmission and transfer packets.
It is composed of a selector 180 for selecting the output of N and N transmission FIFOs 170. The transmission FIFO
The priority order of 170 is set such that the transmission FIFO 170-1 has the highest priority and the transmission FIFO 170-N has the lowest priority. Each of the buffers 150a and 150b includes a bus I / F circuit 450, an output 190 of the reception FIFO 160, an output 191 of the transfer FIFO 165, and a transmission FIFO 170-.
1 to N are connected to the input 192, and the transfer determination circuit 25
0 means an input 195 to the reception FIFO 160 and a transfer FI.
Input 196 to FO 165, sending FIFO 170-1 ~
The output 197 of the selector 180 for selecting the output of N and the selection control signal 198 of the selector 180 are connected.

Here, the reception, transfer, and transmission FIFOs in the buffers 150a and 150b are respectively received by the reception FIFO 16
0a and 160b, transfer FIFOs 165a and 165b, and transmission FIFOs 170-1 to Na and 170-1 to Nb. In this case, the transmission FIFO constitutes the transmission buffer means for holding the transmission packet in association with the priority regarding the real-time property.

As shown in FIG. 15, the priority determination circuit 500 is composed of two CANs 510a and 510b and registers 520a and 520b. Each CAN5
As shown in FIG. 16, each of the entries 10a and 510b is a combination of information indicating whether the IP address is IPv4 (version 4: 32 bits) or IPv6 (version 6: 128 bits), and an IP address and a port. When,
Correspondingly, priority information and a work area indicating which of the transmission FIFOs 170-1 to 170-N is to be transferred are set, and the combination of the IP address and the port is input instead of the address. The priority information of the entry having the combination of the input IP address and the port that matches the input is output. The work area is used when the CPU 1 updates the entry. When the combination of the IP address and port matches in multiple entries, the index number is 1
Output the information of the youngest entry. The CPU 1 sets and updates the entry of the priority determination circuit 500.

On the other hand, the registers 520a and 520b have three registers R5201 and R52, as shown in FIG.
02 and R5203. Register R52
01 is set by the CPU 1, and the bus I / F circuit 45
The output value when the combination of the IP address and the port inquired from 0 is not registered in the CAM 510 is held. The IP address at that time is held in the register R5202, the port is held in the register R5203, and the update request of the CAM 510 is output to the CPU 1 as an interrupt.

The bus I / F circuit 450 includes an input / output buffer 440, a control circuit 460, selectors 481 and 482a,
It is provided with 482b. The control circuit 460 is
The transmission descriptors 21a and 21b, the transfer FIFOs 165a and 165b, and the reception FIFO 160 in the memory 2
a and 160b are respectively monitored, and when the CPU 1 detects that the packet is registered in the transmission descriptors 21a and 21b, the input / output buffer 440 is set to the input state, and the transmission descriptor 21a and the transmission descriptor 21a are transmitted via the bus 3.
The packet in 21b is read. From the combination of IP address and port in the packet read after this,
Buffers 150a and 150 in the CAMs 510a and 510b
Inquiring whether or not to transfer to the transmission FIFOs 170-1 to Na, b in b, switching the selectors 482a, 482b to the input / output buffer 440 side, and determining the packet output from the input / output buffer 440 by the CAMs 510a, 510b. It is transferred to the output FIFOs 170a and 170b. Similarly, the control circuit 460 controls the transfer determination circuit 250.
After confirming that the packet has been transferred to the transfer FIFOs 165a and 165b, the priority order determination circuit 500 determines whether to transfer to the transmission FIFOs 170-1 to Na, b based on the combination of the IP address and the port of the packet. Query and transfer selectors 482a and 482b F
Transfer FIFO 1 by switching to the side of IFO 165b, 160a
65b, 165a packets from the CAM 510a, 5
Transfer FIFO 170a, 170 defined by 10b
transfer to b.

Further, according to the transfer determination 250, MAC3
Packets received by 00a and 300b are received FIFO
When transferred to 160a and 160b, the control circuit 460
Sets the input / output buffer 440 to the output state and outputs the selector 481 to the output 190 of the reception FIFOs 160a and 160b.
a, 190b are selected, and the selected packet is sent via the bus 3 to the reception descriptors 22a, 22a in the memory 2.
transfer to b.

On the other hand, the transfer determination circuit 250, as shown in FIG. 19, has control circuits 260a and 260b and a register 27.
0a, 270b and CAMs 280a, 280b. The control circuits 260a and 260b are MAC
The CAM 28 receives the packets received by the 300a and 300b.
0a, 280b, and determines whether to receive, transfer, receive & transfer, and discard, and buffer 1
It controls the selector 180 in 50a and 150b. CAMs 280a and 280b have MAC3
00a, 300b receive and forward packets,
It is configured to hold information regarding reception, transfer, and discard.

Specifically, the registers 270a and 270b
Is the three registers R2701,
It is configured to include R2702 and R27003. In the register R2701, the destination MAC address of the packet received by the MAC 300a, 300b is CAM280.
a, 280b when not registered, receive, transfer, receive &
It is set to transfer and discard. Register R2
The transmission FIFO 170-1 to 702 performs priority switching.
Each threshold value of the usage rate common to Na and b is set. The register R2703 has a transmission FIF for activating the flow control.
A threshold value of the usage rate common to O170-1 to Na and b is set. Each threshold can be selected from 0 to 100%, and 0
When% is specified, it is invalid.

Each of the control circuits 260a and 260b monitors the usage rate of the N sending FIFOs 170-1 to 170-N and sends the sending Fs.
When the usage rate of the IFOs 170-1 to N is less than or equal to the threshold value held in the register 2702, the control signal 198 for selecting the output of the sending FIFO 170 holding the packet with the highest priority is output to the selector 180. To do. On the other hand, the usage rate of the transmission FIFO 170 is determined by the register R2702.
If it exceeds the threshold value set in (1), the selection signal 198 for selecting the output of the transmission FIFO 170 that exceeds the threshold value is output to the selector 180.

Similarly, the transmission FIFOs 170-1 to 170-1.
If even one of the usage rates of Na and b exceeds the threshold value (threshold value for flow control) held in the register R2703, the packets for flow control are MAC 300a, 300.
It is output to the Ethernets 820a and 820b via b.

As a result, the sending FIFO 17 is normally operated.
The packets held in 0-1 to N are MAC300
a, 300b, and the transmission FIFO 17
The overflow of 0 can be prevented.

The destination MAC address of the packet received by the MAC 300a, 300b is set to CAM 280a, 2
80b, inquire, receive, transfer, receive & transfer, and determine whether to discard, receive FIFO1 if receive
When transferring to 60a and 160b, transfer FIFO1
65a, 165b, when receiving & transferring, receive FI
FO 160a, 160b and transfer FIFO 165a, 16
5b. When discarding, receive F
IFOs 160a and 160b and transfer FIFOs 165a and 1
Do not transfer to either 65b.

Next, the operation of the two-channel communication device 800 will be described. First, when performing packet transmission processing, as shown in FIG.
Monitors the transmission descriptors 21a and 21b in the memory 2, and the CPU 1 transmits the transmission descriptors 21a and 21b.
When the packet is written to the bus I / F circuit 450, the bus I / F circuit 450 reads the transmission packet from the transmission descriptors 21a and 21b, and inquires the priority determination circuit 500 of the priority of the packet from the combination of the IP address and the port of this packet. Transmission FIFO corresponding to priority
170a, 170b. Next, the transfer determination circuit 2
The packet 50 transfers the packet having the highest priority from the sending FIFOs 170-1 to Na, b to the MAC 300a, 300b, and transmits this packet to the Ethernet 820a or the Ethernet 820b. In the example of FIG. 21, when the IP address of the transmission packet is 3 and the port is 5, the priority is 2, so the packet is transferred to the transmission FIFO 170-2a. Since the sending FIFO 170-1a is empty, this packet is the packet with the highest priority,
It is transmitted to the Ethernet 820a.

Next, in the reception and transfer processing, as shown in FIG. 22, when the MAC 300a, (300b) receives a packet, the transfer determination circuit 250 causes the packet destination MA to be transmitted.
Examine the C address to determine whether to receive or transfer.
When the transfer determination circuit 250 determines that the packet is received, this packet is written in the reception FIFOs 160a and (160b). In response to this, the bus I / F circuit 450 receives the FI.
Read packets from FO 160a, (160b),
Receive descriptor 22 in memory 2 via bus 3
a, (22b).

On the other hand, when transferring, the transfer judgment circuit 25
0 writes the packet received by the MAC 300a, (300b) to the transfer FIFO 165a, (165b). In response to this, the bus I / F circuit 450 causes the transfer FI
Read packets from FO 165a, (165b),
The transfer order determination circuit 500 inquires the priority order of the packet from the combination of the IP address of the packet and the port, and the transmission FIFO 170b corresponding to the priority order,
(170a). Next, the transfer determination circuit 250
Transfers the packet having the highest priority from the transmission FIFOs 170-1 to Nb, (a) to the MAC 300b, (300a), and transfers this packet to the Ethernet 820b, (82).
0a). In the example of FIG. 22, the transfer packet I
P address = 2, port = 1, and its priority is 1
Is. Therefore, the transfer packet received by the MAC 300a is transferred to the transfer FIFO 165a, then transferred to the transmission FIFO 170-1b by the bus I / F circuit 450, and output from the MAC 300b to the Ethernet 820b.

As a result, high priority packets are transmitted and transferred, so that packets for services requiring real-timeness are preferentially transmitted, and QoS can be realized.

Further, in this method, since the CPU 1 registers the priorities in the priority judging circuit 500, the priorities can be set automatically in real time, and it is difficult for the user to allocate the priorities. No settings are required.

The number of packets that can be received and transferred by the 2-channel communication device 800 is set to the MAC 300.
When the number of packets received by a or 300b exceeds the number of packets to be received, flow control is temporarily activated to prevent the source of the packet from transmitting the packet, and the number of packets processed does not exceed the number of received packets. Can be prevented from being destroyed. In addition, without using flow control,
When packet discard occurs, packets requesting retransmission of the discarded packet are transmitted to the Ethernets 820a and 820.
Since it is output to b, extra packets are sent to Ethernet 8.
20a, 820b sent to the Ethernet 820
The efficiency of a and 820b is lowered.

On the other hand, the transfer judgment circuit 250 performs an arbitration process for selecting one of the N sending FIFOs 170-1 to N and sending it to the MACs 300a and 300b. Normally, packets with higher priority are sent first, but when packets are concentrated in a specific sending FIFO and packets with lower priority are delayed, flow control is triggered and sending FIFO overflows. , The communication efficiency of the Ethernets 820a and 820b is reduced.

Therefore, the transfer determination circuit 250 determines the transmission FI.
The usage rate of FO170-1 to FO170-N is constantly monitored, and the transfer FI
When the usage rate of the FO 130 exceeds a preset threshold (threshold for changing the priority order), the transmission FIFO that exceeds the threshold
By preferentially transmitting the packets in 170, it is possible to prevent the communication efficiency of the Ethernets 820a and 820b from decreasing. That is, the transfer determination circuit 250
Together with the bus I / F circuit 450, buffers 150a, 1
Among the packets for transmission held in 50b, the packet with the highest priority is selected according to the judgment result of the priority judgment circuit 500, and the packet corresponding to the communication target (Ethernet 820a, 820b) of the transmission destination or the transfer destination is designated. A priority packet selection means for preferentially outputting to the communication means (MAC 300a, 300b) is configured.

Further, the transfer determination circuit 250 is
0a, 300b determines whether the packet received by the CPU 1 is a packet to be processed by the CPU 1 or a transfer packet, and the packet received according to the determination result is transferred to the memory 2 or transfer F via the reception FIFO 160a, b.
Transmission FIFOs 170-1 to 170-1 through IFOs 165a and 165b
The bus I / F circuit 450 outputs CP
It is configured as a transfer control unit that outputs the packet by the processing of U1 to the transmission FIFOs 170-1 to N serving as the transmission buffer unit.

The MACs 300a and 300b constitute a communication means for transmitting / receiving a packet including an IP address and a port.

In the above embodiment, the packet transmission from the CPU 1 and the two Ethernets 820a and 820b are performed.
In arbitration with the transmission of packets between
A threshold is set for the transfer buffer usage rate, and when the buffer usage rate exceeds the threshold, the priority of the transfer buffer is set higher, so that flow control activation and transfer buffer overflow are prevented, and Ethernet is used. Communication efficiency can be improved.

Since the priority order is set according to the combination of the IP address and the port, and the packet is transmitted and transferred according to this priority order, Q
oS can be realized. Furthermore, a threshold is set for the usage rate of the sending buffer that holds the transmission and transfer packets for each priority, and when the usage rate of the buffer exceeds the threshold, the priority of the sending buffer that exceeds the threshold is increased. As a result, it is possible to prevent the flow control from being activated and the transmission buffer from overflowing, and improve the communication efficiency of the Ethernet.

The packet communication device according to the present invention is I
The invention can be applied not only to P-phones but also to IP videophones.

[0093]

As described above, according to the present invention,
When the transmission packet is transmitted prior to the transfer of the transfer packet and the usage rate of the transfer buffer means exceeds the threshold value, the priority of the transfer packet is set higher than that of the transmission packet, and the transmission packet is transmitted. Since the transfer packet is output to the designated communication means prior to the trust packet, overflow of the transfer buffer means can be prevented.

Further, according to the present invention, when a packet including an IP address and a port which is its auxiliary address is transmitted / received, the priority order of the transmitted / received packet is set to IP according to the real-time requirement of the packet. Since the determination is made according to the combination of the address and the port, the packet can be transmitted / received in accordance with the content of the service which is changing every moment, and the real-time property can be secured.

[Brief description of drawings]

FIG. 1 is a block configuration diagram of a two-channel Ethernet communication device showing a first embodiment of the present invention.

FIG. 2 is a block configuration diagram of a communication network using a two-channel Ethernet communication device according to the present invention.

FIG. 3 is a system configuration diagram when a plurality of 2-channel Ethernet communication devices are connected in series.

FIG. 4 is a system configuration diagram when a plurality of Ethernet communication devices are connected to a HUB.

FIG. 5 is a block configuration diagram of a memory.

FIG. 6 is a block configuration diagram of a bus I / F circuit, a buffer, and a transfer determination circuit.

FIG. 7 is a configuration diagram of a register.

FIG. 8 is a configuration diagram of a CAM.

FIG. 9 is a diagram for explaining selection conditions of a selector in the transfer determination circuit.

FIG. 10 is a flowchart illustrating a packet transmission process.

FIG. 11 is a flowchart for explaining packet reception / transfer processing.

FIG. 12 is a configuration diagram of a communication system when a 2-channel Ethernet communication device is applied to an IP telephone.

FIG. 13 is a block configuration diagram of a two-channel Ethernet communication device showing a second embodiment of the present invention.

FIG. 14 is a block diagram of a buffer.

FIG. 15 is a block diagram of a priority determination circuit.

FIG. 16 is an explanatory diagram of a CAM configuration.

FIG. 17 is an explanatory diagram of a register configuration.

FIG. 18 is a block configuration diagram of a bus I / F circuit.

FIG. 19 is a block configuration diagram of a transfer determination circuit.

FIG. 20 is an explanatory diagram of a register configuration.

FIG. 21 is a flowchart illustrating a packet transmission process.

FIG. 22 is a flowchart for explaining packet reception / transfer processing.

[Explanation of symbols]

1 CPU 2 memory 3 buses 4 2-channel communication module 100a, 100b buffer 110a, 110b receive FIFO 120a, 120b transmission FIFO 130a, 130b transfer FIFO 200 Transfer judgment circuit 300a, 300b Ethernet MAC 400 bus I / F circuit 810a, 810b PHY 820a, 820b Ethernet 150a, 150b buffer 250 transfer determination circuit 450 bus I / F circuit 300a, 300b Ethernet MAC 450 bus I / F circuit 500 priority determination circuit

   ─────────────────────────────────────────────────── ─── Continued front page    (72) Inventor Yasuo Watanabe             5-20-1 Kamimizuhonmachi, Kodaira-shi, Tokyo Stock             Ceremony Company within Hitachi Semiconductor Group (72) Inventor Ouchi             5-20-1 Kamimizuhonmachi, Kodaira-shi, Tokyo Stock             Ceremony Company within Hitachi Semiconductor Group (72) Inventor Yoshihiro Tanaka             5-22-1 Kamimizuhonmachi, Kodaira-shi, Tokyo Stock             Ceremony Company Hitachi Cho-LS System             Within (72) Inventor Toshiki Kanai             5-20-1 Kamimizuhonmachi, Kodaira-shi, Tokyo Stock             Ceremony Company within Hitachi Semiconductor Group F term (reference) 5K033 AA01 CB06 CB17 DB13                 5K034 AA05 DD03 FF12 HH50 MM21

Claims (14)

[Claims] 1. A plurality of communication means for transmitting and receiving packets to and from a plurality of communication targets, a packet for transmission by the plurality of communication means, and a processing of packets received by the plurality of communication means. Packet generation processing means, transfer buffer means for holding transfer packets for exchanging information between the plurality of communication targets, and reception packets received by the plurality of communication means are transfer packets. When it is determined that the received packet is present, the received packet is output to the transfer buffer means, and one of the packet generated by the packet generation processing means and the transfer packet held in the transfer buffer means is transmitted to the destination or transferred. And a transfer control unit for preferentially outputting to a designated communication unit corresponding to the previous communication target. When the usage rate of the transfer buffer means exceeds a threshold, the stage sets the priority of the transfer packet higher than that of the generated packet,
A packet communication device configured to output the transfer packet to the designated communication unit prior to the generated packet. 2. A plurality of communication means for transmitting and receiving packets to and from a plurality of communication objects, a packet for transmission by the plurality of communication means, and a processing of packets received by the plurality of communication means. Packet generation processing means, transfer buffer means for holding transfer packets for exchanging information with each other among the plurality of communication objects, and packet generation processing means for receiving packets received by the plurality of communication means. Whether the packet is a packet to be processed or the transfer packet, the received packet is output to the packet generation processing means or the transfer buffer means according to the determination result, and the packet generation processing means generates the packet. One of the packets and the transfer packet held in the transfer buffer means is a destination or And transfer control means for preferentially outputting to a designated communication means corresponding to the communication destination of the transfer destination, the transfer control means, when the usage rate of the transfer buffer means exceeds a priority change threshold, A packet communication device in which the priority of a transfer packet is set higher than that of the generated packet, and the transfer packet is output to the designated communication means in preference to the generated packet. 3. The packet communication apparatus according to claim 1, wherein the transfer control means includes a priority order register that can be set by the packet generation processing means, and the priority order register includes the transfer order register. A packet communication device, wherein a threshold value changing threshold for the usage rate of the buffer means is set. 4. Any one of claims 1, 2 and 3
In the packet communication device described in the paragraph 1, the transfer control means is for flow control to a designated communication means corresponding to a communication object of a transfer source when the usage rate of the transfer buffer means exceeds a flow control threshold value. A packet communication device that outputs a packet. 5. Any one of claims 1, 2 and 3
In the packet communication device according to the paragraph (3), there is provided a receiving buffer means for temporarily holding a received packet by the reception of the plurality of communication means, wherein the transfer control means is such that the usage rate of the receiving buffer means is a flow control threshold value. A packet communication device that outputs a flow control packet to a designated communication means corresponding to the communication target of the transmission source when the number exceeds the limit. 6. The packet communication device according to claim 4, wherein the transfer control unit includes a flow control register that can be set by the packet generation processing unit, and the flow control register includes the transfer control unit. A packet communication device, wherein a flow control threshold value relating to a usage rate of the buffer means or the reception buffer means is set. 7. A plurality of communication means for transmitting and receiving a packet including an IP address and a port which is its auxiliary address to a plurality of communication targets, and a priority order regarding real-time property of the packet of the IP address and the port. Out of the transmission packets held in the plurality of transmission buffer means, a plurality of transmission buffer means for holding transmission packets in association with the priority regarding the real-time property And a priority packet selection means for selecting the highest priority packet according to the determination result of the priority determination means and preferentially outputting it to the designated communication means corresponding to the communication object of the transmission destination or the transfer destination. Packet communication device. 8. The packet communication device according to claim 7, wherein the packet generation processing means generates a packet to be transmitted by the plurality of communication means and processes a packet received by the plurality of communication means, Transfer buffer means for holding transfer packets for exchanging information between a plurality of communication objects, and whether the received packets received by the plurality of communication means are packets to be processed by the packet generation processing means or not. It is determined whether the packet is a transfer packet, the received packet is output to the packet generation processing means or the transfer buffer means according to the determination result, and the packet generated by the packet generation processing means is transmitted to the transmission buffer means. And a transfer control means for outputting to A packet communication device, characterized in that the transfer packet held in (1) is output to a designated transmission buffer means according to its priority. 9. The packet communication device according to claim 7, wherein the priority packet selection means is configured to operate when the usage rate of any one of the plurality of transmission buffer means exceeds a threshold value. A packet communication device, wherein the packet held in the transmission buffer means is output to the designated communication means in preference to other packets. 10. The packet communication device according to claim 9, wherein the priority packet selection means includes a register that can be set by the packet generation processing means, and the register has a threshold value relating to a usage rate of the transfer buffer means. A packet communication device, characterized in that 11. A plurality of packet communication devices for transmitting and receiving a packet including an IP address and a port which is an auxiliary address thereof, and a priority order regarding real-time property of packets transmitted and received between the plurality of packet communication devices. A packet communication system comprising: a priority control unit that determines a combination of an IP address and the port; and the plurality of packet communication devices are connected in series. 12. The packet communication system according to claim 11, wherein the plurality of packet communication devices comprises the packet communication device according to any one of claims 7, 8, 9, and 10. A packet communication system characterized by the above. 13. A plurality of communication means for transmitting and receiving packets to and from a plurality of communication objects, and a transfer buffer means for holding transfer packets for exchanging information between the plurality of communication objects. When the received packet received by the plurality of communication units is the transfer packet, the received packet is output to the transfer buffer unit, and the transmission packet and the transfer packet held in the transfer buffer unit are output. A transfer control unit that preferentially outputs one of the packets to a designated communication unit corresponding to the communication target of the transmission destination or the transfer destination, wherein the transfer control unit is configured to reduce the usage rate of the transfer buffer unit. When the threshold value is exceeded, the priority of the transfer packet is set higher than that of the transmission packet, and the priority is given to the transmission packet. A packet communication module which outputs the transfer packet to the designated communication means. 14. The packet communication module according to claim 13, wherein the transfer control means includes a priority order register that can be set by the packet generation processing means, and the priority order register includes the transfer buffer means. A packet communication module, wherein a threshold for changing the priority order regarding the usage rate of the packet communication module is set.