JP2003158179A - Semiconductor device and its fabricating method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To make a highly reliable isolation trench having a flat surface. SOLUTION: The semiconductor device comprises an isolation region formed of a first trench made in a specified region on the surface of a semiconductor substrate and an insulation film filling the first trench and isolating the semiconductor substrate into a plurality of element regions, and an alignment mark consisting of an empty second trench exposed to the surface of the substrate wherein the surface level of the insulation film in the isolation region projects from the surface of the semiconductor substrate in the vicinity of the alignment mark.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly to formation of a trench including formation of an alignment mark.

[0002]

2. Description of the Related Art In recent years, as semiconductor devices have become finer and more highly integrated, a technique for processing subquarter micron with high accuracy and reproducibility is required. Especially, in forming a multi-layer or three-dimensional element including element isolation, formation of a highly precise and fine trench has become an extremely important issue.

In recent years, with the high integration of semiconductor devices, ST
An element isolation method using a fine trench, which is called an I (Shallow Trench Isolation) element isolation method, is drawing attention. When element isolation is performed using this STI element isolation method, it often involves a step of forming an alignment mark by a trench used in a subsequent element formation process. In order to facilitate detection in the subsequent mask alignment process, this alignment mark needs to be used in a state where it is left as a recess without being filled with silicon oxide.

Therefore, conventionally, an alignment mark is formed by forming the alignment mark in the same step as forming the trench, filling the trench with an insulating film, and then removing the buried insulating film only in the alignment mark region. Was going on.

That is, first, as shown in FIG.
A silicon nitride film 2 is formed on the surface of a silicon substrate 1, and a resist pattern 3 for forming trenches is formed on the silicon nitride film 2 by photolithography.

Subsequently, the silicon nitride film 2 is patterned using the resist pattern 3 as a mask, and the surface of the silicon substrate 1 is etched by RIE using the resist pattern 3 and the silicon nitride film 2 as masks.
The trench 4 having a desired depth is formed.

After removing the resist pattern 3,
A silicon oxide film 5 is formed by the CVD method, and CMP (Ch
The surface is flattened by an emical mechanical etching method to form a trench filled with the silicon oxide film 5 as shown in FIG.

Further, as shown in FIG. 3C, a resist is applied to the surface of the silicon nitride film 2 to form a second resist pattern 6 having an opening only around the trench in the region serving as an alignment mark.

Then, wet etching or RIE is performed.
Is used to etch the silicon oxide film to remove the silicon oxide film inside the trench by etching. Then, the resist pattern 6 is removed, and as shown in FIG. 3D, an alignment mark 7 composed of a trench is formed.

In the semiconductor substrate having the alignment mark thus formed, as is apparent from FIG. 3D, the silicon oxide film 5 is raised on the surface of the trench 4 for element isolation, and a step is formed on the surface. Is formed. Here, a step corresponding to the film thickness of the silicon nitride film is formed, and the step is about 200 nm. For this reason, the focus margin in the lithography process becomes small, which has been a serious problem that prevents highly accurate pattern formation.

[0011]

As described above, in the conventional element isolation method, a step is formed on the surface for forming the alignment mark, which is a big problem to prevent miniaturization.

The present invention has been made in view of the above circumstances, and an object thereof is to form a highly reliable element isolation trench having a flat surface.

[0013]

Therefore, in the first aspect of the present invention, a plurality of semiconductor substrates are formed by a trench formed in a predetermined region on the surface of the semiconductor substrate and an insulating film filled in the trench. The device isolation region is divided into the device regions of the above, and the surface level of the insulating film in the device isolation region is configured not to protrude beyond the surface of the semiconductor substrate.

According to this structure, the surface of the substrate can be flattened. Therefore, even when the number of layers is increased, the focus margin in the lithography process can be improved, and a highly reliable semiconductor device can be obtained.

According to a second aspect of the present invention, the semiconductor substrate is formed of a plurality of elements by a first trench formed in a predetermined region on the surface of the semiconductor substrate and an insulating film filled in the first trench. An element isolation region that is separated into regions, and an alignment mark formed of an empty second trench exposed on the surface of the substrate, wherein the element isolation region is at least
It is characterized in that the surface level of the insulating film in the element isolation region does not protrude beyond the surface of the semiconductor substrate in the vicinity of the alignment mark.

According to this structure, the surface of the substrate around the alignment mark can be flattened, the focus margin in the lithography process can be improved, and a highly reliable semiconductor device can be obtained. Becomes

Preferably, the semiconductor substrate is a silicon substrate, and a silicon oxide film is formed on an inner wall of the trench to form an element isolation region.

According to this structure, it is possible to obtain a highly reliable structure such as a MOS device.

According to the method of the present invention, the step of forming the trench on the surface of the semiconductor substrate includes the step of forming a first etching-resistant mask having an opening in the trench formation region on the surface of the semiconductor substrate, and the opening. A step of forming a second mask so as to cover a region in which an alignment mark is to be formed, and the semiconductor substrate is etched using the first and second masks as masks to form trenches for element isolation. The first etching step, and the second step
Removing the mask, exposing the opening of the alignment mark formation region, filling an insulating film in the element isolation trench, until the semiconductor substrate surface of the alignment mark formation region is exposed, An etch-back step of etching the insulating film, and etching the surface of the semiconductor substrate in the alignment mark forming region under an etching condition having etching selectivity with respect to the insulating film to form an alignment mark trench. And the step of removing the first mask.

According to this structure, only the element isolation trench is formed in the first etching process for forming the trench, and the alignment mark trench is formed after filling the element isolation trench with the insulating film. Since the etching is performed on the semiconductor device, a flat surface can be obtained without rising of the insulating film in the element isolation trench around the alignment mark trench, and a highly reliable and highly reliable semiconductor device can be obtained. Can be easily formed.

Preferably, the semiconductor substrate is a silicon substrate, and the step of forming the first mask includes a step of forming a silicon nitride film and a step of patterning the silicon nitride film by photolithography. Is characterized by.

Preferably, the step of forming the insulating film is CV.
It is characterized in that it is a step of forming a silicon oxide film by the D method.

Preferably, the etch-back step is C
It is characterized by being an MP process.

Preferably, the second etching step is a wet etching step.

[0025]

BEST MODE FOR CARRYING OUT THE INVENTION Next, a first embodiment of the present invention will be described in detail with reference to the drawings. in this way,
In the first etching step for forming the trench, only the element isolation trench is formed, the element isolation trench is filled with an insulating film, and then etching for forming the alignment mark trench is performed. The insulating film does not rise in the element isolation trench around the mark trench to obtain a flat surface.

First, as shown in FIG. 1A, a 170 nm thick silicon nitride film 2 (Si) is formed on the surface of a silicon substrate 1.
₃ N ₄ ) is formed, and a resist pattern 3 is formed on this upper layer by photolithography and patterned.

Then, etching is performed using the resist pattern 3 as a mask to form a first mask 2 made of a silicon nitride film having an opening H in the trench formation region as shown in FIG. 1B.

Further, a silicon nitride film is formed and patterned by photolithography, and a third mask 8 is formed so as to cover the opening edge of the alignment mark forming region in the opening H, and this mask 2 is used. Then, as shown in FIG. 1C, plasma etching is performed to form trenches 4 for element isolation.

As an apparatus for this etching, for example, an inductively coupled plasma etching apparatus is used, the silicon substrate 1 is placed on a polyimide electrostatic chuck, and three-step etching is performed under the following conditions.

Step 1: Pressure = 15 mTorr, Source power: 1200 W, Bias power: 100 W, H
Etching is performed for 5 seconds using a mixed gas of Br / CF ₄ = 80/80 sccm.

Step 2: Pressure = 15 mTorr, Source power: 1000 W, Bias power: 150 W, C
Using a mixed gas of l ₂ / N ₂ = 125/50 sccm,
Etch for 15 seconds.

Step 3: Pressure = 40 mTorr, Source power: 1500 W, Bias power: 180 W, H
Etching is performed for 50 seconds using a mixed gas of Br / Cl ₂ / O ₂ = 160/20/5 sccm.

By performing the three-step etching in this way, it becomes possible to obtain a gentle trench having a steep taper surface in a region where the opening is gentle and deep.

Here, in the etching process of step 1,
The pressure is preferably set to 30 mTorr or less in order to prevent the generation of residue. Further, it is desirable that the source power is 1500 W or less and the bias power is 300 W or less in order to suppress the amount of mask film reduction.

Further, the flow rate ratio of HBr / CF ₄ is 120: 4.
It is considered to be usable in the range of 0 to 40: 120 sccm. However, when the CF ₄ ratio is high, the amount of mask film loss is large.

The etching gas and flow rate ratio are
It may be selected so that a desired taper angle can be obtained.

Next, regarding the second etching step, the reaction product is not limited to the mixed gas of Cl ₂ and N ₂ and is reacted with the halide of silicon to form a reaction product which is deposited on the substrate surface. It is desirable to select a gas composition that can be used.

As a combination of this gas, HBr +
N ₂ , HBr + Cl ₂ + O ₂ , HBr + Br ₂ + O ₂ , Cl ₂
+ O ₂ + N ₂ , HCl + N ₂ , HCl ₂ + Cl ₂ + N _{2 and the} like can be selected.

In the third etching step, Cl ₂ , HCl, Br ₂ , HBr, HI or the like can be selected as the gas.

The taper angle of the trench thus obtained was from 48.2 degrees to 59.0 degrees, and the values as designed were obtained without variation. Variation is at most 1
The angle was 1.8 degrees, the taper angle of the trench formed by the conventional method was 45.7 degrees to 68.0 degrees, and the variation was 22.3 degrees.

Subsequently, as shown in FIG. 1D, the third mask 8 is peeled and removed, a silicon oxide film is formed by a CVD method, and a silicon oxide film 5 is formed inside the trench 4. At this time, a silicon oxide film is also formed in the alignment mark formation region after removing the third mask 8.

Subsequently, as shown in FIG. 1D, CMP is performed until the silicon oxide film 5 is removed and the substrate surface 1 in the alignment mark forming region is exposed.

Then, similarly, silicon is etched using an inductively coupled plasma etching apparatus to form the alignment mark trench 7 in the alignment mark forming region as shown in FIG. 1 (e).

Finally, the silicon nitride film 2 is removed, and
As shown in (f), an element isolation wafer having a flat surface can be formed.

The element-isolated wafer thus formed can have a flat surface without rising of the insulating film in the element-isolation trench around the alignment mark trench, and can improve the focus margin. In addition, it is possible to easily form a highly reliable semiconductor device with high lithography accuracy. A fine and highly reliable trench can be formed, an area required for element isolation is small, and an element can be miniaturized.

Although the silicon nitride film is used as a mask in the above embodiment, other materials may be used. The third mask that covers the opening of the alignment mark formation region is not limited to silicon nitride, and a resist or the like may be used as long as it has etching resistance to the etching conditions of silicon.

Further, needless to say, the present invention can be applied not only to those having an alignment mark, but also to general element isolation structures using trenches.

The trench 5 is required to have a gentle shape having a steep taper surface in a region where the opening is gentle and deep in view of reduction of strain in SIT and pattern accuracy formed in the upper layer. Therefore, in the first embodiment, the trench is formed by three etching steps. However, the trench for the alignment mark may be formed so as to have a sharp edge and have a depth required for alignment.

Therefore, as a second embodiment of the present invention,
An example will be described in which the trench for the alignment mark has a smaller opening area than the other trenches and has a sharper edge and a shallow shape.

2 (a) to 2 (f) show the manufacturing process. Also in this method, as in the first embodiment, only the element isolation trench is formed in the first etching step for forming the trench, and the element isolation trench is filled with the insulating film, and then the alignment mark trench 7 is formed. Etching is performed to form a flat surface with no swelling of the insulating film in the element isolation trench around the alignment mark trench 7.

The difference from the first embodiment is that the resist pattern 3 formed in the upper layer of the silicon nitride film 2 on the surface of the silicon substrate 1 is used for alignment marks as shown in FIGS. 2 (a) and 2 (b). The opening H is made smaller at a portion, and the etching step of the alignment mark trench 7 is performed by a dry etching step having high anisotropy as shown in FIG.

Other steps were the same as those in the first embodiment. According to such a configuration, it is possible to form the alignment mark trench 7S capable of detecting the position sharply and accurately without depending on the trench profile of the SIT.

Also, the depth of the alignment mark trench can be set without depending on the SIT trench depth. Here, it is formed to be shallower than the SIT trench depth, but it may be formed to be approximately the same as the SIT trench depth or deeper than the SIT trench depth.

Furthermore, although the SIT trench has been described in the above embodiment, when forming a trench capacitor or forming a semiconductor device using the inner wall of the trench as a contact region, a transistor having the inner wall of the trench as a channel region is used. Although the shape of the trench is different depending on the case, such as in the case of forming, in the above-described embodiment, the alignment mark having a desired profile can be formed without depending on this, and the substrate surface also has good flatness. It becomes possible to obtain.

[0055]

As described above, according to the present invention, since the surface level of the insulating film filled in the element isolation region does not protrude beyond the semiconductor substrate surface, the substrate surface It is possible to achieve planarization, and it is possible to improve the focus margin in the lithography process even when forming multiple layers, and it is possible to obtain a highly reliable semiconductor device.

[Brief description of drawings]

FIG. 1 is a diagram showing a step of forming a trench according to a first embodiment of the present invention.

FIG. 2 is a diagram showing a step of forming a trench according to a second embodiment of the present invention.

FIG. 3 is a diagram showing a conventional trench forming process.

[Explanation of symbols]

1 Silicon substrate 2 Silicon nitride film (first mask) 3 resist pattern 4 trench 5 Silicon oxide film 6 resist pattern 7 Alignment mark trench 8 third mask

Claims (8)

[Claims] 1. A device isolation region, which is formed by a trench formed in a predetermined region of a semiconductor substrate surface and an insulating film filled in the trench, and which divides the semiconductor substrate into a plurality of device regions, A semiconductor device, wherein a surface level of the insulating film in the element isolation region is configured so as not to protrude beyond the surface of the semiconductor substrate. 2. A semiconductor substrate is divided into a plurality of element regions by a first trench formed in a predetermined region on the surface of the semiconductor substrate and an insulating film filled in the first trench. An element isolation region, and an alignment mark formed of a second trench exposed on the substrate surface in an empty state, wherein the element isolation region is at least near the alignment mark and is formed of the insulating film in the element isolation region. A semiconductor device, characterized in that the surface level thereof is configured so as not to protrude beyond the surface of the semiconductor substrate. 3. The semiconductor substrate is a silicon substrate,
The semiconductor device according to claim 2, wherein a silicon oxide film is formed on an inner wall of the trench to form an element isolation region. 4. The step of forming a trench on the surface of a semiconductor substrate includes the step of forming a first etching-resistant mask having an opening in a trench formation region on the surface of the semiconductor substrate, and forming an alignment mark among the openings. A step of forming a second mask so as to cover the desired region, and a first etching step of etching the semiconductor substrate using the first and second masks as masks to form trenches for element isolation. Removing the second mask to expose the opening in the alignment mark formation region, filling an insulating film in the element isolation trench, and exposing the semiconductor substrate surface in the alignment mark formation region Until an etching-back step of etching the insulating film is performed, and an etch-selection process having etching selectivity with respect to the insulating film is performed. A semiconductor comprising: a second etching step of etching the surface of the semiconductor substrate in the alignment mark forming region to form an alignment mark trench under etching conditions; and a step of removing the first mask. Device manufacturing method. 5. The semiconductor substrate is a silicon substrate,
The method of manufacturing a semiconductor device according to claim 4, wherein the step of forming the first mask includes a step of forming a silicon nitride film and a step of patterning the silicon nitride film by photolithography. . 6. The method of manufacturing a semiconductor device according to claim 5, wherein the step of forming the insulating film is a step of forming a silicon oxide film by a CVD method. 7. The method of manufacturing a semiconductor device according to claim 4, wherein the etch back step is a CMP step. 8. The method according to claim 4, wherein the second etching step is a wet etching step.
A method for manufacturing a semiconductor device according to any one of 1.