JP2003157097A - Coded voice decoder - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an inexpensive and high-performance coded voice decoder by a frequency time area conversion circuit carrying out an efficient arithmetic operation, of which hardware cost is reduced. SOLUTION: The coded voice decoder is provided with an MPU interface, a first memory, a first memory interface, a second memory, a second memory interface, a product sum computing element and an arithmetic control circuit. Frequency sample data transferred from an MPU and temporary arithmetic data utilized in the middle of the arithmetic operation by the product sum computing element are stored in the first memory. Coefficient data utilized in the middle of the arithmetic operation by the product sum computing element and decoded voice and audio data are stored in the second memory.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a coded audio signal decoding apparatus for decoding a digital audio signal whose data has been compressed by high-efficiency encoding and outputting the digital audio signal.

[0002]

2. Description of the Related Art In recent years, various broadcasting media such as satellite broadcasting and cable television, communication networks represented by the Internet, portable audio players and DVDs.
When dealing with a voice signal having a large amount of information in a storage medium such as the above, a method of compressing the information amount by encoding a digitized voice signal is generally used.

As a voice signal encoding system, ISO /
MPEG Au standardized by IEC11172-3
A method called “dio” or ISO / IECIS13813
An encoding method called MPEGAAC standardized by -7 is known. These audio signal coding systems are
This is a method of converting a digital audio signal into frequency domain samples (hereinafter abbreviated as frequency samples), reducing the amount of information by prediction and difference processing, and then normalizing, quantizing and encoding.

In the MPEGAAC system, a decoding process is handled for each unit called an audio frame, and an audio signal for 1024 samples is encoded in one audio frame. The decoding process in MPEGAAC is shown in FIG.
Shown in. The procedure of the decoding process can be roughly divided into two blocks as described below.

(1) A frequency data operation unit for inputting encoded data (bit stream), performing variable length decoding processing, performing inverse quantization of a spectrum signal and inverse normalization using a scale factor, (2) ) An arithmetic unit that performs frequency-time domain conversion (hereinafter abbreviated as fT conversion) by performing inverse cosine conversion and window processing on the frequency samples.

By the above (1) and (2), the decoding process of the coded stream can be performed to obtain a digital audio signal. Since the audio decoder for performing the voice decoding process described above requires a complicated decoding process, a dedicated LSI is often used. On the other hand, a dedicated LSI for voice decoding
Since the scale is large and expensive, in addition to system decoding and system control processing, the frequency sample calculation is performed by an inexpensive general-purpose MPU, and only f-T conversion is performed by repeating the multiply-accumulate operation of coefficient data and operation data. A device has been devised that performs the operation with a small dedicated circuit.
(JP-A-10-11092)

[0007]

DISCLOSURE OF THE INVENTION Problems to be Solved by the Invention
A coded audio signal decoding device disclosed in Japanese Patent Laid-Open No. 11092 distributes a coded image / audio multiplex stream input from 201 into a coded stream of an image and a coded stream of an audio by a distribution device 202. The image elementary is decoded by the video decoder 203 to obtain the digital image output 204. One audio encoded stream is decoded by the MPU 210, the FIFO controller 205, the memory 206, and the FT conversion circuit 207 to obtain a digital audio output 208.

[0008] The MPU 210 performs a frequency sample calculation operation of the encoded audio stream and stores the result in the memory 206 in frame units. Here, it is the FIFO controller 205 that monitors the free state of the memory.
Is. The f-T conversion circuit 207 reads the frequency sample data of one frame stored in the memory 207 and performs the f-T conversion calculation.

The inventors of the present application have previously studied the hardware configuration of the fT converter which employs the audio decoding processing method in the above-described coded signal decoding apparatus as shown in FIG. In this hardware configuration, MPU
The frequency sample data calculated in step 4 is input to the FIFOA 401. The arithmetic unit 402 reads the arithmetic data stored in the FIFOA 401, and the local memory 404
Calculate using. At this time, the coefficient data is also read from the local memory 404. The data being calculated is temporarily stored in the local memory 404. Further, the arithmetic data and the coefficient data are read from the local memory 404, arithmetic processing is performed, and the arithmetic data is stored in the local memory 404. The speech decoded signal which is the final result of repeating this series of processes is output to the FIFOB 403.

In the above-mentioned configuration, the input / output memories, the FIFOA 401 and the FIFOB 403, can be composed of a single port memory or a dual port memory. Consider data transfer when the FIFOA 401 is configured by a single port memory. In the method of decoding the coded audio signal, the MPU performs a frequency sample calculation operation, and transfers the calculated frequency sample data to the input memory configured by hardware on a frame-by-frame basis.

Considering the transfer from the MPU to the input FIFO memory at this time, the access timing is shown in FIG. That is, from MPU to input memory (a + b) * n
Data is transferred by applying a clock, and decoding is performed by the next d clock. Here, of the time (a + b) clocks required for the MPU to transfer one word of frequency sample data, a clock is an access clock of the input memory and b clock is a period for absorbing synchronization with the MPU bus.
Further, n is the number of frequency sample data in one frame and is 1024 in the AAC method. In this way, for the data transfer from the MPU, the operating clock of the MPU bus and the input F
The waste clock generated because the operation clock of the IFOA memory is asynchronous requires (b * n) clocks.

In order to avoid such a wasteful clock, a method of performing a decoding process by shifting the frame transferred from the MPU and the frame to be decoded can be considered. At this time, one frame decoding period is d clocks. However, this requires having a plurality of frames of memory to be used as the input FIFO, which increases the hardware cost.
Further, although the useless clock can be avoided by using the input FIFO as the dual port memory, the hardware cost similarly increases. This waste clock is output F
The same applies to transfers from the IFO.

Next, the problems concerning the local memory for storing the operation data and the coefficient data will be examined as follows. Consider the basic processing of the f-T conversion operation. f-T
The calculation process in the conversion is configured by repeating the sum of products calculation of the coefficient data (W) of the following formula (z0 = x + y * W) or (z1 = x−y * W) and the calculation data (x, y). There is a feature that Therefore, when the coefficient data and the operation data cannot be read at the same time, a plurality of clocks are required to read the data required for integration, which causes a decrease in operation efficiency. This problem can also be improved by having a dual port memory, but the hardware cost increases like the above-mentioned problem.

As described above, the configurations examined previously are as follows:
There is a problem that a wasteful clock is generated in the arithmetic processing when data is transferred between the outside of the circuit and the input / output memory, and a problem that the circuit scale remarkably increases if the number of memories or the number of ports for data transfer is increased to eliminate the wasteful clock. is there. Therefore, in the present inventors, the input / output FIF
O, by devising the configuration of the arithmetic memory, it is possible to suppress an increase in hardware cost, improve the efficiency of accessing arithmetic data, and perform arithmetic processing at high speed.
I thought to minimize the useless clock when transferring data to and from.

An object of the present invention is to provide a coded speech decoding device having a small circuit scale. Another object of the present invention is to provide a coded speech decoding apparatus which has a high access efficiency of operation data and can perform operation processing at high speed. The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0016]

The outline of a typical one of the inventions disclosed in the present application will be briefly described as follows. An MPU interface as a frequency-time domain conversion circuit that performs frequency sample calculation calculation in decoding processing for decoding encoded voice and audio signals and decodes frequency sample data from the MPU to obtain voice and audio signals. , A first memory, a first memory interface, a second memory, a second memory interface, a product-sum calculator and a calculation control circuit, and the frequency sample data and the product-sum calculator transferred from the MPU are The first memory stores temporary calculation data used during calculation, and the second memory stores coefficient data and decoded voice and audio data used by the product-sum calculation unit during calculation.

[0017]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows a block diagram of an embodiment of a coded speech decoding apparatus according to the present invention. In the figure, 101 is an input interface and 102 is M.
PU, 103 is ROM, 104 is RAM, 105 is a data bus, and 106 is a D / A converter.

Reference numeral 110 collectively constitutes an fT conversion circuit. 111 is an MPU interface, 112 is a product-sum calculator, 113 is a memory interface A, 114 is a memory A, 115 is a control circuit, 116 is a memory B, 117 is a memory interface B, and 118 is a D / A interface.

The coded voice decoding device of this embodiment decodes an input signal obtained by encoding a digital voice signal based on the MPEGAAC standard, and outputs an analog voice signal. M
The PU 102 receives the encoded digital audio signal from the input interface 101, and the ROM 103 and the RAM 104
Is used to control the system and perform frequency data calculation in the audio signal decoding process to derive frequency sample data.

The f-T conversion circuit 110 is the general-purpose MPU.
The frequency samples output from 102 are subjected to inverse cosine transform, and window processing is performed to calculate and output digital voice. In the f-T conversion circuit 110, the memory A 114 stores frequency sample input data and operation data. The memory B116 stores output voice data and coefficient data.

Further, the memory interface A113 monitors the storage status of the memory A114, and outputs a writable signal when the number of stored frames is less than the maximum number, and outputs a readable signal when the number of stored frames is one or more. Similarly, the memory interface B117 outputs a write signal and a read signal for the memory B116.

A procedure for inverse cosine transforming frequency samples in the fT conversion circuit 110, performing window processing to calculate and output digital voice will be described below. If a frame writable signal for the memory A 114 is output from the memory interface A 113, the MPU 102
Writes frequency samples into the memory A 114 frame by frame. Further, if the frame read enable signal is output from the memory interface A113 and the frame write enable signal of the memory B116 is output from the memory interface B117, the control circuit 11
5 outputs a calculation start signal to the product-sum calculation unit 112.

When the signal for starting the calculation is received, the product-sum calculator 11
2 calculates the address of the necessary operation data and outputs the address together with the read signal to the memory interface A113. At the same time, the product-sum calculator 112 calculates the address of the necessary coefficient data, and the memory interface B11
The address is output together with the read signal to 7.

Upon receiving the read signal and the address, the memory interface A113 transfers the operation data to the memory A114.
And outputs to the product-sum calculator 112. At the same time, the memory interface B117 stores the coefficient data in the memory B1.
16 and outputs to the product-sum calculator 112. Simultaneous reading from the memory A 114 and the memory B 116 enables high-speed product-sum calculation.

The product-sum calculation unit 112 performs a product-sum calculation on the received calculation data and coefficient data, and outputs the calculation result data to the memory interface A113 together with the write signal and the address calculated by the product-sum calculation unit 112.

The operation data is the memory interface A11.
3 is repeatedly read from the memory A 114 to the product-sum calculator 112, and at the same time, the memory interface B 11 is read.
The coefficient data read from the memory B 116 through 7 is subjected to a product-sum operation by the product-sum operation unit 112 to implement the inverse cosine transform and window processing.

The temporary result during the calculation is repeatedly stored in the memory A114 through the memory interface A113. After the arithmetic processing is completed up to the final result, the arithmetic data decoded into digital audio is stored in the memory B116 through the memory interface B117. The digital audio decoded data stored in the memory B116 is serially transferred to the D / A converter 106 through the D / A interface 118.

As described above, the memory A 114 has the MP
The frequency sample from U102 is the unit of speech decoding 1
Each of the frames serves as an input buffer memory for storing a plurality of frames and a calculation buffer memory for storing temporary data during f-T calculation processing, and the memory B116 outputs the results output from the f-T calculation circuit 110 for a plurality of frames. The output buffer memory for storing and the coefficient buffer memory for storing coefficient data also serve as input / output FI.
By reducing the memory required for FO and accessing the operation data and the coefficient data at the same time, the product-sum operation unit can operate efficiently.

Next, a method for avoiding a wasteful clock generated when data is transferred from the MPU 102 to the fT conversion circuit 110 will be described below. From MPU 102 to f
The frequency sample data is transferred to the −T arithmetic circuit 110 preferentially to arithmetic processing. In FIG. 6, the control circuit 115 outputs an operation stop signal to the product-sum operation unit 112 during the memory access period a clock. In the synchronous processing period b clock, the sum-of-products calculator 1 does not output the calculation stop signal.
Processing is performed at 12.

One frame decoding period performed by this is (a * n + d) clocks, and the wasteful clock (b * n) shown in FIG. 5 can be reduced. This method is performed by the D / A converter 1 from the memory B 116 through the D / A interface 118.
The same can be applied to the case of transfer to 06, and the wasteful clock (b * n) can be reduced.

As described above, the MPU performs the process of deriving a frequency sample in the audio signal decoding process and the system control. The f-T conversion circuit performs inverse cosine conversion on the frequency samples output from the MPU and performs window processing to calculate digital voice. Above MPU
The interface transfers the frequency samples derived from the general-purpose MPU to the fT conversion circuit. The control circuit outputs a calculation stop signal that enables the frequency samples derived from the general-purpose MPU to be transferred to the f-T conversion circuit and the f-T calculation process at the same time, and controls the calculation unit. With function. The arithmetic unit realizes the fT arithmetic processing by repeating the sum-of-products arithmetic operation of coefficient data and arithmetic data, and also calculates a data address and outputs a data read signal and a write signal.

The memory A includes an input buffer memory that stores frequency samples from the general-purpose MPU for each frame, which is a unit of voice decoding, for a plurality of frames, and an operation buffer memory that stores temporary data during f-T operation processing. Also serve. The memory interface A monitors the stored data status of the memory A, outputs a frequency sample data writable signal from the MPU, outputs a readable signal if the number of stored frames is 1 or more, and further performs the above calculation. Controls the reading and writing of data to and from the container. Memory B above
Serves as both an output buffer memory for storing the results output from the f-T arithmetic circuit for a plurality of frames and a coefficient buffer memory for storing coefficient data. The memory interface B monitors the status of the data stored in the memory B, outputs the audio decoded data writable signal from the arithmetic unit, and if the number of stored frames is 1 or more, the audio digital signal frame readable signal To control the reading and writing of data to and from the arithmetic unit. further,
The MPU preferentially transfers the frequency sample data when the writable signal is output.

[0033]

As described above, the input data FIF
O and operation data local memory integrated, output data FI
By integrating the FO and the coefficient data local memory, and further by providing the control circuit for controlling the input / output and the operation, the f-T of the encoding / speech decoding device has a single-port memory having a small circuit scale. With respect to the conversion unit, it is possible to realize efficient data transfer with the MPU and high-speed processing by high-speed arithmetic data processing, and to provide hardware for realizing a coded speech decoding apparatus having a small circuit scale. it can.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a coded speech decoding device according to the present invention.

FIG. 2 is a block diagram showing an example of a conventional technique.

FIG. 3 is a flowchart diagram for explaining a decoding process in MPEGAAC.

FIG. 4 is a configuration diagram of an arithmetic unit examined prior to the present invention.

5 is an MPU access timing diagram of FIG.

FIG. 6 is an MPU access timing chart of an embodiment of the encoded voice decoding device according to the present invention.

[Explanation of symbols]

101 ... Input Interface, 102 ... MPU, 103
... ROM, 104 ... RAM, 105 ... Data bus, 10
6 ... D / A converter, 110 ... FT conversion circuit, 111 ...
MPU interface, 112 ... Sum of products operator, 113 ...
Memory interface A, 114 ... Memory A, 115 ...
Control circuit, 116 ... Memory B, 117 ... Memory interface B, 118 ... D / A interface, 201 ... Transport stream input terminal, 202 ... Distribution device, 203 ... Video decoder, 204 ... Digital image signal output terminal, 205 ... FIFO controller, 206 ...
FIFO memory, 207 ... FT conversion circuit, 208 ... Digital audio output, 209 ... Data bus, 210 ... MP
U, 211 ... System control process, 401 ... FIFO
A, 402 ... Arithmetic unit, 403 ... FIFOB, 404 ... Local memory.

   ─────────────────────────────────────────────────── ─── Continued front page    (72) Inventor Takashi Nakamoto             5-20-1 Kamimizuhonmachi, Kodaira-shi, Tokyo Stock             Ceremony Company within Hitachi Semiconductor Group F-term (reference) 5D045 DA11 DB00 DB03                 5K041 AA08 CC01 EE31 FF36 HH09                       HH41 JJ24 JJ31 JJ38

Claims (3)

[Claims] 1. An MPU that performs a frequency sample calculation operation in a decoding process for decoding encoded voice and audio signals, and a voice that decodes frequency sample data from the MPU.
A frequency time domain conversion circuit for obtaining an audio signal, wherein the frequency time domain conversion circuit comprises an MPU interface, a first memory, a first memory interface, a second memory, a second memory interface, a sum of products operator A first memory for storing frequency sample data transferred from the MPU and temporary calculation data used by the product-sum calculator in the middle of calculation, and the product-sum calculator in the middle of calculation. A coded speech decoding device characterized in that coefficient data and decoded speech and audio data to be used in step 2 are stored in a second memory. 2. The coded speech decoding apparatus according to claim 1, wherein the operation of the product-sum calculator is stopped when the MPU accesses the first memory. 3. The coded speech decoding apparatus according to claim 1, wherein the operation of the product-sum calculator is stopped when the speech / audio output interface accesses the second memory.