JP2003153168A - Stream processor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve the degree of freedom to a configuration. SOLUTION: A system is provided with a digital TV receiver 100, an AVHDD 112 and a digital VTR 113. The digital TV receiver 100 includes a stream processor 101, a memory 106, a CPU 107, an AV decoder 108 and a hard disk device 109. the stream processor 101 includes tuners 110 and 111, a switch matrix 102, an IEEE 1394 interface 103, a demultiplexer 104 and a HDD interface 105. The system can simultaneously and parallelly process a plurality of streams and also can directly output an inputted stream. Also, a system configuration can be freely changed in accordance with the setting of a switch within the switch matrix 102.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a stream processing device that handles a plurality of streams.

[0002]

2. Description of the Related Art In recent years, video / audio / data has been increasingly broadcast / transmitted / stored as digital data. For example, digital TV broadcasting, DVD, digital VT
In R, digital video cameras, IEEE 1394, etc., video signals, audio signals, data of data broadcasting, EPG, etc. are collectively broadcast, transmitted, processed, and accumulated as a stream. The data formats of these streams are diverse. For example, digital TV broadcasting and digital V
In TR, a transport stream defined in the MPEG system standard is used. In DVD,
A program stream defined in the MPEG system standard is used. When transmitting the recorded data of the digital video camera on the IEEE1394 bus, D
V format is used. Then, a unique process is required for each of these data formats.

Under such circumstances, some digital AV devices have not only a single function but also a plurality of functions. For example, in a digital TV receiver equipped with an IEEE 1394 interface, "Receive and display broadcast program", "Receive broadcast program, I
It is possible to "record on an external storage device connected via the IEEE1394 bus" and "play and display a program from an external storage device connected via the IEEE1394 bus". The stream input to this digital TV receiver is the "stream of the program being broadcast."
And "a stream of a program reproduced from an external storage device connected via the IEEE 1394 bus", and an output stream is "a program recorded in an external storage device connected via the IEEE 1394 bus." Stream. In this way, a plurality of streams are input / output.

[0004]

The digital TV receiver is provided with a transport decoder as an LSI for processing a stream. Further, a stream input / output interface LS that supplies a stream input from the outside to a transport decoder and outputs a stream processed by the transport decoder to the outside.
I (for example, IEEE 1394 interface LSI)
Is provided as an LSI separate from the transport decoder. The connection between these LSIs on the printed board is optimized according to the application system. However, it is impossible to assume all future usages, and the future application range is limited by the assumptions made during system design.

Recently, with the progress of LSI integration, it has become possible to mount a transport decoder and a stream input / output interface in one LSI. For this reason, LSI will continue to be used in the future.
It has become necessary to assume the application range of SI and the function realized in a system using an LSI when designing the LSI.

On the other hand, with the progress of digitization of video / audio and networkization, the types of stream input / output interfaces are increasing and the number of streams that must be processed simultaneously is also increasing. Also, the processing contents of the stream have been diversified.

An object of the present invention is to provide a stream processing device capable of improving the degree of freedom in the configuration of a device having a function of processing a plurality of streams.

[0008]

A stream processing apparatus according to the present invention comprises a selection means and first to fifth processing means. The selecting means associates the plurality of inputs with the plurality of outputs according to the control from the outside, and provides the stream provided to each of the plurality of inputs to the corresponding output. The first processing means provides a first stream to a first input of the plurality of inputs. The second processing means provides the second stream to the second input of the plurality of inputs. The third processing means receives the stream from the first output of the plurality of outputs. The fourth processing means receives a stream from the second output of the plurality of outputs.
The fifth processing means receives a stream from the third output of the plurality of outputs, performs a predetermined process on the received stream, and outputs the processed stream to the stream of the plurality of inputs. To the third input of.

Preferably, the selecting means associates the plurality of inputs with the plurality of outputs in a one-to-one correspondence.

In the above stream processing apparatus, the stream from the first processing means is supplied to one of the third and fourth processing means and the stream from the second processing means is controlled to the third stream by controlling the selecting means. And the other of the fourth processing means. Further, by controlling the selecting means, the stream from one of the first and second processing means is given to one of the third and fourth processing means, and the stream from the other of the first and second processing means is given. It is also possible to supply the stream to the fifth processing means and supply the stream after being processed by the fifth processing means to the other of the third and fourth processing means. As described above, since the allocation of the stream input to the selection means and the third to fifth processing means can be freely changed, the degree of freedom in the configuration of the device having the function of processing a plurality of streams is improved. Can be made.

[0011] Preferably, the selecting means includes one of the plurality of inputs and two of the plurality of outputs.
Correspond to Tsuto.

In the above stream processing apparatus, the stream from the first processing means is supplied to one of the third and fourth processing means and the fifth processing means by controlling the selecting means, and the fifth processing is performed. The stream processed by the means can be provided to the other of the third and fourth processing means. In addition, the stream from the first processing means is
And to the fourth processing means.

Preferably, the selecting means multiplexes at least two of the plurality of outputs to form a new one output.

According to the above stream processing apparatus, it is possible to output a plurality of streams from one system of output.

Preferably, the fifth processing means extracts desired information from the received stream to generate a partial stream, and supplies the generated partial stream to a third input of the plurality of inputs.

[0016] Preferably, at least one of the third processing means and the fourth processing means converts the interface format of the received stream and outputs it.

Preferably, at least one of the first stream and the second stream includes video data and / or audio data. At least one of the third processing means and the fourth processing means decodes video data and / or audio data included in the received stream.

Preferably, the fifth processing means extracts desired video data and / or audio data from the received stream, and the extracted video data and / or audio data is the third of the plurality of inputs. Give to input.

[0019] Preferably, at least one of the first stream and the second stream is encrypted. The fifth processing means cancels the encryption applied to the received stream.

Preferably, the fifth processing means encrypts the received stream.

[0021] Preferably, at least one of the first stream and the second stream is encrypted by the first encryption method. The fifth processing means cancels the encryption applied to the received stream. The stream processing device further includes sixth processing means. The sixth processing means receives a stream from the fourth output of the plurality of outputs, encrypts the received stream by the second encryption method, and outputs the encrypted stream to the first of the plurality of inputs. Give to 4 inputs.

Preferably, the stream processing device further comprises a storage means. At least one of the third processing means and the fourth processing means writes the received stream in the storage means. At least one of the first processing means and the second processing means reads a stream from the storage means and supplies the read stream to a corresponding input.

Preferably, at least one of the third processing means and the fourth processing means stores the write position in the storage means of the stream written in the storage means. At least one of the first processing means and the second processing means stores the read position in the storage means of the stream read from the storage means.

Preferably, at least one of the first processing means and the second processing means refers to a writing position stored in at least one of the third processing means and the fourth processing means. To read the stream from the storage means.

Preferably, at least one of the third processing means and the fourth processing means refers to a read position stored in at least one of the first processing means and the second processing means. , Writes a stream in an area other than an area in the storage unit in which a stream that has not been read is stored.

[0026] Preferably, at least one of the first stream and the second stream includes a plurality of packets. Each of the plurality of packets includes identification information for selecting necessity. The fifth processing means extracts a desired packet from a plurality of packets included in the received stream by referring to the identification information, generates a first partial stream, and outputs the first partial stream. The third input of the plurality of inputs is given. Third above
And at least one of the fourth processing means described above writes the received first partial stream in the storage means. At least one of the first processing means and the second processing means reads out the first partial stream from the storage means and supplies it as the second partial stream to the corresponding input. The third processing means and the fourth
At least one of the processing means of (1) extracts desired information from the received second partial stream.

[0027]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will now be described in detail with reference to the drawings. In the drawings, the same or corresponding parts are designated by the same reference numerals, and the description thereof will not be repeated.

(First Embodiment) <Overall Configuration of System> FIG. 1 is a block diagram showing an overall configuration of a system of a digital TV receiver according to a first embodiment of the present invention. The system shown in FIG. 1 includes a digital TV receiver 100, an AVHDD 112, and a digital VTR 113.

The digital TV receiver 100 includes a stream processing device 101, a memory 106, a CPU 107,
It includes an AV decoder 108 and a hard disk device 109.

The stream processing apparatus 101 includes a tuner 1
10 and 111, the matrix switch 102, and I
It includes an EEE 1394 interface 103, a demultiplexer 104, and an HDD interface 105.
The tuners 110 and 111 are tuners for receiving a digital TV broadcast, and output the received broadcast stream to the matrix switch 102. The stream processing device 101 includes a broadcast stream from the digital TV tuners 110 and 111 and an IEEE 1394 bus B.
2 stream / playback stream from the hard disk device 109 is input. The input stream is processed and accumulated in the memory 106, or output as a processed stream. In addition, the input stream may be output as it is. A stream is output from the stream processing device 101 to the IEEE 1394 bus B2, the hard disk device 109, and the AV decoder 108.

The memory 106 is the digital TV receiver 100.
Is the main memory of. The memory 106 is the CPU 107
It is used when executing software by and used to store data. The memory 106 stores the stream processed by the stream processing apparatus 101.

The AV decoder 108 decompresses the AV data received and reproduced by the digital TV receiver 100 and outputs it.

The hard disk device 109 records the stream output from the stream processing device 101 and stores the accumulated stream in the stream processing device 10.
Output to 1.

The AVHDD 112 is a hard disk device having a function of recording / reproducing a digital AV stream. The AVHDD 112 has an interface with the bus B2, and records a stream input from the bus B2 and outputs a reproduction stream to the bus B2.

The digital VTR 113 is a VTR device having a recording / playback function for a digital AV stream.
The digital VTR 113 records the stream input from the bus B2 and outputs the reproduction stream to the bus B2.

<Internal Configuration of Stream Processing Device 101>
FIG. 2 is a block diagram showing in detail the configuration of the stream processing apparatus 101 shown in FIG.

<Matrix Switch 102> Referring to FIG. 2, the matrix switch 102 includes input terminals T0-T.
7, T20, output terminals T10-T18, switch groups 200-208, and switch control register 209.

The input terminals T0 and T1 are connected to the tuner 11
Receive streams from 0 and 111. Input terminal T
2 and T3 receive streams from output ports OUT0 and OUT1 of demultiplexer 104. The input terminals T4 to T6 receive streams from the output ports OUT0 to OUT2 of the IEEE1394 interface 103. The input terminal T7 is the HDD interface 1
05 output port OUT0.
The input terminal T20 receives a control signal from the CPU bus B1.

The switch group 200-208 includes switches (00-70)-(08-78). Switch (0
0-70)-(08-78), when in the ON state, outputs the stream given to the input terminals T0-T7 to the output terminal T1.
It is given to 0-T18.

The switch control register 209 is the CPU 1
A control signal is applied to the switch group 200-208 in response to the control signal applied from 07 to the input terminal T20 via the bus B1. The control signal provided to the switch group 200-208 is a signal that specifies which of the switches included in the switch group is to be turned on. Each of the switch groups 200-208 responds to the control signal from the switch control register 209 by corresponding switch (0
Turn on one of 0-70)-(08-78). That is, each of the switch groups 200-208 selects one of the streams given to the input terminals T0-T7 and outputs it to the output terminals T10-T18 in response to the control signal from the switch control register 209.

In the matrix switch 102 configured as described above, each of the output terminals T10-T18 is associated with one of the input terminals T0-T7 in accordance with the control signal from the switch control register 209, and the correspondence is established. The stream given to the attached input terminal is the output terminal T10.
Output from each of T18. That is, the input terminal T
0-T7 to each of the 8 input streams
It can be output to any one of the two output terminals T10 to T18.

<IEEE1394 Interface 103
> The IEEE 1394 interface 103 has three input ports IN0-IN2 and three output ports OUT0-
OUT2. The streams from the output terminals T10-T12 of the matrix switch 102 are given to the input ports IN0-IN2 of the IEEE1394 interface 103. IEEE 1394 interface 10
The streams from the three output ports OUT0-OUT2 are given to the input terminals T4-T6 of the matrix switch 102. IEEE 1394 interface 103
Converts the interface format of the stream from the bus B2 and outputs the converted stream from the output ports OUT0 to OUT2. The stream supplied to the input ports IN0 to IN2 is converted into the interface format and output to the bus B2.

<HDD Interface 105> The HDD interface 105 has two input ports IN0 and IN1 and one output port OUT0. HDD
Input ports IN0 and IN1 of interface 105
Are provided with streams from the output terminals T18 and T17 of the matrix switch 102. The stream from the output terminal OUT0 of the HDD interface 105 is given to the input terminal T7 of the matrix switch 102. The HDD interface 105 converts the interface format of the stream from the hard disk device 109 and outputs the stream from the output port OUT0, and converts the stream given to the input ports IN0 and IN1 to the hard disk device 109 after converting the interface format. .

<Demultiplexer 104> The demultiplexer 104 has four input ports IN0-IN3 and two output ports OUT0 and OUT1. The input ports IN0-IN3 of the demultiplexer 104 have
The streams from the output terminals T13 to T16 of the matrix switch 102 are given. Demultiplexer 104
From the output ports OUT0 and OUT1 of the matrix switch 102 are input terminals T2 and T2.
Given to 3. The demultiplexer 104 can simultaneously process the four streams provided to the input ports IN0 to IN3. The demultiplexer 104 is
The processed stream is output from the output ports OUT0 and OUT1. Also, the data resulting from the demultiplexing process (the process of extracting data from the stream) is recorded in the memory 106 via the bus B1, or the AV decoder 108 is used.
Or output to.

<Several Processes Simultaneously Performed> Next, it will be sequentially described that various processes and outputs for various streams can be simultaneously performed in the system configured as described above.

<Processing 1> The received program is transferred to the AVHDD 11
A process (process 1) of temporarily accumulating in 2 and reproducing / displaying with a time difference will be described with reference to FIGS. 1, 2 and 3A.

First, a process of extracting a stream of a desired program from the broadcast stream and accumulating it in the AVHDD 112 will be described.

A control signal for instructing to turn on the switch 03 of the switch group 203 and the switch 20 of the switch group 200 (stream passes) is the CPU 107.
To the switch control register 209 of the matrix switch 102. In response to this, the switch control register 209 gives a control signal for turning on the switches 03 and 20 to the switch groups 203 and 200. In response to this, the switches 03 and 20 are turned on.

The broadcast stream (encrypted stream) received by the tuner 110 is the matrix switch 1
02 is input to the input terminal T0, passes through the switch 03, and is output from the output terminal T13.
Is input to the input port IN0.

The demultiplexer 104 has the input port I
The CPU 107 decrypts the stream input to N0 and extracts the stream forming the desired program.
Is preset by. The demultiplexer 104 decrypts the broadcast stream input to the input port IN0, takes out the stream forming the desired program, and outputs the stream from the output port OUT0. The stream output from the output port OUT0 of the demultiplexer 104 is given to the input terminal T2 of the matrix switch 102. The stream input to the input terminal T2 passes through the switch 20 and is output from the output terminal T10.
Input port IN0 of EE1394 interface 103
Given to. IEEE 1394 interface 103
Sends this stream to the AVHDD 112 via the bus B2.
Send to. The AVHDD 112 stores this stream.

Next, a process of sequentially reading the program stream accumulated in the AVHDD 112 and performing the time difference reproduction of the received program will be described.

A control signal for instructing to turn on the switch 44 of the switch group 204 in addition to the switch 03 of the switch group 203 and the switch 20 of the switch group 200 is given from the CPU 107 to the switch control register 209 of the matrix switch 102. . In response to this, the switch control register 209 gives a control signal for turning on the switch 44 in addition to the switches 03 and 20 to the switch group 204. In response to this, switch 44 is turned on in addition to switches 03 and 20.

In addition to the above-mentioned settings, the demultiplexer 104 is further set by the CPU 107 to take out AV data from the stream input from the input port IN1 and output it to the AV decoder 108.

After that, the program streams accumulated in the AVHDD 112 are sequentially read out and given from the output port OUT0 of the IEEE 1394 interface 103 to the input terminal T4 of the matrix switch 102. The stream supplied to the input terminal T4 passes through the switch 44, is output from the output terminal T14, and is input to the input port IN1 of the demultiplexer 104. Demultiplexer 10
4 takes out the AV data that constitutes the program and outputs it as AV data.
It is given to the decoder 108. In this way, the playback program A
Perform V playback. As described above, the received program is AVed.
Processing for temporarily accumulating in the HDD 112 and reproducing / displaying at a time difference is performed.

<Process 2> Next, a process (process 2) for dubbing a program stream from the digital VTR 113 to the external hard disk device 109 will be described with reference to FIGS. 1, 2 and 3.
This will be described with reference to (b). Process 2 is performed in parallel with process 1 described above.

A control signal instructing to turn on the switch 58 of the switch group 208 is given from the CPU 107 to the switch control register 209 of the matrix switch 102. In response to this, the switch control register 209
Switches the control signal for turning on the switch 58 to the switch group 2
Give to 08. In response to this, the switch 58 is turned on. In addition, the IEEE13 so that the reproduction stream from the digital VTR 113 is output from the output port OUT1.
94 interface 103 is set. In addition, the HDD interface 105 is configured to store the stream given to the input port IN0 in the hard disk device 109.
Is set.

When the digital VTR 113 is reproduced after the above setting, the reproduced stream is given from the output port OUT1 of the IEEE 1394 interface 103 to the input terminal T5 of the matrix switch 102 as shown in FIG. 58 through the output terminal T18 to the input terminal IN of the HDD interface 105
0 is stored in the hard disk device 109.

Since the passage route of the stream in the matrix switch 102 in the process 2 is different from the passage route in the process 1 described above, the process 2 can be simultaneously performed in parallel with the process 1.

<Process 3> Next, a program stream from another received broadcast is taken out and is taken out from the hard disk device 109.
FIG. 1, FIG. 2 and FIG.
This will be described with reference to (c). Process 3 is performed in parallel with the above-mentioned first and process 2.

A control signal for instructing to turn on the switch 15 of the switch group 205 and the switch 37 of the switch group 207 is sent from the CPU 107 to the matrix switch 1
02 switch control register 209. In response to this, the switch control register 209 sets the switch 1
A control signal for turning on the switches 5 and 37 is sent to the switch group 205.
And 207. In response to this, the switches 15 and 37 are turned on.

The broadcast stream received by the tuner 111 is applied to the input terminal T1 of the matrix switch 102, passes through the switch 15 and is output from the output terminal T15, and is input to the input port IN2 of the demultiplexer 104.

The demultiplexer 104 is preset by the CPU 107 so as to take out a stream forming a desired program. Demultiplexer 10
4 takes out a stream forming a desired program from the broadcast stream input to the input port IN2 and outputs it from the output port OUT1. The stream output from the output port OUT1 of the demultiplexer 104 is given to the input terminal T3 of the matrix switch 102. The stream input to the input terminal T3 passes through the switch 37, is output from the output terminal T17, and is applied to the input port IN1 of the HDD interface 105. The HDD interface 105 stores this stream in the hard disk device 109.

The passage route of the stream in the matrix switch 102 in the process 3 is the above process 1 and process 2.
Since it is different from the passage route in, the processing 3 can be simultaneously performed in parallel with the first and the processing 2.

<Process 4> Next, the hard disk device 10
A case where the data broadcast information stored in 9 is taken out, placed in the memory 106, and processed by the CPU 107 (process 4) will be described with reference to FIGS. 1, 2 and 3D. The process 4 is performed in parallel with the above-mentioned first to third processes.

A control signal instructing to turn on the switch 76 of the switch group 206 is given from the CPU 107 to the switch control register 209 of the matrix switch 102. In response to this, the switch control register 209
Switches the control signal for turning on the switch 76 to the switch group 2
Give to 06. In response to this, the switch 76 is turned on. Further, the demultiplexer 104 is set by the CPU 107 so that the data broadcast information is taken out from the stream given to the input port IN3 and stored in the memory 106.

The HDD interface 105 takes out the data broadcasting information stored in advance in the hard disk device 109 and supplies it from the output port OUT0 to the input terminal T7 of the matrix switch 102. Input terminal T7
The stream applied to the input port I of the demultiplexer 104 passes from the output terminal T16 to the input port I of the demultiplexer 104.
Given to N3. The demultiplexer 104 extracts the data broadcasting information from the stream given to the input port IN3 according to the setting and stores it in the memory 106. This allows the CPU 107 to refer to and process the data broadcast information stored in the memory 106.

Since the passage route of the stream in the matrix switch 102 in the process 4 is different from the passage route in the process 1-process 3 described above, the process 4 is processed in the process 1-process 3.
Can be done in parallel with.

<Multiple processes for one stream>
Next, it will be described that the system shown in FIG. 1 can perform a plurality of processes and outputs for one stream.

<Case 1> First, FIG. 1, FIG. 2 and FIG. 4A will be described with respect to a case (case 1) in which AV reproduction processing of a broadcast program and processing of storing audio data of the program in the memory 106 are simultaneously performed. The description will be made with reference.

A control signal instructing to turn on the switch 03 of the switch group 203 and the switch 04 of the switch group 204 is sent from the CPU 107 to the matrix switch 1
02 switch control register 209. In response to this, the switch control register 209 sets the switch 0
The control signal for turning on 3 and 04 is a switch group 203.
And 204. In response to this, the switches 03 and 04 are turned on. Also, the AV data of the program to be viewed is set to P from the stream given to the input port IN0.
The demultiplexer 10 is operated by the CPU 107 so that the demultiplexer 10 extracts the ES packet format and outputs it to the AV decoder 108.
4 is set. Further, the demultiplexer 104 is set so as to extract audio data of the program to be viewed from the stream given to the input port IN1 as an elementary stream and store it in the memory 106.

The broadcast stream from the tuner 110 is given to the input terminal T0 of the matrix switch 102.
This stream passes through the switch 03 and goes to the output terminal T13.
To the input port IN0 of the demultiplexer 104. The demultiplexer 104 extracts the AV data to be viewed from this stream in the PES packet format and outputs this to the AV decoder 108. On the other hand, the broadcast stream from the tuner 110 is the matrix switch 1
02 through the switch 04, and is also given from the output terminal T14 to the input port IN1 of the demultiplexer 104.
The demultiplexer 104 extracts the audio data of the viewing target program from this stream in the elementary stream format and stores it in the memory 106.

In this way, one stream can be branched and a plurality of types of processing can be performed simultaneously.

<Case 2> Next, a case where the same program is recorded in the AV HDD 112 in the transport stream format at the same time as the AV reproduction of the broadcast program stream is performed.
This will be described with reference to FIGS. 2 and 4 (b).

The control signal for instructing to turn on the switch 03 of the switch group 203, the switch 04 of the switch group 204 and the switch 20 of the switch group 200 is CP.
It is given from U107 to the switch control register 209 of the matrix switch 102. In response to this, the switch control register 209 sends a control signal for turning on the switches 03, 04, 20 to the switch groups 203, 204, 200.
Give to. In response to this, the switches 03, 04, 20 are turned on. Further, the CPU 107 sets the demultiplexer 104 so as to extract the AV data of the program to be viewed in the PES packet format from the stream given to the input port IN0 and output it to the AV decoder 108. Further, the demultiplexer 104 is set so as to take out the stream of the program to be viewed from the stream given to the input port IN1 and output it from the output port OUT0 in the transport stream format. Also,
The stream given to the input port IN0 is AVHDD
The IEEE 1394 interface 103 is set to record in 112.

The broadcast stream from the tuner 110 is given to the input terminal T0 of the matrix switch 102.
This stream passes through the switch 03 and goes to the output terminal T13.
To the input port IN0 of the demultiplexer 104. The demultiplexer 104 extracts the AV data to be viewed from this stream in the PES packet format and outputs it to the AV decoder 108. On the other hand, the tuner 110
The broadcast stream from A passes through the stream switch 04 of the matrix switch 102 and is input from the output terminal T15 to the input port IN1 of the demultiplexer 104.
The demultiplexer 104 extracts the viewing target program from this stream as a transport stream and outputs it from the output port OUT0. The stream output from the output port OUT0 of the demultiplexer 104 is given to the input terminal T2 of the matrix switch 102, passes through the switch 20, and is output from the output terminal T10 to IEEE1394.
It is given to the input port IN0 of the interface 103. The IEEE 1394 interface 103 records this stream in the AVHDD 112 via the bus B2.

In this way, one input stream can be branched to perform a plurality of types of processing simultaneously.

<Other Processing> Next, the program stream from the received broadcast is taken out, the broadcast encryption applied to this program stream is released, and then the encryption for the hard disk recording is applied to the hard disk device 109. The recording process will be described with reference to FIGS. 1, 2, and 5.

The control signal for instructing to turn on the switch 15 of the switch group 205, the switch 26 of the switch group 206 and the switch 37 of the switch group 207 is CP.
It is given from U107 to the switch control register 209 of the matrix switch 102. In response, switch control register 209 causes switches 15, 26 and 37 to
A control signal for turning on the switch group 205, 206, 2
Give to 07. In response to this, switches 15, 26 and 37 are turned on. The broadcast stream received by the tuner 111 is the input terminal T1 of the matrix switch 102.
Is input to the input port IN2 of the demultiplexer 104 through the switch 15 and is output from the output terminal T15.
Entered in.

The demultiplexer 104 has the input port I
To remove a stream constituting a program to be recorded from the stream input from N2 to decrypt the broadcast code, and to encrypt a stream input from the input port IN3 for hard disk recording. It is preset by the CPU 107.

The demultiplexer 104 has the input port I
A stream forming a desired program is taken out from the broadcast stream input to N2, the broadcast code applied to this stream is released, and the stream is output from the output port OUT0.

Output port OU of demultiplexer 104
The stream output from T0 is the matrix switch 1
02 input terminal T2. The stream input to the input terminal T2 passes through the switch 26 and is output to the output terminal T1.
6 and the input port IN3 of the demultiplexer 104.

The demultiplexer 104 has the input port I
The stream input to N3 is encrypted for hard disk recording and output from the output port OUT1.

Output port OU of demultiplexer 104
The stream output from T1 is the matrix switch 1
02 input terminal T3. The stream input to the input terminal T3 passes through the switch 37 and is output to the output terminal T1.
7 and is given to the input port IN1 of the HDD interface 105. HDD interface 105
Stores this stream in the hard disk device 109.

In this way, the input stream is de-encrypted for broadcast by the demultiplexer 104, and is again input to the demultiplexer 104 via the matrix switch 102. Then, the hard disk recording encryption processing is performed in the demultiplexer 104, and the data is stored again in the hard disk device 109 from the hard disk interface 105 via the matrix switch 102.

<Effect> As described above, in the system according to the first embodiment, it is possible to simultaneously process a plurality of streams in parallel or directly output an input stream. Further, the system configuration can be freely changed according to the settings of the switches in the matrix switch 102.

Matrix switch 102, IEEE
The number of input / output ports of the E1394 interface 103 and the HDD interface 105 is not limited to the above number, and can be set freely according to the required system configuration. Also, other types of stream input / output interfaces and stream processing circuits are not excluded.

(Second Embodiment) <Overall Configuration of System> FIG. 6 is a block diagram showing the overall configuration of a system of a digital TV receiver according to a second embodiment of the present invention. The system shown in FIG. 6 includes a digital TV receiver 500, an AVHDD 112, and a digital video camera 508.

The digital TV receiver 500 includes a stream processing device 501, a memory 106, a CPU 107,
It includes an Ethernet (R) interface 507 and a DVD drive device 509.

The stream processing device 501 includes a tuner 1
11, the matrix switch 502, and the IEEE 139
4 interface 503 and demultiplexer 504
, AV decoder 505, and HDD interface 10
5 and a DMA circuit 506. To the stream processing device 501, the broadcast stream from the tuner 111, the stream from the bus B2, and the reproduction stream from the DVD drive device 509 are input. The input stream is processed and accumulated in the memory 106, or output as a processed stream. In addition, the input stream may be output as it is. Further, the stream can be accumulated in the memory 106 or the stream can be read from the memory 106 and input.
A stream is output from the stream processing device 501 to the bus B2 / DVD drive device 509.

The DVD drive device 509 records the stream output from the stream processing device 501 and records the accumulated stream in the stream processing device 5.
Output to 01.

Ethernet (R) interface 507
Stores the data received via the Ethernet (R) in the memory 106 or transmits the data in the memory 106 to the Ethernet (R).

The digital video camera 508 reproduces the recorded AV stream via the bus B2 and records the AV stream input via the bus B2.

<Internal Configuration of Stream Processing Device 501>
FIG. 7 is a block diagram showing in detail the configuration of the stream processing device 501 shown in FIG.

<Matrix Switch 502> Referring to FIG. 7, the matrix switch 502 has an input terminal T30-
It includes T37 and T50, output terminals T40 to T48, a switch group 600-608, and a switch control register 609.

The input terminal T30 receives the stream from the output port OUT0 of the DMA circuit 506. The input terminal T31 receives the stream from the tuner 111.
The input terminals T32 and T33 are connected to the demultiplexer 50.
It receives streams from four output ports OUT0 and OUT1. The input terminals T34 to T36 are IEEE13
94 interface 503 output ports OUT0-OU
Receive stream from T2. Input terminal T37 is H
It receives a stream from the output port OUT0 of the DD interface 105. The input terminal T50 receives the control signal from the bus B1.

The switch group 600 includes switches 00-3.
Including 0,70. When the switches 00-30 and 70 are in the ON state, they provide the streams given to the input terminals T30-T33 and T37 to the output terminal T40. Switch group 6
01 includes switches 01-31 and 71. Switch 0
1-31 and 71 are input terminals T30-
Output terminal T4 for the stream given to T33 and T37
Give to one. The switch group 602 includes switches 02-72.
including. When the switch 02-72 is in the ON state, it supplies the stream supplied to the input terminals T30-T37 to the output terminal T42. The switch group 603 includes the switch 13-
Including 73. When the switch 13-73 is in the ON state,
The stream given to the input terminals T31-T37 is given to the output terminal T43. Switch group 604 is switch 0
4,14,44-74 are included. Switches 04, 14, 4
When the 4-74 is in the ON state, the input terminals T30, T3
1, the streams given to T34 to T37 are given to the output terminal T44. The switch group 605 includes switches 05,
Including 15, 45-75. Switches 05, 15, 45-
75 is an input terminal T30, T31, T
34-T37 outputs the stream provided to the output terminal T45.
Give to. The switch group 606 includes switches 06, 16,
46-76 are included. Switch 06,16,46-76
Is in the ON state, the input terminals T30, T31, T34
-The stream given to T37 is given to the output terminal T46. Switch group 607 includes switches 07-67. When the switches 07-67 are in the ON state, they output the stream provided to the input terminals T30-T36 to the output terminal T4.
Give to 7. The switch group 608 includes switches 08-68.
including. When the switches 08-68 are in the ON state, the streams supplied to the input terminals T30-T36 are supplied to the output terminal T48.

In the switch group 600-608 shown in FIG. 7, some switches are omitted as compared with the switch group 200-208 shown in FIG. This is IEEE1
This is because a switch that does not pass a stream, such as outputting a stream input from the 394 interface 503 to the IEEE 1394 interface 503, is omitted.

The switch control register 609 is the CPU 1
A control signal is applied to the switch group 600-608 in response to the control signal applied from 07 to the input terminal T50 via the bus B1. The control signal provided to the switch group 600-608 is a signal that specifies which of the switches included in the switch group is to be turned on. The switch group 600-608 includes a switch control register 609.
One of the switches is turned on in response to the control signal from. That is, the switch group 600-608 is one of the streams given to the input terminals T30-T37.
One of them is selected and output to the output terminals T40 to T48.

In the matrix switch 502 having the above-described structure, 8 input to the input terminals T30 to T37 is applied.
9 input terminals each with 9 output terminals T40-
It can be output to the designated one of T48.

<IEEE1394 Interface 503
> IEEE 1394 interface 503 has two input ports IN0 and IN1 and three output ports OUT0-
OUT2. Streams from the output terminals T40 and T41 of the matrix switch 502 are applied to the input ports IN0 and IN1 of the IEEE 1394 interface 103. IEEE 1394 interface 50
The streams from the output ports OUT0-OUT2 of No. 3 are input terminals T34-T3 of the matrix switch 502.
Given to 6. IEEE 1394 interface 50
3 converts the interface format of the stream from the bus B2 and outputs it from the output ports OUT0-OUT2, and converts the stream given to the input ports IN0 and IN1 to the bus B2 after converting the interface format.

<HDD Interface 105> The HDD interface 105 includes two input ports IN0 and IN1 and one output port OUT0. HDD
Input ports IN0 and IN1 of interface 105
Are supplied with streams from the output terminals T48 and T47 of the matrix switch 502. The stream from the output terminal OUT0 of the HDD interface 105 is given to the input terminal T37 of the matrix switch 502. The HDD interface 105 converts the stream from the DVD drive device 509 into its interface format and outputs it from the output port OUT0, and converts the stream given to the input ports IN0 and IN1 into its interface format to the DVD drive device 509. Output.

<Demultiplexer 504> The demultiplexer 504 has three input ports IN1-IN3 and two output ports OUT0 and OUT1. The input ports IN1-IN3 of the demultiplexer 504 are
The streams from the output terminals T44 to T46 of the matrix switch 502 are given. Demultiplexer 504
The streams from the output ports OUT0 and OUT1 of are input to the input terminals T32 and T33 of the matrix switch 502. The demultiplexer 504 can simultaneously process the three streams provided to the input ports IN1-IN3. Demultiplexer 504
Outputs the processed stream to the output ports OUT0, OUT
Output from 1. In addition, the data resulting from the demultiplexing process (the process of extracting data from the stream) is transferred to the bus B.
1 to the memory 106.

<DMA Circuit 506> DMA Circuit 506
Has an input port IN0 and an output port OUT0. The stream from the output terminal T43 of the matrix switch 502 is applied to the input port IN0 of the DMA circuit 506. Output port OUT0 of DMA circuit 506
The stream from is supplied to the input terminal T30 of the matrix switch 502. The DMA circuit 506 writes the stream given to the input port IN0 to the memory 106 via the bus B1 and stores the write position of the stream in the memory 106.
The stream written in 6 is read out via the bus B1 and output from the output port OUT0, and the read position of the stream in the memory 106 is stored.

<Various Processes> Next, the case where various processes are performed on various streams in the system shown in FIG. 6 will be described.

<Processing 1> First, the digital video camera 5
The case where the video / audio reproduced from 08 is decoded by the AV decoder 505 and reproduced is shown in FIG. 6, FIG. 7 and FIG.
A description will be given with reference to (a).

A control signal for instructing to turn on the switch 53 of the switch group 603 and the switch 02 of the switch group 602 is applied from the CPU 107 to the switch control register 609. In response to this, the switch control register 609 gives a control signal for turning on the switches 53 and 02 to the switch groups 603 and 602. In response to this, the switches 53 and 02 are turned on. In addition, DM the address of the data storage area in the memory 106.
The A circuit 506 is set, and the DMA circuit 506 is set so as to store the input stream in this data storage area and read the stream from the data storage area in response to a data request from the AV decoder 505.

From digital video camera 508 to bus B2
The video / audio stream output to is IEEE1394
Input to the interface 503 and output port OUT1
Is input to the input terminal T35 of the matrix switch 502. This stream passes through the switch 53 and is input from the output terminal T43 to the input port IN0 of the DMA circuit 506. The DMA circuit 506 writes this stream in the data storage area in the memory 106. DMA at this time
The circuit 506 refers to the read position of the stream in the memory 106 so that the stream is not written in the area where the stream that has not been read is stored. That is, the stream is written to the area in the memory 106 other than the area in which the stream that has not been read is stored.

When a data request is issued from the AV decoder 505, the DMA circuit 506 reads the stream stored in the data storage area in the memory 106 and outputs it from the output port OUT0 to the input terminal T of the matrix switch 502.
Give to 30. At this time, the DMA circuit 506 causes the memory 1
Referring to the write position of the stream in 06,
Read the stream from the area where the stream is already stored. This stream is stream switch 02
Through the output terminal T42 to the input port IN0 of the AV decoder 505, and the AV decoder 505 performs AV decoding processing for display / reproduction.

<Processing 2> Next, a case where demultiplexing processing is performed on a stream received via the Ethernet (R) and taken out by the CPU 107 will be described with reference to FIGS. 6 and 7.
Also, description will be made with reference to FIG.

A control signal instructing to turn on the switch 04 of the switch group 604 is given from the CPU 107 to the switch control register 609. In response to this, the switch control register 609 gives a control signal for turning on the switch 04 to the switch group 604. In response to this, the switch 04 is turned on. Also, the input port IN1
The demultiplexer 504 is set so that the demultiplexing process is performed on the stream provided to the memory 106 and the processing result is stored in the memory 106. In addition, the memory 106
Of the DMA circuit 50 so that the stream is read from the received stream storage area in the output stream OUT0 and output from the output port OUT0.
6 is set.

Ethernet (R) interface 507
The packet received by is stored in the Ethernet (R) data receiving area of the memory 106 via the bus B1. The CPU 107 processes this Ethernet (R) packet, extracts a desired stream from the packet, and stores it in the memory 10
The data is accumulated in the reception stream accumulation area 6 of FIG.

The DMA circuit 506 reads the stream accumulated in the reception stream accumulation area of the memory 106, and outputs the stream from the output port OUT0 to the matrix switch 502.
Input to the input terminal T30. This stream passes through the switch 04 and the output terminal T44 to the demultiplexer 5
No. 04 input port IN1. The demultiplexer 504 performs a demultiplexing process on the input stream, and stores the resulting data in the memory 106.

As described above, the stream received by an interface such as Ethernet (R) which is not a normal stream interface can be demultiplexed.

<Process 3> Next, a process of extracting a program table, deciphering key data, and the like processed by the software of the digital TV receiver 500 from the broadcast stream (transport stream) received by the tuner 111 will be described with reference to FIG. This will be described with reference to FIGS. 7 and 8C.

First, the data format of the transport stream and the demultiplexing process for it will be described. The transport stream is composed of a series of transport stream packets. The transport stream packet is a packet having a length of 188 bytes and stores various digital broadcast data. The data stored in the transport packet is mainly divided into PES (Packetized Elementary Stream) packet and section data. The PES packet stores video and audio data (elementary data) that constitutes a broadcast program. The section data stores a program guide, deciphering key data, and the like, which are subject to processing by software of the digital TV receiver. A packet identifier (PID) is attached to each transport stream packet. The packet identifier (PID) indicates the type of stored data, that is, whether it is video, audio, or a program table. Further, there is header information at the beginning of the section data. The header information includes
Information such as more detailed types and update status of the contents of the section data is embedded.

The demultiplexer 504 identifies the PID of the input transport stream packet,
It is determined whether it is an elementary stream of a program to be received or section data to be received, and selection (PID filter processing) is performed in transport stream packet units. Next, the PES packet and the section data are extracted from the transport stream packet. For the retrieved section data,
Selection processing (section filtering processing) is performed based on the header information of the section data. The general processing content of the section filter processing is to compare 16 bytes of the header portion of the section data with 32 types of condition data and determine whether there is a match. After the sorted PES packets and section data are temporarily stored in the memory 106 for each type,
The PES packet, that is, video and audio data is decompressed by the AV decoder 505 and reproduced. On the other hand, the section data is processed by software, the program guide is extracted and the decryption key data is extracted, and the operation of the digital TV receiver 500 is controlled based on this.

In general, the data rate of the transport stream in digital TV broadcasting is 30 Mbps (20
000 packets / second), and it is necessary to execute demultiplexing processing in real time at this data rate. In particular, the section filtering process needs to be executed up to 10 times for one transport stream packet. That is, 32 types × 16 for section data of 20000 packets × 10 per second.
Byte comparison processing (comparison processing for a total of 100 MB or more)
Need to do.

In the second embodiment, the PID filter process and the section filter process of the demultiplexing process are not performed in real time but are performed twice.

First, the demultiplexer 504 extracts the elementary data to be received by the PID filter processing and stores it in the memory 106. Meanwhile, the demultiplexer 5
04 generates a partial transport stream in which only the transport stream packet having the PID of the section data to be received of the input transport stream remains, and temporarily stores it in the memory 106. The temporarily stored partial transport streams are sequentially taken out from the memory 106 and are again demultiplexed by the demultiplexer 50.
4, and section filtering is performed at this time.

Generally, 1 to 2 of the data rate of 30 Mbps of the transport stream of digital TV broadcasting
Mbps is section data, and the rest is elementary data. That is, the average data rate of the partial transport stream composed only of the section data to be received extracted by the PID filter process is at most 1 to 2 Mbps. As a result, the capacity of the comparison processing required for the section filter processing is 1/30 as compared with the case where the received transport stream is processed in real time as described above.
It is reduced to ~ 1/15. As a result, the circuit scale is reduced, and the section filter processing by software becomes possible.

The operation of the above-described two-stage demultiplexing process will be specifically described below. Here, the average data rate of the section data to be received in the transport stream received from the broadcast is 1 Mbps.

The control signal for instructing to turn on the switch 15 of the switch group 605, the switch 23 of the switch group 603 and the switch 04 of the switch group 604 is CP.
It is given to the switch control register 609 from U107. In response to this, the switch control register 609 gives a control signal for turning on the switches 15, 23 and 04 to the switch group 604. In response to this, switch 1
5, 23 and 04 are turned on. Also, input port I
For the stream input from N2, only the packet containing the section data to be received is extracted by the PID filter process, and the partial transport stream consisting of this packet is created and this is output port OUT.
The demultiplexer circuit 504 is set to output from 0. For the stream input from the input port IN1, section data selection and memory 10
The demultiplexer 504 is set so as to perform the accumulation process for the data of the data in the No. 6 storage unit. Further, the address of the data storage area in the memory 106 is set in the DMA circuit 506, and the input port IN
The DMA circuit 506 is set to accumulate the stream given to 0 in this area, read the accumulated data at a low speed (1 Mbps), and output it from the output port OUT0.

The stream received by the tuner 111 is input to the input terminal T31 of the matrix switch 502,
The signal passes through the switch 15 and is input from the output terminal T45 to the input port IN2 of the demultiplexer 504. The demultiplexer 504 extracts only the packet containing the section data from this stream by PID filtering, generates a partial transport stream consisting of only the section data, and outputs this from the output port OUT0. Since the average data rate of the section data to be received is 1 Mbps, the data rate of this partial stream is 1 Mbps on average. This partial stream is supplied to the input terminal T32 of the matrix switch 502, passes through the switch 23, and is output from the output terminal T43 to the DMA circuit 50.
6 is input to the input port IN0. DMA circuit 506
Temporarily stores the input partial stream in the data storage area in the memory 106. At the same time, when a stream is stored in the data storage area, the DMA circuit 506 reads this stream at low speed (1 Mbps) and outputs it from the output port OUT0. This stream passes through the switch 04 of the matrix switch 502 and is input from the output terminal T44 to the input port IN1 of the demultiplexer 504. Demultiplexer 504
Performs section data extraction and section filter processing on the stream input to the input port IN1, and records the processing result data in a predetermined area of the memory 106.

As described above, it is possible to temporarily store a stream for performing section filter processing that does not require real-time processing, and then process it again as a low-speed stream.

As described above, since the demultiplexing process is performed in two stages, it is possible to reduce the circuit scale of the circuit that performs the section filter process and perform the section filter process by software.

Although the DMA circuit 506 reads the partial transport stream accumulated in the memory 106 at a low speed here, instead of this, the demultiplexer 504 issues a data request, and the DMA circuit 506 responds to this. Reads a partial transport stream from the data storage area in the memory 106 and demultiplexer 50
4 may be supplied. That is, a data request signal is provided corresponding to each output terminal of the matrix switch 502, and the data request signal traces the connection of the matrix switch 502 in the opposite direction to the data and the input port associated with the output terminal. Output to the stream source. In the above example, the demultiplexer 504
The data request signal is output from the input port IN1 of the DMA circuit 50 via the matrix switch 502.
Input from the 6th output port OUT0 to the DMA circuit 506. The DMA circuit 506 reads the partial stream stored in the memory 106 in response to the data request signal. The read partial stream is supplied to the input port IN1 of the demultiplexer 504 via the matrix switch 502. By supplying the data in response to the data request in this way, it becomes possible to flexibly execute the demultiplexing process even when the data rate of the partial stream to be processed changes.

<Effect> As described above, in the second embodiment, since the DMA circuit 506 capable of reading and writing the stream from the memory 106 is provided, the data can be temporarily accumulated during the stream processing and the CPU 107 can perform the processing. The processed data can be processed as a stream, and the degree of freedom in system configuration is further improved.

Since the stream is supplied in accordance with the data request signal, the degree of freedom in operation and the types of input / output / processing means that can be combined are increased.

The number of input and output ports shown in this embodiment is an example, and the number is not limited to this.
In addition, the data request signal is sent from the demultiplexer 504 to the DM.
Although the example of delivering to the A circuit 506 has been described, the present invention is not limited to this, and it is possible to deliver from all stream supply destinations to stream supply sources according to the setting of the matrix switch. Further, not only the data request signal but also other control signals can be similarly passed.

(Third Embodiment) In the first and second embodiments, the switch group of the matrix switch selects one stream from the streams input from the eight input terminals and outputs it. . The switch group of the matrix switch according to the third embodiment is characterized in that a plurality of streams can be multiplexed and output.

<Structure of Switch Group> FIG. 9 is a block diagram showing the structure of the switch group according to the third embodiment.
The configuration other than the switch group is the same as the configuration of the system shown in FIGS. 6 and 7. Referring to FIG. 9, each input stream 0-7 is captured in a respective register 800-807 each time the data enable signal 0-7, which indicates that there is valid data input, becomes active. The data enable signal 0-7 is input to the multiplex control circuit 808, and the multiplex control circuit 808 manages which of the registers 800-807 the data is stored. In addition, the multiplex control circuit 808
Controls the selector 809 to sequentially select the data stored in the registers 800-807 and outputs the output data enable signal and the output data selection signal. However, an output selection signal is input from the switch control register 609 and controls whether or not multiple outputs are made for each input. The output data enable signal and the output data selection signal are also input to the output destination instruction circuit 810. In the output destination instruction circuit 810, the correspondence between the input to the switch group and the output destination is indicated by the switch control register 609.
Specified by. Based on this correspondence, the output destination instruction circuit 810 outputs an output destination instruction signal. The output destination instruction signal indicates an output destination to which the input signal indicated by the output data selection signal should be output. In this way, the switch group multiplexes and outputs the designated one of the plurality of input data, and at the same time,
It is possible to identify each multiplexed data and output a signal indicating the output destination. In the circuit to which the multiplexed output data and the output destination instruction signal are input, refer to the output destination instruction signal to separate the original data from the multiplexed output data,
Individual processing can be performed on each data.

<Operation of Switch Group> FIG. 10 shows an example of an operation timing chart of this switch group. In this example, it is assumed that data 0, 1, 2, and 3 are input, and the switch control register 609 instructs to output the data 0, 1, and 2 out of them. Further, it is assumed that the switch control register 609 is designated to output data 0 to the output destination 1, data 1 to the output destination 0, and data 2 to the output destination 3. First, when data 0 is input, it is stored in the register 800, and at the next clock, the selector 809
Simultaneously selects and outputs data 0, and at the same time, the output destination designating circuit 8
An output destination instruction signal indicating the output destination 1 is output from 10. Next, data 1, 2, and 3 are input at the same time and written in registers 801 to 803, respectively. In accordance with an instruction from the multiplex control circuit 808, the data 1 outputs the data 1 at the next clock, and at the same time, outputs the output destination instruction signal indicating the output destination 0, and further outputs the data 2 at the next clock.
Is output, an output destination instruction signal indicating the output destination 3 is output. However, the data 3 is the switch control register 6
It is not output because there is no output instruction from 09. By implementing the switch group that operates in this way, the AV decoder 5 is multiplexed with a plurality of stream inputs to form one stream.
You can enter in 05 etc.

FIG. 11 shows another example of the operation timing chart of this switch group. In this example, data 0, 1,
2 and 3 are input, and the switch control register 609 is instructed to multiplex output of the data 0 and 1. Further, it is assumed that the switch control register 609 is designated to branch data 0 to the output destination 1 and branch data 1 to the output destination 0 and the output destination 3 for output.
First, when data 0 is input, it is stored in the register 800, and at the next clock, the selector 809 selects and outputs data 0, and at the same time, the output destination instruction circuit 810 outputs the output destination 1
Is output. Next data 1,
2 and 3 are input at the same time, and registers 801-8
Written in 03. These data are multiplexed control circuit 8
According to the instruction of 08, data 1 is output at the next clock and at the same time, an output destination instruction signal indicating the output destination 0 and the output destination 3
And an output destination instruction signal indicating But data 2
And data 3 are not output because there is no output instruction from the switch control register 609. By implementing the switch group that operates in this manner, a plurality of stream inputs can be multiplexed into one stream, and this one stream can be input to the AV decoder 505 or the like that individually processes the plurality of streams. Also, the AV decoder 505
It is also possible to use two of the three streams input to the same stream. That is, branching one stream and executing two types of processing described in the first embodiment can also be realized by using a switch group that multiplexes and outputs output data.

<Functions Realizable in System> By providing the switch group as described above, the system shown in FIGS. 6 and 7 can realize the following functions. Here, it is assumed that the AV decoder 505 is capable of receiving a stream in which a plurality of streams are multiplexed as an input stream, extracting each of the multiplexed data based on the output destination instruction signal, and decoding it as separate AV data.

[0135] The playback stream from the digital video camera 508 connected to the bus B2 and the DVD drive device 509 connected to the HDD interface 105.
A case will be described in which two video images of the playback stream from the above are simultaneously decoded and displayed by the AV decoder 505.

The switch group 609 is set by the CPU 107 and the switch control register 609 so that the switches 42 and 72 are turned on and the stream input from the input terminal T34 and the stream input from the input terminal T37 are multiplexed and output. . Also, the playback stream from the digital video camera 508 is output to the output port OU.
The IEEE 1394 interface 503 is set to output from T0. In addition, the DVD drive device 50
The HDD interface 105 is set to output the reproduction stream from the output port OUT0.

The reproduction stream from the digital video camera 508 is input to the switch 42 from the output port OUT0 of the IEEE1394 interface 503. On the other hand, the reproduction stream from the DVD drive device 509 is input to the switch 72 from the output port OUT0 of the HDD interface 105. These two streams are multiplexed by the switch group 602 and input to the input port IN0 of the AV decoder 505. The AV decoder 505 decodes each of the two multiplexed streams and displays both images.

By configuring and operating as described above, it is possible to freely connect a plurality of streams with only one stream connection in terms of circuit scale.

[0139]

As described above, according to the stream processing apparatus of the present invention, it is possible to improve the degree of freedom in the configuration of the apparatus having the function of processing a plurality of streams.

[Brief description of drawings]

FIG. 1 is a block diagram showing an overall configuration of a system according to a first embodiment of the present invention.

FIG. 2 is a block diagram showing in detail the configuration of the stream processing device shown in FIG.

FIG. 3A is a diagram illustrating a process of extracting a stream of a desired program from a broadcast stream and accumulating the stream in an AVHDD connected to an IEEE1394 bus. (B) is a diagram for explaining a process of dubbing a program stream from a digital VTR to an external hard disk device. (C) is a figure for demonstrating the process which takes out the program stream from another reception broadcast, and records this in a hard disk unit. (D)
FIG. 6 is a diagram for explaining a case where data broadcast information stored in a hard disk device is taken out, placed in a memory and processed by a CPU.

4A is a diagram for explaining a case where AV reproduction of a broadcast program and a process of accumulating audio data of the program in a memory 106 are performed at the same time. FIG. (B)
[Fig. 6] is a diagram for explaining a case where the same program is recorded in the AV HDD 112 in the transport stream format at the same time as the AV reproduction of the broadcast program stream.

FIG. 5: Extracting the program stream from the received broadcast,
It is a figure for demonstrating the process which cancels | releases the encryption for broadcasting applied to this program stream, further applies the encryption for hard disk recording to this program stream, and records it in a hard disk device.

FIG. 6 is a block diagram showing an overall configuration of a system according to a second embodiment of the present invention.

7 is a block diagram showing in detail the configuration of the stream processing device shown in FIG.

FIG. 8A is a diagram for explaining a process of decoding and reproducing video / audio reproduced from a digital video camera by an AV decoder. (B) is a diagram for explaining a case where demultiplexing processing is performed on a stream received via Ethernet (R) and taken out by the CPU. (C) is a diagram for explaining a process of extracting a program table, deciphering key data, and the like processed by software of the digital TV receiver from the broadcast stream received by the tuner.

FIG. 9 is a block diagram showing a configuration of a switch group according to a third embodiment of the present invention.

FIG. 10 is a timing chart for explaining the operation of the switch group shown in FIG.

FIG. 11 is a timing chart for explaining the operation of the switch group shown in FIG.

[Explanation of symbols]

101,501 Stream processing device, 102,502
Matrix switch, 103, 503 IEEE13
94 interface, 104, 504 demultiplexer, 105 HDD interface, 106 memory,
107 CPU, 108, 505 AV decoder, 11
0,111 tuner, 200-208,600-60
8 switch group, 209, 609 switch control register, 506 DMA circuit, 507 Ethernet (R) interface, 800-807 register, 808 multiplex control circuit, 809 data selection circuit.

─────────────────────────────────────────────────── ─── Continued Front Page (51) Int.Cl. ⁷ Identification Code FI Theme Coat (Reference) G11B 20/12 H04N 5/44 A 5D080 H04N 5/44 5/91 L 5/92 7/08 Z 7 / 08 7/167 Z 7/081 5/92 H 7/167 F term (reference) 5C025 AA28 AA29 BA21 BA25 BA27 BA30 DA01 DA04 DA10 5C053 FA22 FA23 GB38 LA06 LA07 LA15 5C063 AB03 AB07 AC01 AC05 CA12 5C064 CA14 5D044 AB05 AB07 BC01 CC05 DE14 DE43 GK12 GK17 HL11 5D080 BA02 BA03 BA05 DA07 EA01 EA02 FA01

Claims (16)

[Claims] 1. A selection means for associating a plurality of inputs with a plurality of outputs according to control from the outside and for giving a stream given to each of the plurality of inputs to a corresponding output, and a selecting means for selecting a plurality of the plurality of inputs. A first processing means for providing a first stream to one input, a second processing means for providing a second stream to a second input of the plurality of inputs, and a first processing means of the plurality of outputs. A third processing means for receiving a stream from one output, a fourth processing means for receiving a stream from a second output of the plurality of outputs, and a third processing means of a third output of the plurality of outputs. And a fifth processing means for receiving the stream, performing a predetermined process on the received stream, and giving the processed stream to a third input of the plurality of inputs. Story Processing apparatus. 2. The stream processing device according to claim 1, wherein the selection unit associates the plurality of inputs with the plurality of outputs in a one-to-one correspondence. 3. The stream processing device according to claim 1, wherein the selection unit associates one of the plurality of inputs with two of the plurality of outputs. 4. The stream processing device according to claim 2 or 3, wherein the selection unit multiplexes at least two of the plurality of outputs into a new output. 5. The fifth processing means according to claim 1, wherein the fifth processing means extracts desired information from the received stream to generate a partial stream, and the generated partial stream is a third input of the plurality of inputs. A stream processing device characterized by being provided to. 6. The stream processing according to claim 1, wherein at least one of the third processing means and the fourth processing means converts the interface format of the received stream and outputs the converted stream. apparatus. 7. The method according to claim 1, wherein at least one of the first stream and the second stream includes video data and / or audio data, and at least one of the third processing means and the fourth processing means. At least one of them is a stream processing device characterized by decoding video data and / or audio data included in the received stream. 8. The seventh processing means according to claim 7, wherein the fifth processing means extracts desired video data and / or audio data from the received stream, and the extracted video data and / or audio data.
Alternatively, the stream processing device is characterized in that audio data is given to a third input of the plurality of inputs. 9. The method according to claim 1, wherein at least one of the first stream and the second stream is encrypted, and the fifth processing means removes the encryption applied to the received stream. A stream processing device characterized by: 10. The stream processing apparatus according to claim 1, wherein the fifth processing means encrypts the received stream. 11. The method according to claim 1, wherein at least one of the first stream and the second stream is encrypted by a first encryption method, and the fifth processing means applies a call to the received stream. The stream processing device further includes sixth processing means, and the sixth processing means receives and receives a stream from a fourth output of the plurality of outputs. A stream processing device, characterized in that a stream is encrypted by a second encryption method, and the encrypted stream is given to a fourth input of the plurality of inputs. 12. The storage device according to claim 1, further comprising: a storage unit, wherein at least one of the third processing unit and the fourth processing unit writes the received stream in the storage unit. At least one of the means and the second processing means reads a stream from the storage means and supplies the read stream to a corresponding input. 13. The method according to claim 12, wherein at least one of the third processing means and the fourth processing means stores a write position in the storage means of a stream written in the storage means, At least one of the processing means and the second processing means stores the read position in the storage means of the stream read from the storage means. 14. The method according to claim 13, wherein at least one of the first processing means and the second processing means is stored in at least one of the third processing means and the fourth processing means. A stream processing device, wherein a stream is read from the storage means with reference to an existing writing position. 15. The method according to claim 13, wherein at least one of the third processing means and the fourth processing means is stored in at least one of the first processing means and the second processing means. A stream processing apparatus, wherein a stream is written in an area other than an area in which a stream that has not yet been read is stored in the storage unit with reference to a read position. 16. The method according to claim 12, wherein at least one of the first stream and the second stream includes a plurality of packets, and each of the plurality of packets includes identification information for selecting necessity. And the fifth processing means extracts a desired packet from a plurality of packets included in the received stream with reference to the identification information, generates a first partial stream, and outputs the first partial stream. A stream is given to a third input of the plurality of inputs, and at least one of the third processing means and the fourth processing means writes the received first partial stream in the storage means; At least one of the first processing means and the second processing means reads the first partial stream from the storage means and outputs it to the second partial stream. To give the corresponding inputs, it said at least one of the third processing means and said fourth processing means, the stream processing unit and extracts a desired information from the second portion stream received.