JP2003151300A - Semiconductor memory device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor memory device in which a test time is shortened without increasing the number of terminals when a write-in mask function test is performed using a memory test (DMA). SOLUTION: Increment of the number of terminals is suppressed by allotting a mask address signal IDQM[0-7] externally inputted as it is or allotting a decoded mask address signal to address terminals 1A[12-19] accompanied by decreasing of input/output data terminals at a test mode, also, the test time at the test mode is shortened by performing verification of the write-in mask function and making a state in which the mask function is not used simultaneously.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device,
In particular, the present invention relates to a test of a write mask function in a memory having a data write mask function, and particularly to a test of a built-in memory incorporated in an LSI.

[0002]

2. Description of the Related Art In recent years, the increase in the scale of LSIs and the complication of built-in functions have been remarkable, and the speeding up of processing and the amount of memory embedded in LSIs have increased regardless of type. The capacity of the memory and the number of its input / output terminals continue to increase as the processing speed increases. At the same time, the importance of testing on the operation of LSI, technical difficulty, test circuit and test time increase. With the increase in the number of input / output terminals, it is necessary to partially mask the input / output terminals for writing in the processing of the LSI. On the other hand, in the memory test, the DMA (Direc
The number of input / output terminals is reduced by using a means such as t Memory Access), and the reduced input / output is decoded by an address to perform the test.

[0003]

Therefore, when the write mask function is tested by using the memory test (DMA), the mask function is simultaneously performed with the increase in the number of address terminals corresponding to the decrease in the number of input / output terminals. Therefore, the increase in the number of terminals cannot be ignored. Also,
In addition to being unable to fully perform the test in the actual use state, it results in an increase in test time.

The present invention has been made in view of the above problems, and an object thereof is to perform a test of a write mask function using a memory test (DMA) without increasing the number of terminals and a test time. Another object of the present invention is to provide a semiconductor memory device in which

[0005]

In order to achieve the above object, a semiconductor memory device according to the present invention has a mask function for masking write data by using a mask address signal as an input, and a data input / output in a test mode. A semiconductor memory device in which the number of terminals and the number of address input terminals are variable, wherein a mask address input terminal or a mask address signal of the semiconductor memory device is provided in response to a decrease in data input / output terminals in a test mode. The signal is the same as or corresponding to the address input terminal at the time.

According to this structure, the mask address for masking the write data becomes the address in the test mode as it is. Therefore, the write operation having the mask function in the actual use state is the same as the write operation in the test mode. Therefore, it is not necessary to prepare another write mask function test in the actual use state, and it is not necessary to increase the address input for that purpose.

In the semiconductor memory device according to the present invention, the mask address signal input in the test mode and the semiconductor memory device already exist to write the data from the selected data input terminal to the memory cell array at the time of data writing. A write selection signal generation circuit that generates a write selection signal based on a normal address signal from an address input terminal, and an output terminal that is selected by a mask address signal and a normal address signal when reading data, and outputs the data to the outside. And an output circuit.

According to this structure, the address at the time of writing and the address at the time of reading can be matched, and the number of input / output terminals in the memory test can be reduced.

Further, in the semiconductor memory device according to the present invention, the mask address input terminal is used as the address input terminal in the test mode provided corresponding to the decrease of the data input / output terminals in the test mode. Instead of all the mask address signals input in the mode, a mask address decode signal generated by decoding a required number of bits of the mask address signal is selected based on the first test mode activation signal, It is preferable to include a first mask address signal decoding circuit for outputting as a column address.

According to this structure, when the write mask address signal input from the outside is used as it is as the address input signal in the memory test, the mask address signal in the actual use state is not already decoded, In addition, when the signal specifies a mask when writing, there is no difference between the read address and the write address in the memory test, and especially when the number of mask addresses in actual use is large, There is a reduction effect.

In the semiconductor memory device according to the present invention, the mask address input terminal is used as the address input terminal in the test mode which is provided in response to the decrease of the data input / output terminals in the test mode. Instead of all the mask address signals that are sometimes input, a mask address decode signal generated by decoding a required number of bits of the mask address signal is used as a first test mode activation signal and an externally or internally generated signal. It is preferable to include a second mask address signal decoding circuit which selects based on the second test mode activation signal generated by the command signal and outputs as a column address.

According to this structure, it is possible to select and use all the inputted mask address signals and mask address decode signals according to the purpose of the memory test.

In the semiconductor device according to the present invention,
It is preferable that all the mask address signals in the test mode be activated through the write selection signal generating circuit to collectively write data to the memory cell array. In this case, the second mask address signal decoding circuit It is preferable to have a collective data writing means.

With this configuration, the write operation similar to that in the actual use state can be performed, and particularly in the large-capacity memory, the high-speed write operation can be performed in the test mode.

[0015]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing a configuration example of a semiconductor memory device according to an embodiment of the present invention. In order to simplify the description and keep the specificity, the actual use state of the memory device and the configuration at the time of testing are illustrated as in FIG.

In FIG. 1, 1 is a memory cell array, 2 is
Is an input register, 3 is a row decoder, 4 is a column decoder, 5 is a sense amplifier, 6 is a multiplexer, 7 is an output register, and 8 is a clock generator.

In actual use, DIN [0-127] is 128-bit input data, DOUT [0-127] is 128-bit output data, and DQM [0-7] is 16-bit.
Of the 8-bit mask address signal and the 16-bit address signal A [0-15] that mask the input data DIN [0-127] in bit units, 12-bit A [0-
11] is a row address signal, 4-bit A [12-1
5] becomes a column address signal.

On the other hand, in the test mode, the PDI
N [0-1] is 2-bit input data, PDOUT [0
-1] is 2-bit output data, PDQM [0-7] is 8-bit mask address signal, and 16-bit address signal PA [0-15] out of 12-bit PA [0-].
11] is a row address signal and 8-bit PA [12-1
9] becomes a column address signal.

Here, in the test mode, input data PDIN [0-1] and output data PDOUT [0-
1] is 2 bits each, input data D that can be decoded by DQM [0-7] in actual use.
While the bit number of IN [0-127] and DOUT [0-127] is 16 bits, the column address signal PA [12-19] is increased by 4 bits to enable decoding.

FIG. 2 is a circuit diagram showing a structure of the data input circuit 21 in the input register 2 in the semiconductor memory device of FIG.

The data input DIN [0-127], which is 128 bits in the actual use state, becomes the 2-bit data input PDIN [0-1] in the test mode, and the number of data inputs is reduced, so that it is shown in FIG. DIN [0-63]
Indicates that the test mode activation signal PTEST has a logic High
If it is a level, it is input as PDIN [0].
Therefore, the input data DIN [0-63] is PD
The same data as IN [0] is input, and the same data as PDIN [1] is input as the input data DIN [64-127]. When the test mode activating signal PTEST is at the logic high level, this is as shown in FIG. 3, but the column address signal PA [16-19] to be input to the address input circuit 22, which will be described later, and the mask input, which will be described later. According to the mask address signal PDQM [0-7] input to the circuit 23, the memory cell array 1
The selected position is supplied to the memory cell array 1. The position of the data from the memory cell array is selected by the same column address signal PA [16-19] and mask address signal PDQM [0-7], and is output as output data to the outside of the memory.

FIG. 3 is a circuit diagram showing configurations of the address input circuit 22 and the mask address signal input circuit 23 in the input register 2 in the semiconductor memory device of FIG. In FIG. 3, when the test mode activation signal PTEST is at the logic high level, the mask address signal DQ
M [0-7] has its internal signal transition stopped by the NAND circuit 230, and the NAND circuit 231 outputs PD.
QM [0-7] is supplied internally. Therefore, the mask address signal PDQM [0
-7] is supplied as the internal mask address signal IDQM [0-7]. This internal mask address signal IDQM
[0-7] is used as a signal for selecting the input data DIN [0-127] and the output data DOUT [0-127]. The column address signal PA [12-19] is similarly supplied as the internal column address signal IA [12-19], but since 16-bit data is selected, the column address signal PA [12-19] is set in the test mode. It is supplied to the corresponding terminal as a signal to be used only.

FIG. 4 is a circuit diagram showing a structure of the output circuit 71 in the output register 7 in the semiconductor memory device of FIG.

In FIG. 4, the output data DOUT [0-63] in the actual use state is the test mode activation signal PT.
When EST is at the logic high level, the internal column address signal IA [16- shown in FIG. 6 is generated by the internal mask address signal IDQM [0-7] shown in FIG. 3 and the address decode circuit 10 shown in FIG. 7 and described later. 19] and an internal column address signal IAD [0-15] decoded to be output. DO [0-63] is data read inside the memory. Test mode activation signal PTEST, internal mask address signal IDQM
[0] and internal column address decode signal IAD
When [0] is at the logic high level, the read data DO [0] in the test mode is output from the output circuit unit 710, and the output terminal outputs the output circuit unit 711 commonly connected to the output circuit unit 710. Impedance is Hi
The gh impedance state is set. Similarly, the test mode activation signal PTEST and the internal mask address signal IDQ
M [7] and internal column address decode signal IA
When D [15] is at the logic High level, read data DO [63] is output from the output circuit unit 711, and the output impedance of the output circuit unit 710 whose output terminal is commonly connected to the output circuit unit 711 is High. It becomes possible to select without entering a new address in the impedance state.

FIG. 5 is a circuit diagram showing a structure of write select signal generating circuit 41 in column decoder 4 in the semiconductor memory device of FIG. In FIG. 5, the write selection signal generation circuit 41 uses the internal column address decode signal I
AD [0-15] and internal mask address signal IDQM
It is a circuit that generates a write selection signal Y [0-127] by taking a logical product with [0-7]. The write selection signal generation circuit 41 causes the input data DIN [0-
Write selection signal Y [0] necessary for selecting [127].
-127] is the internal mask address signal IDQM [0-
7]. Internal mask address signal IDQ
When M [0] is at the logic high level, one of the internal column address decode signals IAD [0-15] becomes the logic high level, and thereby selected from the input data DIN [0-7]. The data thus written is written in the memory cell array 1.

FIG. 6 is an address decode signal generation circuit 42 in the column decoder 4 in the semiconductor memory device of FIG.
3 is a circuit diagram showing the configuration of FIG. In FIG. 6, from the internal column address signal IA [16-19], the inverter circuit 420 generates the inverted internal column address signal IA [16-19] X which is an inverted signal of each. In the NAND circuit 421 provided for decoding, the internal column address signal IA [16-19] and the inverted internal column address signal IA are input to the NAND circuit 421 according to the combination as the selection signal.
[16-19] X is input and decoded, and internal column address decode signals IAD [0-15] are generated. This internal column address decode signal IAD
[0-15] is input to the output circuit 71 shown in FIG.
It functions as a selection signal, and the read data DO [0-12
7] selected data is output data (DOUT)
Is output to the outside of the memory. Further, the internal column address decode signal IAD [0-15] is input to the write selection signal generation circuit 41 shown in FIG. 5 and functions as a selection signal, and the selected data of the input data DIN [0-127] is It is written in the memory cell array 1.

FIG. 7 is a circuit diagram showing a structure of mask address signal decoding circuit 10 added to the semiconductor memory device of FIG. Depending on the number of mask bits in actual use and the number of built-in input data lines and output data lines, it is necessary to reduce the number of mask address signal lines due to equipment restrictions such as a memory tester. . Therefore, as shown in FIG. 7, inside the memory device,
It is necessary to decode the necessary number of internal mask address signals IDQM and supply them to the above-mentioned write selection signal generation circuit 41.

The inverter array 100 of FIG. 7 has an internal mask address signal IDQM [0-
7], a required number, for example, 3-bit internal mask address signal IDQM [0-2] X is inverted to generate an internal mask address signal IDQM [0-2] X. By inputting the inverted internal mask address signal IDQM [0-2] X and the internal mask address signal IDQM [0-2] in a predetermined combination into the NAND circuit 101 and using the output signal of the NAND circuit as a selection signal, Inside the memory,
8-bit internal mask decode signal IDQMD [0-
7] can be generated, and the test mode activation signal P
When TEST is at a logic high level, it can be supplied internally as the internal mask decode signal IDQMD [0-7]. In addition, the test mode activation signal PT
When the EST is at the logic low level, the internal mask address signal IDQM [0-7] is supplied as it is to the inside as a signal of the same phase.

FIG. 8 is a circuit diagram showing a modification of the mask address signal decoding circuit of FIG. 8 is different from FIG. 7 in that the test mode activation signal PTEST2
Is generated by the test mode activation signal PTEST and an externally or internally generated command signal and supplied to the mask address signal decoding circuit 11.
When the test mode activation signal PTEST2 is at the logic low level, the internal mask address signal IDQM [0-
7] is directly supplied to the inside of the memory and the test mode activation signal PTEST2 is at the logic high level,
The signal obtained by decoding the internal mask address signal IDQM [0-2] is the internal mask decode signal IDQM.
It is supplied to the inside of the memory as D [0-7]. In the actual use state, the test mode activation signal PTEST is set to the logic low level, and the test mode activation signal PTEST2 is set.
To a logic high level.

FIG. 9 is a circuit diagram showing a further modification of the DQM signal decoding circuit of FIG. 9 is different from FIG. 7 in that the test mode activation signal PTEST2 is
A 2-input NAND in the final stage that outputs the internal mask decode signal IDQMD [0-7] from the point generated from the test mode activation signal PTEST by an external or internal command signal and supplied to the mask address signal decode circuit 11. The circuit is a 3-input NAND circuit, and the signal AWT is supplied to one input terminal of the 3-input NAND circuit.

When the signal AWT is set to the logic Low level, all the IDQMD [0-7] are set to the logic High level in the active state. On the other hand, the signal AWT is logic high.
At the h level, and the test mode activation signal PTEST2
Is a logic high level, a signal obtained by decoding the internal mask address signal IDQM [0-2] is supplied to the inside of the memory as an internal mask decode signal IDQMD [0-7]. As a result, by setting the signal AWT to the logic low level, the write operation similar to that in the actual use state can be performed, and particularly in the large capacity memory, the high speed write operation can be performed in the test mode. .

[0032]

As described above, according to the present invention, when the write mask function is tested by using the memory test (DMA), the number of address terminals corresponding to the decrease in the number of input / output terminals is increased. , Without increasing the number of terminals,
Further, it is possible to sufficiently carry out a test in actual use of the mask function. Further, by performing writing in a form close to the actual use state, it is possible to improve the quality level and shorten the test time.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration example of a semiconductor memory device according to an embodiment of the present invention.

2 is a circuit diagram showing a configuration of a data input circuit 21 in an input register 2 in the semiconductor memory device of FIG.

3 is a circuit diagram showing a configuration of an address input circuit 22 and a mask address signal input circuit 23 in the input register 2 in the semiconductor memory device of FIG.

4 is a circuit diagram showing a configuration of an output circuit 71 in an output register 7 in the semiconductor memory device of FIG.

5 is a circuit diagram showing a configuration of a write selection signal generation circuit 41 in a column decoder 4 in the semiconductor memory device of FIG.

6 is a circuit diagram showing a configuration of an address decode signal generation circuit 42 in a column decoder 4 in the semiconductor memory device of FIG.

7 is a circuit diagram showing a configuration of a mask address signal decoding circuit added to the semiconductor memory device of FIG.

8 is a circuit diagram showing a modification of the mask address signal decoding circuit of FIG.

FIG. 9 is a circuit diagram showing a further modification of the mask address signal decoding circuit of FIG.

[Explanation of symbols]

1 memory cell array 2 input registers 21 Data input circuit 22 Address input circuit 23 Mask address signal input circuit 3 Row decoder 4 column decoder 41 Write Selection Signal Generation Circuit 42 Address decode circuit 5 sense amplifier 6 multiplexer 7 Output register 71 Output circuit 8 clock generator 10, 11, 12 Mask address signal decoding circuit

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Claims (6)

[Claims] 1. A semiconductor memory device having a mask function of masking write data by inputting a mask address signal and varying the number of data input / output terminals and the number of address input terminals in a test mode. The mask address input terminal or the mask address signal is the same as or corresponding to the address input terminal in the test mode provided corresponding to the decrease of the data input / output terminals in the test mode. Semiconductor memory device. 2. The semiconductor memory device according to claim 1, wherein the mask address signal input in a test mode and the semiconductor memory device are already present in order to write data from a selected data input terminal to a memory cell array during data writing. A write selection signal generation circuit that generates a write selection signal based on a normal address signal from an address input terminal that the device has, and an external output terminal that outputs data from the output terminal selected by the mask address signal and the normal address signal when reading data. 2. The semiconductor memory device according to claim 1, further comprising an output circuit for outputting to. 3. The semiconductor memory device according to claim 1, wherein the mask address input terminal is used as the address input terminal in a test mode provided corresponding to a decrease in the data input / output terminals in a test mode. A mask address decode signal generated by decoding a required number of bits of the mask address signal is selected instead of all the mask address signals that are sometimes input, based on the first test mode activation signal. 2. A first mask address signal decoding circuit for outputting as a column address is provided.
The semiconductor memory device described. 4. The semiconductor memory device according to claim 1, wherein the mask address input terminal is used as the address input terminal in a test mode provided corresponding to a decrease in the data input / output terminals in a test mode. A mask address decode signal generated by decoding a required number of bits of the mask address signal instead of all of the mask address signals that are input at any one time is used as an external or internal signal for the first test mode activation signal. 2. The semiconductor device according to claim 1, further comprising a second mask address signal decoding circuit which selects based on a second test mode activation signal generated by the generated command signal and outputs as a column address. Storage device. 5. The data writing to the memory cell array is collectively performed by activating all the mask address signals in the test mode via the write selection signal generating circuit. The semiconductor memory device described. 6. The second mask address signal decode circuit has means for collectively writing data to the memory cell array by activating all the mask address signals in a test mode. The semiconductor memory device according to claim 3.