JP2003151292A - Data shift circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a redundancy multiplexer circuit technique with improved integrated circuit area efficiency, in which complexity of a circuit, die area necessary to support a complementary control signal in a memory device IC and redundant elements, and undesired parasitic capacitance are reduced. SOLUTION: Redundancy multiplexer circuit technique with an improved integrated circuit area efficiency provides similar functionality to conventional CMOS transmission, or 'pass' gates while concomitantly reducing circuit complexity, the die area necessary to support the redundant elements and the complementary control signals in the memory devices ICs and undesired parasitic capacitance. This technique is achieved by utilizing the on-chip boosted voltage level (Vpp ) to supply the voltage for the control signal applied to a single N- channel transistor pass gate. Higher throughput speeds in the address and data paths can be obtained by the significant reduction in undesired parasitic capacitance.

Description

Detailed Description of the Invention

RELATED APPLICATION This application is assigned to the assignee of this invention, United Springs, Colorado, United Memories Inc. and Sony Corporation, Shinagawa-ku, Tokyo, Japan. No. 09 / 648,845, filed Aug. 25, 2000, the disclosure of which is specifically incorporated herein by reference.

[0002]

BACKGROUND OF THE INVENTION The present invention generally relates to integrated circuits (I
C) Relating to the field of devices. More specifically, the present invention provides an improved integrated circuit area that provides a significantly reduced parasitic capacitance that is particularly applicable for use in integrated circuit memory devices and other semiconductor devices incorporating embedded memory elements. The present invention relates to efficient redundant multiplexer circuit technology.

Current integrated circuit memory redundancy technology uses a number of conventional complementary metal oxide semiconductor (CMOS) transmissions or "passes" for each repairable element.
Gates are often used, and each such passgate includes parallel-coupled N-channel and P-channel transistors controlled by complementary gate control signals. Functionally, these pass gates serve to read / write redundant circuit elements.
Often used to shift write data and addresses.

For example, the address paths of normal and spare row and column elements (as well as the data flow of data paths) can be directed by the use of pass gate logic. In a conventional CMOS implementation of a passgate,
Instead, the input signal can be propagated without the threshold voltage (V _t ) drop in signal level as would occur with only a single N-channel or P-channel transistor. In the former example, the N-channel device leads a drop of V _{t to} a logic "1" signal level, and in the latter case, the P-channel device to a logic "0" signal level V _t.
guide the descent of _t .

Although CMOS passgate designs have traditionally been well suited for these purposes, the layout of such circuits nevertheless consumes undesirably large integrated circuit die (on-chip) area and is complementary control. The need for signal generation, routing, and other attendant requirements adds attendant circuit complexity. This additional die space and layout complexity adds to the cost and design time of the device while also presenting a significant amount of parasitic capacitance, which slows down the address and data paths. Moreover, while previously using single-device passgate circuit technology, their use is typically in applications where the voltage drop across the conducting transistor is inconclusive or can be boosted through subsequent amplification steps. Was limited to. Moreover, single device pass gates have never been used in conjunction with shift redundancy techniques.

[0006]

SUMMARY OF THE INVENTION The improved integrated circuit area efficient redundant multiplexer circuit technology of the present invention disclosed herein advantageously provides similar functionality to conventional CMOS transmission or "pass" gates. While offering
At the same time, it reduces the circuit complexity, the die area required to support the redundant elements in the memory device IC, and results in a significantly reduced parasitic capacitance. The technology of this invention is
This objective is achieved by using an on-chip boosted voltage level (V _pp ) commonly available in such devices, while the significant reduction in the unwanted parasitic capacitance provided results in address and data Higher throughput rates on the path are possible.

In the particular embodiment of the invention disclosed herein, a single N-channel pass transistor uses a V _pp voltage level (which is boosted above the normal power supply voltage level V _cc ). The voltage of the control signal applied to the gate of the N-channel transistor. At this time, the voltage level V _pp and the circuit ground (GND) are used as signal levels of logic “high” and “low”, respectively. After activation of the device, these control signals operate at a direct current (DC) level to enable this use. Once the integrated circuit device is powered up and stable (and after redundancy is programmed), the signal level at the N-channel passgate stabilizes.

The integrated circuit device specifically disclosed herein has a power supply voltage level applied thereto with respect to a reference voltage level and a boosted voltage level greater than the power supply voltage level. The device includes a redundant multiplexer circuit that includes a plurality of switching devices, each of the switching devices being coupled between a respective input signal line and a common output signal line. A plurality of control signal lines are also provided, each of the control signal lines being coupled to the corresponding control terminal of the switching device. A switching device operates in response to a control signal applied to its control terminal at a boosted voltage level, and transfers an input signal on a corresponding input signal line to an output signal line without a drop in threshold voltage across it. .

With reference to the following description of the preferred embodiments in connection with the accompanying drawings, the foregoing and other features and objects of the invention and the manner in which they are achieved will become more apparent, and the invention itself will be best understood. It will be well understood.

[0010]

DESCRIPTION OF EXEMPLARY EMBODIMENTS Referring to FIG. 1, a conventional integration.
Gate level circuit redundancy multiplexer circuit 10
A schematic diagram is shown. The circuit 10 includes a large number of CMOS transformers.
Mission or "pass" gate 12₀From 12₂Including
, Each of which is a pair of parallel-coupled N-channel
Including a transistor 14 and a P-channel transistor 16.
Mu. On-chip required by the active device itself
In addition to the area, complementary control signals
Two₀From 12₂Each N-channel transistor 14 and
And routing to the gate of P-channel transistor 16
Must. For example, the signal SR (shift right)
Gate control line 22₀Must be given to its complement
SRB (SR "bar" (/ SR))
Line 24₀Must be given to. Similarly, the signal NS
Gate control line 22 (without shift)₁Must be given to
, And its complementary NSB (NS "bar" (/ N
S)) to the gate control line 24 ₁Must be given to.
On the other hand, the signal SL (shift left) is applied to the gate control line 22.₂To
And its complementary SLB (SL "
-"(/ SL)) to the gate control line 24₂Must be given to
I won't.

[0011] Thus, depending on the state of the complementary control signal applied to the gate control line 22 ₀ -22 ₂ and 24 ₀ -24 _2, the respective signals DRP on input lines 18 ₀ to 18 ₂
The selected one of <0>, DRP <1> or DRP <2> will be transmitted to the output line 20 (DR).

Functionally, the N-channel transistor 14
Gate voltage of logic level "0" (or circuit ground GN
D), the complementary gate voltage for the corresponding P-channel transistor 16 is at logic level "1" (or power supply voltage level VCC) and both N-channel and P-channel transistors 14 and 16 are non-conductive. . Alternatively, if the gate voltage of N-channel transistor 14 is at logic level "1" and the corresponding gate voltage of P-channel transistor 16 is at complementary logic level "0", then both transistors are conductive.

In those instances where the gate voltage for N-channel transistor 14 is at or near the power supply voltage level V _cc, there is a threshold voltage drop V _t across N-channel transistor 14, but P-channel transistor 16 is present. There is virtually no voltage drop across. On the other hand, if the gate voltage is close to GND, the N-channel transistor 14 hardly exhibits a voltage drop. In other words, N-channel transistor 14 operates to conduct a logic level "0" with little voltage drop, but typically _conducts a drop in V _t to logic level "1". That is, there is a need for a parallel-coupled P-channel transistor 16 that guides the latter logic level with little voltage drop.

In the particular embodiment of circuit 10 shown, N
Channel transistor 14 may have a channel width of 1.0μ and P-channel transistor 16 may have a corresponding channel width of 2.0μ.

Still referring to FIG. 2, an integrated circuit area efficient multiplexer circuit 30 according to an embodiment of the present invention.
A schematic diagram at the corresponding gate level of is shown. In the particular implementation shown, the circuit 30 includes a plurality of pass gates 3.
2 ₀ 32 ₂ incorporated but, depending on the design of the integrated circuit device, any number "n" of such a pass gate 3
2 may be included. Each of the pass gates 32 ₀ to 32 ₂ includes only a single N-channel transistor 34, which allows the on-chip area and layout and complementary required for the corresponding P-channel device, as in conventional circuit 10 (FIG. 1). Eliminates the need for control signal routing.
The single device pass gates 32 ₀ to 32 ₂ also provide much improved parasitic capacitance characteristics over conventional circuit 10, as will be described more fully below.

Each of pass gates 32 ₀ to 32 ₂ has a single gate terminal coupled to a corresponding control line 40 ₀ to 40 ₂ (labeled SL, NS and SR, respectively). When one of the control lines 40 ₀ to 40 ₂ is activated at the level of V _pp (boosted above the power supply voltage level V _cc ), the input signals on the input lines 36 ₀ to 36 ₂ (respectively DRP < One of the correspondence from 0> to DRP <2>)
It is delivered to output line 38 (DR) without a voltage drop of V _t across N-channel transistor 34. In the embodiment of circuit 30 shown, N-channel transistor 34 has a substantially 1.0 μ channel width and a substantially 0.34 μ channel width.
May have corresponding channel lengths. Typically, the voltage level of the boosted voltage level V _pp will be substantially 1.5 to 2.2 times the power supply voltage level V _cc . In the implementation of circuit 30 shown, V _cc is nominally 1.5V and V _cc is
_pp is about 3.3V.

Generally, for proper operation of the circuit 30,
Is V_ppIs V_ccAbove or above the level of "board
"Body effected" V_tMust be
Yes. DRAM or other device with embedded memory
A typical implementation of the invention in connection with which memory device
In the example, V_ppLevels meet this criterion. Because V
_ppThe main function of the full logic level "1", single N
Only channel pass gate transistors are typically used
Used by word lines so that they can be stored in a given memory cell
This is because it provides a power supply that is high enough to operate.

Although the actual on-chip area reduction provided by the circuit 30 of the present invention may appear relatively small compared to the conventional circuit 10 (FIG. 1), the actual reduction in die area is due to the memory array density. , Depends on several factors including the amount of redundancy used and the total input / output (I / O) width.

Nevertheless, the circuit 30 provides a significant improvement in undesired parasitic capacitance over the conventional circuit 10 (FIG. 1). Particularly for the circuit 10 of FIG.
It can be seen that 0 (DR) encounters all of the gate capacitances of the "on" N-channel transistor 14 and P-channel transistor 16 for each selected path of pass gates 12 ₀ to 12 ₂ . For example, if no shift is selected, the signal NS on line 22 ₁ is "high" and the signal NSB on line 24 ₁ is "low". On the other hand, the line 22 ₀
Signals SR and SL on 22 and 22 ₂ are "low" and signals SRB and SLB on lines 24 ₀ and 24 ₂ are "high". In this example, DRP <1> signal on output node 20 and input line 18 _1, and the full gate capacitance of N-channel transistor 14 and P-channel transistor 16 of the pass gate 12 _1, both transistors of pass gates 12 ₀ and 12 ₂ It is necessary to drive the junction capacitance of and.

The circuit 30 eliminates the need for parallel-coupled P-channel transistors altogether, thereby eliminating their gate and source / drain capacitances altogether. This drives more than half the capacitance of circuit 10, since P-channel transistors are typically sized with a gate width twice the size of N-channel transistors due to their channel mobility. It is necessary to reduce the capacity. In comparison with the previous _one , the signal NS on input line 40 ₁ is at VPP (logic “high”) and the signals SL and SR on input lines 40 ₀ and 40 ₂ are both logic “low” level or It is in GND. In this example, the signal DRP <1> on the input line 36 ₁ and the DR on the output line 38 are then determined by the gate capacitance of the N-channel transistor 34 of the pass gate 32 ₁ and the pass gate 3 1.
It only needs to drive the source / drain capacitances of the N ₀ -channel transistors 34 of ₂₀ and 32 ₂ .

Referring generally to FIGS. 3-10, self-correcting memory 100 includes a memory array 106 including rows and columns of DRAMs or other memory cells, sense amplifier column 1.
12, error correction data shifter or shift redundancy circuit 1
08, output buffer circuit 110, fuse block 10
2 as well as boost logic block 104.
Other conventional circuit elements such as those known to those skilled in the art of memory design are not shown in FIG. 3, such as row and column decoders and other data control circuits. Data bus 114
Carries the raw, uncorrected data and one or more spare bits to shift redundancy circuit 108. The corrected output data is carried to the output buffer circuit 110 via the bus 116. Data is buffered and provided to external pins via data bus 118.
The fuse block 102 is used to program the data pattern carried to the logic block 104 via the bus 120. The boosted and decoded data pattern is, as described in more detail below,
It is carried to the shift redundancy circuit 108 via the left shift bus 126, the unshifted bus 124 and the right shift bus 122.

The shift redundancy circuit 108 may also be referred to as an "error correction circuit" or "data shifter" or "data shift circuit". The operation of shift redundancy circuit 108 is such that the output data is partially shifted to the right by one bit for a portion of the output data word, or partially shifted to the left for a portion of the output data word by one bit. It differs from conventional shift register circuits in that it may be shifted or not shifted at all for a portion of the data word, or any combination thereof. Also, as described in more detail below, the gate of the N-channel transistor used to fabricate the shift redundancy circuit 108 has a boosted VCC.
Driven to the + control voltage, the voltage loss between the input and output of shift redundancy circuit 108 is essentially minimized to 0V.

Referring now to FIG. 4, shift redundancy circuit 1
08 includes a series of interconnected multiplexers 136 and 138, each having an input coupled to the shift redundancy circuit input, at least one output coupled to the shift redundancy circuit output, and a programmed boosted DC control. And at least one control terminal for receiving a voltage. The control voltage input is not shown in FIG. 4, but will be described in detail below. Only the first six multiplexers are shown and labeled in order. Any number required by the input data word may be used. The input of shift redundancy circuit 108 is shown for reading an input data word having N bits. Individual input bits are DRP <1> to DR
Labeled P <6>. Other input bits up to a total of N input bits, N multiplexers and N sets of output connections are not shown in FIG. 4, but up to the desired total number N,
It is constructed according to the pattern shown in FIG. Two "spare bits" are also provided to replace data that may be lost in a damaged row of the memory array, but only the first spare bit input DRP SPARE1 is shown. The second spare bit is associated with the last multiplexer in the series, as described in more detail below. The first multiplexer 136 has two inputs for receiving input data and a first spare bit. All other multiplexers 138 each have a single input for receiving a single data input bit. The first multiplexer 136 and the last multiplexer 140 (not shown in FIG. 4) each have two outputs. All other multiplexers 138 each have three outputs and are "left shifted" as illustrated in FIG.
<N-1>, “No shift” <N> and “Right shift”
The <N + 1> output is coupled to the adjacent multiplexer 138.

Referring to FIG. 5, each nth multiplexer 138 in the series has an input 141 for receiving the nth data bit, a first for providing the (n-1) th data bit. Output 142, a second output 144 for providing the nth data bit, a third output 146 for providing the (n + 1) th data bit, a first control terminal 152 for receiving a right shift control voltage. , A second control terminal 150 for receiving an unshifted control voltage and a third control terminal 1 for receiving a left shift control voltage
Including 48. As will be described in more detail below, the control voltage is a boosted DC voltage that is boosted to a voltage greater than the memory power supply voltage and is programmed according to a preset pattern if desired to route the input signal to an appropriate output terminal. And correct possible memory row or bit errors.

Referring to FIG. 6, multiplexer 138
Is a first transistor 158 having a current path coupled between the input 141 and the first output 142 and a gate coupled to the first control terminal 152, and an input 141 and a second output 144. A second transistor 156 having a current path coupled between it and a gate coupled to the second control terminal 150, an input 140 and a third output 146.
A current path coupled to and a third control terminal 14
Third transistor 15 having a gate coupled to 8
4 and are further included. Each of the first, second and third transistors 158, 156 and 154 is an N-channel transistor. Since the DC gate voltage is boosted above the standard power supply voltage, the voltage drop across each of the transistors is minimized, essentially equal to a 0V drop.

Referring to FIG. 7, multiplexer 136
Is a first input 16 for receiving a first data bit
2 and a second input 1 for receiving the spare data bit
60, a first output 164 for providing DR <1> data bits, and a second output 166 for providing DR <2> data bits. The multiplexer 136 is
A first control terminal 174 for receiving a first right shift control voltage, a second control terminal 172 for receiving a non-shift control voltage, and a third control for receiving a second right shift control voltage. Including the terminal 170, the spare bit is shifted as necessary.

Referring to FIG. 8, multiplexer 136
Is a first transistor 168 having a current path coupled between the second input 160 and the first output 164 and a gate coupled to the first control terminal 174; A second transistor 178 having a current path coupled to the first output 164 and a gate coupled to the second control terminal 172; and a first input 162.
Third having a current path coupled between the second output 166 and the second output 166 and a gate coupled to the third control terminal 170.
And the transistor 176 of FIG. Each of the first, second and third transistors 168, 178 and 176 is an N-channel transistor.

Referring to FIG. 9, the last multiplexer 140 in the series of multiplexers has a first input 180 for receiving the last data bit DRP <N> and a spare data bit DRP SPARE2. The second input 182 and the penultimate data bit D
A first output 184 for providing R <N-1> and a second output 1 for providing the last data bit DR <N>
86 and. The multiplexer 140 has a first control terminal 192 for receiving a first left shift control voltage and a second control terminal 190 for receiving an unshifted control voltage.
And a third control terminal 188 for receiving a second left shift control voltage.

Referring to FIG. 10, multiplexer 140
Is a first transistor 198 having a current path coupled between the first input 180 and the first output 184 and a gate coupled to the first control terminal 192; A second transistor 196 having a current path coupled to the second output 186 and a gate coupled to the second control terminal 190, and a second input 182.
Third having a current path coupled between the second output 186 and the third control terminal 188 and a gate coupled to the third control terminal 188.
Further included in the transistor 194. The first, second and third transistors 198, 196 and 194 are N
It is a channel transistor.

Like the intermediate multiplexer 138, the first multiplexer
Multiplexer 136 and last multiplexer 1
Both 40, as will be explained in more detail below,
It received a boosted and programmed DC control voltage to shift left or right or not shift.

Returning to FIG. 3 again, the shift redundancy circuit 108
Includes a number of programmed fuses for generating a predetermined data pattern through logic block 104 for boosting the data pattern and converting it to left shift, no shift and right shift control voltages. It is coupled to the fuse block 102. Fuse block 1
02 includes a number of fuses that are programmed during the initial test phase and opened and closed as is known in the art to create the initial data pattern transferred on bus 120. The fuse block 102 is 3.3V or 5V
Or a first power terminal 128 for receiving an unboosted power supply voltage, such as another standard power supply voltage level,
Powered through a second power terminal 130, which is coupled to ground. Logic block 104 spans the data pattern on bus 120 to the desired predetermined left-shifted data pattern on bus 126, the desired predetermined unshifted data pattern on bus 124, and bus 1
It also includes conventional CMOS or other digital circuitry to logically convert to the desired right shift data pattern on 22. Logic block 104 includes a first power terminal 132 for receiving a boosted power supply voltage greater than the unboosted VCC power supply voltage, and a second power terminal 134 coupled to ground. The logic gates or transistors in logic block 104 are boosted to VCC.
The DC control voltage thus powered by the + power supply voltage and ground and thus boosted is thus supplied to the shift redundancy circuit 108. Finally, shift redundancy circuit output bus 1
Buffered and error corrected data output bus 11 using output buffer 110 to buffer 16
Offer eight.

In operation, at the wafer level test, the memory wafer is read and any memory errors are stored in registers. The fuses in fuse block 102 are either blown or metal mask programmed or otherwise programmed as is known in the art. The wafer is then further environmental and performance tested and then packaged and shipped to the customer as usual.

While the principles of the invention have been described with reference to particular device types, dimensions and circuit implementations, the foregoing description is for purposes of illustration and limits the scope of the invention. Please understand clearly that this is not the case. In particular, it will be appreciated that the teachings of the above disclosure will suggest other modifications to those skilled in the art. Such modifications are known per se and may include other features used in place of or in addition to the features already described herein. In this application, the claims are made for a particular combination of features, but the scope of the disclosure herein is likely to be novel to one of ordinary skill in the art or novel features, either explicitly or implicitly disclosed. Whether it pertains to the same invention as claimed in any claim, including any combination of features or generalizations or modifications thereof, and any or all of the technical problems faced by this invention. It should be understood that it does or does not alleviate. The applicant hereby reserves the right to make new claims for such features and / or combinations of such features during the prosecution process of this application or of all further applications arising therefrom. Is.

[Brief description of drawings]

FIG. 1 is a gate-level schematic diagram of a conventional integrated circuit redundant multiplexer circuit.

FIG. 2 is a schematic diagram at a corresponding gate level of an integrated circuit area efficient multiplexer circuit according to an embodiment of the present invention.

FIG. 3 is a block diagram of a self-correction memory circuit including a memory array, a data correction shift redundancy circuit, an output buffer circuit, a fuse block and a boost logic block according to the present invention.

4 is a block diagram of the shift redundancy circuit of FIG. 3 with one or two inputs for receiving uncorrected raw data or raw data and spare bits and shifted or unshifted data. Give
FIG. 6 shows a series of interconnected multiplexers according to the invention, each having two or three outputs for providing a corrected output data word.

5 is a block diagram of an intermediate nth multiplexer in the series shown in FIG.

FIG. 6 is a transistor level schematic diagram of the nth multiplexer of FIG. 5;

FIG. 7 is a block diagram of the first multiplexer of FIG.

FIG. 8 is a transistor-level schematic of a first multiplexer in the series shown in FIG.

FIG. 9 is a block diagram of the final multiplexer.

FIG. 10 is a transistor level schematic of the last multiplexer of FIG. 9;

[Explanation of symbols]

102 fuse blocks, 104 logic blocks, 1
08 shift redundancy circuit, 110 output buffer.

Continued front page    (72) Inventor Michael Curtis Paris             United States, 80906 Colorado, CO             Rorad Springs, Daltrey Leh             5715 (72) Inventor Kim Carver Hardy             United States, 80920 Colorado, CO             Rorad Springs, Kit Curso             Lane, 9760 F term (reference) 5J055 AX44 BX03 BX04 CX27 DX22                       DX61 EZ00 EZ12 EZ13 EZ48                       GX01 GX02                 5L106 AA01 CC12 CC13 CC17 EE02                 5M024 AA42 BB10 BB26 BB30 BB35                       CC50 CC99 DD20 DD80 GG20                       HH10 KK35 MM12 MM13 MM20                       PP01 PP03

Claims (20)

[Claims] 1. A data shift circuit for use in an error correction memory comprising: a data shift circuit input for receiving uncorrected data and at least one spare bit; and a data shift for providing corrected data. A circuit output and a plurality of interconnected multiplexers, each of which has an input coupled to the data shift circuit input, at least one output coupled to the data shift circuit output, and a programmed boosted DC control voltage. A data shift circuit having at least one control terminal for receiving. 2. At least one of the multiplexers provides an input for receiving the nth data bit, a first output for providing the (n-1) th data bit, and an nth data bit. Output, a third output for providing the (n + 1) th data bit, a first control terminal for receiving a right shift control voltage, and a second control terminal for receiving an unshifted control voltage. 2. The data shift circuit according to claim 1, further comprising: a control terminal for receiving the left shift control voltage; 3. A multiplexer comprising: a first transistor having a current path coupled between an input and a first output and a gate coupled to a first control terminal; and an input and a second output. A second transistor having a current path coupled therethrough and a gate coupled to the second control terminal; and a current path coupled between the input and the third output and the third control terminal. The data shift circuit according to claim 2, further comprising a third transistor having a closed gate. 4. The data shift circuit according to claim 3, wherein each of the first, second and third transistors includes an N-channel transistor. 5. A first one of the multiplexers has a first input for receiving a first data bit, a second input for receiving a spare data bit, and a first data bit for providing a first data bit. A first output, a second output for providing a second data bit, a first control terminal for receiving a first right shift control voltage, and a second control terminal for receiving an unshifted control voltage. The data shift circuit of claim 1, including a control terminal and a third control terminal for receiving a second right shift control voltage. 6. The multiplexer comprises a first transistor having a current path coupled between a second input and a first output and a gate coupled to a first control terminal; a first input; A second transistor having a current path coupled to the first output and a gate coupled to the second control terminal; and a current path coupled to the first input and the second output. The data shift circuit of claim 5, further comprising: and a third transistor having a gate coupled to the third control terminal. 7. The data shift circuit according to claim 6, wherein each of the first, second and third transistors includes an N-channel transistor. 8. The last of the multiplexers has a first input for receiving the last data bit, a second input for receiving the spare data bit, and a second to last data bit. A first output, a second output for providing the last data bit, a first control terminal for receiving a first left shift control voltage, and a second control for receiving an unshifted control voltage The data shift circuit of claim 1, including a terminal and a third control terminal for receiving a second left shift control voltage. 9. The multiplexer comprises a first transistor having a current path coupled between a first input and a first output and a gate coupled to a first control terminal; a first input; A second transistor having a current path coupled to the second output and a gate coupled to the second control terminal, and a current path coupled to the second input and the second output. 9. The data shift circuit of claim 8, further comprising: and a third transistor having a gate coupled to the third control terminal. 10. The data shift circuit of claim 9, wherein the first, second and third transistors each include an N-channel transistor. 11. A fuse block including a plurality of programmed fuses for generating a predetermined data pattern, and for boosting the data pattern and converting it to left shift, no shift and right shift control voltages. The data shift circuit according to claim 1, further comprising a logic block. 12. The data shift circuit of claim 11, wherein the fuse block further includes a first power terminal for receiving an unboosted power supply voltage, and a second power terminal coupled to ground. . 13. The data shift circuit of claim 11, wherein the logic block further includes: a first power terminal for receiving a boosted power supply voltage; and a second power terminal coupled to ground. 14. The data shift circuit of claim 1, further comprising an output buffer for buffering the data shift circuit output. 15. A data shift circuit for use in an error correction memory, the data shift circuit input coupled to an uncorrected data bus, and the data shift circuit output coupled to a corrected data bus. A plurality of interconnected multiplexers, each for receiving an input coupled to a data shift circuit input, at least one output coupled to a data shift circuit output, and a programmed boosted DC control voltage. A data shift circuit having at least one control terminal. 16. At least one of the multiplexers has a first control terminal for receiving a first left shift control voltage, a second control terminal for receiving an unshifted control voltage, and a second left shift. The data shift circuit according to claim 15, further comprising a third control terminal for receiving a control voltage. 17. Each of the multiplexers includes a first and a second.
And a third N-channel transistor.
5. The data shift circuit according to item 5. 18. The programmed and boosted DC control voltage is boosted to a voltage higher than a memory power supply voltage.
The data shift circuit according to claim 15. 19. A fuse block for providing a data pattern, and a programmed and boosted D for boosting the data pattern.
The data shift circuit according to claim 15, further comprising a logic block for converting into a C control voltage. 20. A data shift circuit for use in an error correction memory, the data shift circuit input for receiving uncorrected data and at least one spare bit, and a data shift for providing corrected data. A circuit output and a plurality of interconnected N-channel transistor multiplexers, each of which has an input coupled to the data shift circuit input, at least one output coupled to the data shift circuit output, and a programmed boosted output. D
A data shift circuit having at least one control terminal for receiving a C data shift control voltage.