JP2003149673A - Active matrix substrate and display device using the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce the area of a switching matrix region in an active matrix substrate provided with the switching matrix region. SOLUTION: In an active matrix substrate provided with a display region and the active matrix region, a switching transistor 24 is formed on a gate switching bus line 22 for driving the switching transistor 24 provided in the active matrix region.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an active matrix substrate used for a display device, and more particularly, to an active matrix substrate mounted on a device requiring low power consumption such as a mobile phone, a PDA (Personal Digital Assistance) and a notebook personal computer. The present invention relates to an active matrix substrate and a display device using the same.

[0002]

2. Description of the Related Art In a conventional active matrix substrate used for a display device, a plurality of gate bus lines 102 and a plurality of signal bus lines 104, which are formed in parallel with each other, are made of glass, as schematically shown in FIG. Board 1
Thin film transistors (TFTs) 106 for switching pixels, which are arranged in a grid pattern on the upper part of each pixel 00. In each TFT 106, its gate electrode, source electrode and drain electrode are electrically connected to the gate bus line 102, source bus line 104 and pixel electrode 108, respectively.

The gate bus lines 102 and the source bus lines 104 are connected to the lead lines of the scan electrode driving IC 109 and the signal electrode driving IC 110 in a one-to-one correspondence. In this way, the display region is formed, and the gate electrode voltage and the source signal voltage are applied from the scan electrode driving IC 109 and the signal electrode driving IC 110, respectively.
A predetermined voltage is applied to 08.

In such a conventional technique, as the number of gate bus lines 102, which are scanning lines, increases, the number of connection points between the gate bus lines 102 and the lead lines of the scan electrode driving IC 109 becomes enormous. . Further, as the number of connection points increases, the pitch between the connection points also decreases, which makes it difficult to mount the scan electrode driving IC 109 on the periphery of the display area of the active matrix substrate 100. This problem similarly occurs in the relationship between the lead line of the signal electrode driving IC 110 and the source bus line 104. Further, since the number of IC chips required for the scan electrode driving IC 109 and the signal electrode driving IC 110 is increased, there is a problem that the cost ratio occupied by such a driving IC in the liquid crystal display device is also increased.

These problems have become particularly apparent in portable equipment such as portable telephones, which require a low-priced and compact liquid crystal display device.

In order to solve such a problem, as shown in FIG. 8, Japanese Patent Laid-Open No. 3-245126 discloses a method in which a plurality of source bus lines 104 are provided in an area adjacent to a display area of an active display substrate. It is disclosed that a switching matrix region having a plurality of switching transistors 112 is provided in order to selectively correspond the lead lines of the one signal electrode driving IC 110.

According to this technique, since the switching transistor 112 can be formed on the glass substrate 100 by using the thin film semiconductor technique like the TFT 106, the switching transistor 112 on the active display substrate to be connected to the lead line of the signal electrode driving IC 110 is formed. The number of electrodes can be reduced,
The above problem can be solved.

[0008]

However, the switching transistor 112 according to this technique is the TFT 10 for switching a pixel having a capacitance of only a few pF.
Different from 6, it is necessary to drive the source bus line (or gate bus line) having a capacitance of several tens of pF or more.

To this end, as disclosed in Japanese Patent Application Laid-Open No. 3-245126, the source electrode and the drain electrode are formed in a comb shape so that the ratio W of the width W of the switching transistor 112 to the channel length L is W. / L needs to be increased. However, such a shape causes a problem that the size of the switching transistor 112 becomes large and the area occupied by the switching matrix region becomes large.

By forming the source electrode and the drain electrode in a comb shape, the capacitance of the gate bus line 114 of the switching transistor 112 is increased. As a result, a large amount of current is required to drive the gate bus line 114, resulting in a new problem as a liquid crystal display device of a mobile device that requires low current consumption.

The present invention solves the above-mentioned problems, and an object thereof is to provide an active matrix having a switching matrix region for selecting one from a plurality of source bus runs or gate bus lines and applying a signal. To reduce the area of the switching matrix region in the substrate. Another object is to reduce the power consumption of such an active matrix substrate. Another object is to provide a display device using an active matrix substrate having such characteristics.

[0012]

The active matrix substrate of the present invention includes a display area and a switching matrix area. The display area includes a plurality of gate bus lines and a plurality of source bus lines provided on the insulating substrate, one of the plurality of gate bus lines, and one of the plurality of source bus lines, respectively. A plurality of pixel transistors connected to each other and a plurality of pixel electrodes connected to each of the plurality of pixel transistors are included. The switching matrix region is adjacent to the display region and intersects the plurality of source bus lines. The plurality of gate switch bus lines are provided on the insulating substrate and the plurality of source bus lines are connected to the ends thereof. A plurality of lines that are commonly connected by a predetermined number of lines, and are inserted in the plurality of source bus lines between the display region and the plurality of lines, respectively, and one of the plurality of gate switch bus lines A switching transistor provided on the gate switch bus line to be switched by.

Each of the plurality of switching transistors includes an island-shaped semiconductor structure having an intrinsic amorphous silicon layer and an n ⁺ amorphous silicon layer provided on the gate switch bus line via an insulating film, and is adjacent to each other. It may be separated from the semiconductor structure of the switching transistor. Further, each of the plurality of switching transistors may have a comb-shaped source electrode and a comb-shaped drain electrode provided on the semiconductor structure.

The comb-shaped source electrode and the comb-shaped drain electrode each have a plurality of electrode fingers and a connecting portion for connecting them, and the connecting portion may not overlap the gate switch bus line.

At least one of the plurality of gate switch bus lines may have a narrower width in at least one intersecting region with the plurality of source bus lines than in a region where the switching transistor is provided.

The display device of the present invention has any one of the above active matrix substrates, a counter substrate, and a display medium layer sandwiched therebetween.

[0017]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of an active matrix substrate according to the present invention will be described below.

As shown in FIG. 1, the active matrix substrate in this embodiment includes an insulating substrate 10, a display region 11 and a switching matrix region 13 provided on the insulating substrate 10.

In the display area 11, a plurality of gate bus lines 12 parallel to each other and a plurality of source bus lines 14 parallel to each other are provided on the insulating substrate 10 in a grid pattern. A thin film transistor (TFT) 16 for switching a pixel is provided near each intersection of the gate bus line 12 and the source bus line 14, and is connected to one of the plurality of gate bus lines 12 and one of the plurality of source bus lines 14. Has been done. TF
A pixel electrode 18 is connected to each T16. T
Each pixel electrode 18 is connected to the gate bus line 1 through the FT 16.
No. 02 and one of the source bus lines 14 are electrically connected. Further, the gate bus line 12 is electrically connected to the lead line of the scan electrode driving IC 19.

In the switching matrix area 13, a plurality of gate switch bus lines 22 are provided so as to be adjacent to the display area 11 on the insulated wire substrate 10, and intersect with the source bus line 14 extending from the display area 11. There is.

A switching transistor 24 is inserted in each source bus line 14 in the vicinity of the intersection with any one gate switch bus line 22. Gate electrode 26 of each switching transistor 24
Is connected to the gate switch bus line 22, and the drain electrode 30 and the source electrode 28 are connected to the source bus line 14.

The source bus lines 14 are commonly connected by wirings 32 in a number equal to the total number m of gate switch bus lines 22, and the wirings 32 are further connected to lead lines of the signal electrode driving IC 20. . Also,
The gate switch bus line 22 is connected to the lead wire of the switching drive IC 34. The switching transistor 24 driven by the outputs of the switching driving IC 34 and the signal electrode driving IC 20 is 1
Source bus line 1 to be identified and consequently driven
4 is also specified. As a result, the signal electrode driving IC 2
It is possible to reduce the number of the wirings 32 to be connected to the 0 lead line to 1 / m of the total number of the source bus lines 14. For example, in the case of an active matrix substrate having 528 source bus lines 14, gate switch bus lines 22
By providing two wirings, the number of wirings 32 to be connected to the lead lines of the signal electrode driving IC 20 can be set to 264.

FIG. 2 is an enlarged view of the structure in the vicinity of the switching transistor 24 formed in the switch matrix region 13, and FIG. 3 is a sectional view taken along the line AA 'shown in FIG.

The switching transistor 24 is formed on the gate switch bus line 22 using the gate switch bus line 22 as a gate electrode. In the switching transistor 24, the intrinsic amorphous silicon layer 3
A semiconductor structure 38 including 8b and an n ⁺ amorphous silicon layer 38a is provided on the gate switch bus line 22 via a gate insulating film 36. A source electrode 28 and a drain electrode 30 are provided on the semiconductor structure 38. The width of the gate switch bus line 22 is substantially equal along the longitudinal direction.

Source electrode 28 and drain electrode 30
Has a comb shape composed of electrode finger portions 28a and 30a and connecting portions 28b and 30b connecting them, respectively, and the electrode finger portions 28a and 30a are fitted to each other.

With this structure, a parasitic capacitance (Cgd1) 44 formed between the gate electrode 26 and the drain electrode 30 of the switching transistor 24 shown in FIG. 4 and between the gate electrode 26 and the source electrode 28 are formed. The parasitic capacitance (Cgs) 40 generated is reduced. Figure 5
A description will be given with reference to FIGS. Note that FIG.
In FIGS. 5A to 5D, it is assumed that the channel widths W of all the switching transistors are the same a.

As shown in FIG. 5A, when the source electrode S and the drain electrode D are not comb-shaped, Cgd1 and Cgd
The parasitic capacitance of the entire gate electrode (C
swg) is Cswg = 2 × a × C C = ε ₀ × ε × W / d, where ε ₀ : dielectric constant ε: relative dielectric constant of the insulating film W: source or drain line width d: thickness of the insulating film Is.

As shown in FIG. 5B, two source electrodes are used.
In the case of a comb shape composed of two electrode fingers, the length of the electrode finger is a in order that the width W of the switching transistor becomes a.
/ 2 is enough. Therefore, Cswg = 3 × (a / 2) ×
C = (3/2) × a × C, and the capacitance is reduced by (1/2) × a × C as compared with the structure of FIG. That is, as shown in FIG. 6, Cswg is 75% as compared with the structure of FIG.

FIG. 5C shows a case where the source electrode has a comb shape consisting of three electrode fingers, and the drain electrode has a comb shape consisting of two electrode fingers. In this case, the length of the electrode finger is Since a / 4 is sufficient, Cswg = 5 × (a / 4) × C =
It becomes (5/4) × a × C.

Similarly, as shown in FIG. 5D, when the drain electrode is formed into a comb shape having n electrode fingers, C
Swg = {(2 × n + 1) / (2 × n)} × a × C.

When n is 10, Csw as shown in FIG.
g is about 53%. Therefore, if n is a sufficiently large numerical value, Cswg = a × C, and Cswg is 50% compared with the structure of FIG.

By thus forming the source electrode and the drain electrode in a comb shape, it is possible to reduce the parasitic capacitance of the gate electrode in each of the switching transistors 24. Therefore, the capacitance of the entire active matrix substrate is also about 50. % Reduction. by this,
The power consumption can also be reduced by about 50%, and the power consumption of the active matrix substrate can be reduced.

Further, the switching transistor 24 is
A part of the gate switch bus line 22 is formed on the gate switch bus line 22 as a gate electrode.
Therefore, the area for forming the switching transistor 24 becomes unnecessary, and the switching matrix area 13 can be made small. Furthermore, by increasing the number of electrode fingers of the source electrode 28 and the drain electrode 28, the effective transistor width W can be made the same even if the width of the gate switch bus line 22 is narrowed. In such a case, the switching matrix region 13 can be made smaller by narrowing the width of the gate switch bus line 22.

In addition to the above structure, as shown by the dotted line in FIG. 2, in the gate switch bus line 22, the width c is larger than the width c of the region where the switching transistor 24 is provided.
The width b of the region intersecting with the source bus line 14 may be narrowed. As a result, the parasitic capacitance (Cgd2) 46 formed between the source bus line 14 and the gate switch bus line 22 shown in FIG. 4 can be reduced. As a result, the capacitance of the source bus line 14 and the gate switch bus line 22 can be reduced. Further, it is possible to prevent the delay of the signal input to the source bus line 14.

This effect is achieved by the gate switch bus line 2
It is obtained by narrowing the width in at least one location of at least one of the two. However,
In order to reduce the power consumption of the active matrix substrate, it is preferable that the parasitic capacitance (Cgd2) 46 be as small as possible. Therefore, it is preferable that the width b is narrow in the intersection region between the gate switch bus line 22 and the source bus line 14 as much as possible. Specifically, among the plurality of intersection regions formed by the intersection of one gate switch bus run 22 and the plurality of source bus lines 14, all the intersection regions where the switching transistor 24 is not provided The width of the gate switch bus line 22 is preferably narrow. In addition, as shown in FIG. 2, each source bus line 1
Switching transistor 24 and wiring 3 provided in 4
Gate bus line 22 and source bus line 1 between 2 and
If there is a crossing region with 4, the width of the gate bus line 22 may be narrow at that portion as well.

Further, the semiconductor structure 38 of each switching transistor 24 is preferably formed in an island shape and separated from the semiconductor structure 38 of the adjacent switching transistor 24. As a result, the source bus line 14 and the switching transistor 24 adjacent thereto
It is possible to prevent a leak current from being generated due to the formation of the channel region.

Further, as shown in FIG.
8 and the drain electrode 30, it is preferable that the connecting portions 28 and 30b do not overlap the gate switch bus line 22. With this structure,
The parasitic capacitance (Cgs) 40 and the parasitic capacitance (C
The gd1) 44 can be further reduced, and the power consumption of the active matrix substrate can be further reduced.

Next, an example of a method of manufacturing the active matrix substrate according to the embodiment of the present invention will be described with reference to FIGS.

First, a titanium film is formed on an insulating substrate 10 such as glass by using a thin film forming apparatus such as a sputtering apparatus.
An aluminum film and a titanium nitride film are laminated in this order, and these films are patterned by a photolithography method to form a gate bus line 12, a gate switch bus line 22, a gate electrode (not shown) of the TFT 16 and a scan electrode driving IC 19. A connection terminal (not shown) for connection and a connection terminal (not shown) for connecting the scanning signal electrode driving IC 20 are formed.

Next, a gate insulating film 36 covering at least the display region 11 and the switching matrix region 13 is formed by a deposition method such as plasma CVD, and then an intrinsic amorphous silicon layer 38b and an n ⁺ amorphous silicon layer 38a are deposited. . The intrinsic amorphous silicon layer 38b and the n ⁺ amorphous silicon layer 38a are patterned by the photolithography method to form the island-shaped semiconductor structure 38 in the switching matrix region 13. Although not shown, the semiconductor structure of the TFT 16 is also formed in the display area 11 at the same time.

A titanium film and an aluminum film are formed in this order on the insulating substrate 10 having the above structure by a sputtering method or the like, and these films are patterned by a photolithographic method to form the source electrode 28, the drain electrode 30, the source. The bus line 14 and the wiring 32 are formed. At the same time, the source electrode of the TFT 16 not shown,
A drain electrode is also formed.

Then, in at least a region of the semiconductor structure 38 that will be a channel, the n ⁺ amorphous silicon layer 3 is formed using the source electrode 28 and the drain electrode 30 as a mask.
8a is removed.

Finally, the insulating substrate 10 having the above structure.
By a deposition method such as plasma CVD to cover the
An active matrix substrate is manufactured by forming a silicon nitride film as a protective film.

Although the active matrix substrate has been described above as an embodiment, the active matrix substrate of the present invention is preferably used for a liquid crystal display device. For example, a counter substrate provided with a counter electrode and a color filter layer is prepared, an alignment film is provided on the active matrix substrate and the counter substrate, and alignment treatment is performed by a rubbing method so that the alignment treated surfaces are inside each other and a sealing material is interposed. By injecting liquid crystal between the bonded substrates, the liquid crystal display device according to the present invention can be obtained.

In addition to the liquid crystal display device, a material whose optical properties are modulated or emits light when a voltage is applied is used as a display medium layer, and is used between the counter substrate and the active matrix substrate of the present invention. By holding such a display medium layer, various display devices can be obtained. For example, the active matrix substrate of the present invention is preferably used for a display device such as an organic EL display device using an organic fluorescent material as a display medium layer.

[0046]

According to the present invention, in the active matrix substrate having the display area and the switching matrix area, the area of the switching matrix area can be reduced.

Further, it is possible to reduce the capacitance of the gate switch bus line that drives the switching transistors in the switching matrix area. Therefore, an active matrix substrate and a liquid crystal display device with low power consumption are provided.

Further, since the capacitance of the source bus line or the gate bus line can be reduced, the delay of the source signal or the gate signal can be prevented, and the active matrix substrate and the liquid crystal display device having excellent responsiveness can be provided.

By preventing a leak current between the switching transistor in the switching matrix region and the source bus line or the gate bus line, an active matrix substrate and a liquid crystal display device having excellent controllability are provided.

[Brief description of drawings]

FIG. 1 is a diagram schematically illustrating an embodiment of an active matrix substrate according to the present invention.

FIG. 2 is a diagram showing a structure of a switching transistor in a switching matrix region which is a main part in an embodiment of an active matrix substrate according to the present invention.

FIG. 3 is a cross-sectional view taken along the line A-A ′ of the structure shown in FIG.

FIG. 4 is a diagram showing a parasitic capacitance of a switching matrix region.

5A to 5D are diagrams showing gate parasitic capacitance of a transistor including a comb-shaped source electrode and a comb-shaped drain electrode.

FIG. 6 is a graph showing the relationship between the number of electrode fingers of the comb-shaped source electrode and the comb-shaped drain electrode and the gate parasitic capacitance.

FIG. 7 is a diagram schematically showing a conventional active matrix substrate.

FIG. 8 is a diagram schematically showing another conventional active matrix substrate.

[Explanation of symbols]

10, 100 insulating substrate 11 Display area 12, 102 Gate bus line 13 Switching matrix area 14, 104 Source bus line Thin film transistor for 16 and 106 pixels 18, 108 Pixel electrode 19, 109 Scan electrode driving IC 20,110 IC for driving signal electrodes 22,112 Gate switch bus line 24, 114 switching transistors 26 Gate electrode 28 Source electrode 30 drain electrode 32 wiring 34 Switching drive IC 36 Gate insulation film 38 Semiconductor structure 40 Parasitic capacitance (Cgs) 44 Parasitic capacitance (Cgd1) 46 Parasitic capacitance (Cgd2)

─────────────────────────────────────────────────── ─── Continuation of front page (51) Int.Cl. ⁷ Identification code FI theme code (reference) H01L 29/78 616T 614 (72) Inventor Hiroshi Fujiki 22-22 Nagaikecho, Abeno-ku, Osaka-shi, Osaka In-house F-term (reference) 2H092 GA14 GA59 JA24 JA42 JB32 MA05 MA07 MA13 NA21 5C094 AA13 AA15 AA22 AA25 BA03 BA43 CA19 DB01 DB04 EA04 EA07 5F110 AA02 AA09 BB02 CC07 DD02 HK21 HK04 HK04 HK04 HK04 HK04 HK04 HK04 HK04 GG04 GG04 GG02 GG15 GG02 GG15 HK02 HK03 HK04

Claims (6)

[Claims] 1. An insulating substrate, a plurality of gate bus lines and a plurality of source bus lines provided on the insulating substrate, and any one of the plurality of gate bus lines and the plurality of source bus lines. A display region including a plurality of pixel transistors each connected to one of the plurality of pixel transistors and a plurality of pixel electrodes connected to each of the plurality of pixel transistors; and a plurality of source buses adjacent to the display region. A plurality of gate switch bus lines provided on the insulating substrate so as to intersect the lines, a plurality of wirings for commonly connecting a predetermined number of the source bus lines at their end portions, and the display area And the plurality of source bus lines are respectively inserted between the plurality of wirings and the plurality of wirings. The active matrix substrate having a switching matrix area, the including a switching transistor provided on the gate switch bus line on so as to be switched by one of the gate switch bus lines. 2. Each of the plurality of switching transistors includes an intrinsic amorphous silicon layer provided on the gate switch bus line via an insulating film and n ^+.
The active matrix substrate according to claim 1, further comprising an island-shaped semiconductor structure having an amorphous silicon layer, which is separated from a semiconductor structure of an adjacent switching transistor. 3. The active matrix substrate according to claim 2, wherein each of the switching transistors has a comb-shaped source electrode and a comb-shaped drain electrode provided on the semiconductor structure. 4. The comb-shaped source electrode and the comb-shaped drain electrode each have a plurality of electrode fingers and a connecting portion that connects them, and the connecting portion does not overlap the gate switch bus line. The active matrix substrate according to. 5. At least one of the plurality of gate switch bus lines has a width narrower than an area where the switching transistor is provided in at least one intersecting region with the plurality of source bus lines. Item 5. The active matrix substrate according to item 3. 6. A display device comprising the active matrix substrate according to claim 1, a counter substrate, and a display medium layer sandwiched therebetween.