JP2003140767A - Frequency control circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a frequency control circuit in which power consumption can be reduced without increasing the variation of a clock frequency. SOLUTION: This frequency control circuit is provided with a control circuit 15 for outputting a first control signal S151 to a clock supplying circuit 12 when a through-put T is requested in order to instruct the clock supplying circuit 12 to decide two clock frequencies and each period from the value of the through-put T and the value of a through-put to be realized from a clock frequency which can be generated by the clock supplying circuit 12, and to select those two clock frequencies in each decided period, and to output it as a system clock, and for outputting a second control signal S152 to a power supply voltage supplying circuit 13 in order to instruct the power supply voltage supplying circuit 13 to supply a power supply voltage with which the operation of a target circuit can be ensured in each of those two clock frequencies instructed to the clock supply circuit 12.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a frequency control circuit for controlling a clock frequency of a system clock supplied to a target circuit which performs a predetermined process in synchronization with the system clock, and more particularly, by controlling the clock frequency. The present invention relates to a technique for achieving low power consumption while realizing the throughput required for a system.

[0002]

2. Description of the Related Art FIG. 8 is a diagram showing a relation between throughput and power consumption of a general electronic circuit system. In FIG. 8, the horizontal axis represents throughput and the vertical axis represents power consumption.

This system is supplied with a clock of the highest operating frequency, and when the power supply voltage of a fixed value that guarantees the operation at the highest operating frequency is supplied, the maximum T
It is assumed that it has the ability to perform processing of 0 and consumes power of P0 at this time. In this system, regardless of the required throughput, the system is set to be supplied with the clock of the maximum operating frequency and the fixed value of the power supply voltage that guarantees operation at the maximum operating frequency. In this case, the power consumption of this system always consumes a constant power P0 as indicated by the characteristic indicated by reference numeral 1-1 in FIG.

Since the throughput of the system is proportional to the operating frequency, it is possible to generate an arbitrary clock frequency in proportion to the required throughput.
If a power supply voltage that guarantees operation at that frequency can be supplied, lowering (lowering) the frequency can lower the power supply voltage that guarantees operation, and the power consumption will be proportional to the frequency. Since it is proportional to the square of the power supply voltage, theoretically, it is possible to reduce the power consumption up to the characteristics shown by reference numeral 1-2 in FIG.

[0005]

However, it is difficult to generate an arbitrary clock frequency, and when the number of frequencies that can be generated is finite, how to approach this characteristic is a technical problem. It was

In a system capable of generating only a single clock frequency, a clock having the highest operating frequency is always supplied, and a power supply voltage having a fixed value that guarantees operation at the highest operating frequency is supplied. Therefore, when there is a process required for the system, a clock is supplied to the system, and when there is no process required for the system, the system clock is stopped to reduce the power consumption. It was At this time, the power consumption of the system can be reduced in proportion to the processing amount, as indicated by the characteristic indicated by reference numeral 1-3 in FIG.

In recent years, there has been proposed a system including a clock supply circuit capable of generating a plurality of clock frequencies and a power supply voltage supply circuit capable of supplying a power supply voltage according to the clock frequencies.

FIG. 9 shows the relationship between throughput and power consumption in a system including a clock supply circuit capable of generating a plurality of clock frequencies and a power supply voltage supply circuit capable of supplying a power supply voltage according to the clock frequencies. FIG. In FIG. 9, the horizontal axis represents throughput and the vertical axis represents power consumption.

In the example of the system shown in FIG. 9, a clock supply circuit capable of generating four types of clock frequencies f0, f1, f2, and f3 is provided, and the throughput of T0, T1, T2, and T3 at each clock frequency is provided. And a power supply voltage supply circuit capable of supplying the lowest power supply voltage that guarantees the operation of the system at each clock frequency, and the maximum power consumption of P0, P1, P2, and P3 is achieved at each clock frequency. I assume.

In this case, when the throughput T required by the system is between T1 and T2, the minimum clock frequency f1 that satisfies T is selected, and the clock supply is stopped when the requested processing is completed. The power consumption at this time is a value proportional to the throughput, with P1 being the maximum.
Therefore, as shown by reference numeral 2-4 in FIG. 9, there is a stepwise relationship according to the number of frequencies. In FIG. 9, the power consumption can be further reduced by operating the system at a plurality of clock frequencies, as compared with the characteristics in the case of a single clock frequency indicated by reference numeral 2-3.

However, in order to further reduce the power consumption, it is necessary to realize more frequencies in order to approach the characteristics shown by reference numeral 2-2 in FIG. 9, which is the theoretical limit. As a method of realizing a plurality of clock frequencies, there are a method of using a plurality of oscillation circuits and a method of setting the settings of the oscillation circuits more finely. However, in either case, the clock supply circuit becomes more complicated. Have a profit

The present invention has been made in view of the above circumstances, and an object thereof is to provide a frequency control circuit capable of reducing power consumption without increasing variations in clock frequency.

[0013]

In order to achieve the above object, the frequency control circuit according to the first aspect of the present invention is capable of supplying system clocks having a plurality of clock frequencies which respectively realize different throughputs. When a throughput T is required and a clock supply circuit that supplies a system clock having a clock frequency corresponding to a control signal to a target circuit that performs processing in synchronism with the value of the throughput T and the clock supply circuit. From the value of the throughput that can be realized from the clock frequency that can be generated, determine the two clock frequencies and their respective periods, and select the two clock frequencies by the determined periods, and output the control signal as the system clock. And a control means for outputting to the clock supply circuit.

In the present invention, the control means determines the period to be selected between the two clock frequencies based on the internal division ratio of the throughput.

Further, in the present invention, when the throughput T is requested, the control means selects one clock frequency that realizes a throughput of T or more and one clock frequency that realizes a throughput of less than T.

Further, according to the present invention, the control means selects one clock frequency that achieves a minimum throughput of T or more and one clock frequency that achieves a maximum throughput of less than T.

Further, in the present invention, the control means gives an instruction by a control signal to select and output a clock having a higher clock frequency from the selected two clock frequencies.

Further, according to the present invention, the control means has a timer capable of setting the measurement time, and the control means sets the determined period in the timer to switch clocks of two frequencies.

According to the frequency control circuit of the second aspect of the present invention, it is possible to supply the system clocks having a plurality of clock frequencies which respectively realize different throughputs to the target circuit which performs processing in synchronization with the system clock. A clock supply circuit for supplying a system clock having a clock frequency according to the first control signal, a power supply voltage supply circuit for supplying a power supply voltage having a value according to the second control signal to the target circuit, and a throughput T. Is required, two clock frequencies and respective periods are determined from the value of the throughput T and the throughput value that can be realized from the clock frequency that can be generated by the clock supply circuit, and the period when the two clock frequencies are determined. First control signal for instructing to select each of them and output as the system clock The second control signal is output to the clock supply circuit, and the second control signal is supplied to the power supply voltage supply circuit so as to supply the power supply voltage that guarantees the operation of the target circuit at each of the two clock frequencies instructed to the clock supply circuit. And a control means for outputting to.

In the present invention, when the control means gives an instruction to increase the frequency, the second means is arranged so that the power supply voltage that can guarantee the operation of the system is increased in advance for the frequency to be changed next. The power supply voltage supply circuit is instructed by the control signal of 1, and the clock supply circuit is instructed by the first control signal to increase the frequency.

Further, according to the present invention, the control means, when instructing to lower the frequency, instructs the clock supply circuit to lower the frequency by the first control signal and changes the frequency to be changed next. On the other hand, the power supply voltage supply circuit is instructed by the second control signal so as to lower the power supply voltage so that the operation of the system can be guaranteed.

Further, according to the present invention, when the control means gives an instruction to increase the frequency, the control means should increase the power supply voltage that can guarantee the operation of the system in advance with respect to the frequency to be changed next. When the power supply voltage supply circuit is instructed by the second control signal, the clock supply circuit is instructed by the first control signal to increase the frequency, and when the frequency is instructed, the frequency is lowered. As described above, the first control signal instructs the clock supply circuit, and the second control signal causes the power supply voltage supply circuit to lower the power supply voltage at which the system operation can be guaranteed for the frequency to be changed next. Give instructions.

According to the present invention, the throughput T is required.
Then, the control means realizes the throughput T.
Therefore, two clock frequencies are determined. To control means
For example, a minimum throughput of T or higher and
One clock frequency that appears and the maximum frequency less than T
One clock frequency to achieve
It For example, if T3 <T2 <T ≦ T1 <T0,
The clock frequency that achieves these throughputs.
Letting f3, f2, f1, and f0 be the throughput T1
Realize achievable clock frequency f1 and throughput T2
The current possible clock frequency f2 is selected. Next,
Set the clock frequency to f1 based on the internal division ratio of the loop
Period t _f1And a period t in which the clock frequency is f2_f2
Is calculated.

Next, for example, it is determined whether or not the higher clock frequency f1 of the selected clock frequencies is higher than the current clock frequency. When the clock frequency f1 is higher than the current clock frequency, a second control circuit for instructing the power supply voltage supply circuit to increase (increase) the power supply voltage value in order to operate at the clock frequency f1 is supplied. To be done. As a result, the power supply voltage supply circuit supplies the target circuit with the power supply voltage set to a value that can guarantee the operation at the clock frequency f1. Then, for example, the control means sets a time (setup time t _set ) for increasing the power supply voltage in advance to the timer.

When the setup time t _set is measured by the timer, the control means detects that the setup time t _set has elapsed since the instruction to increase the power supply voltage was issued. Along with this, the control means outputs the first control signal for instructing the clock supply circuit to select the clock frequency f1 and output it as the system clock to the target circuit. Then, the control means sets the period t _f1 for selecting and outputting the clock frequency f1 to the timer. Clock frequency f in timer
When the period t _{f1 of} 1 is measured, the control means issues an instruction to select and output the clock frequency f1 and then the period t _f1.
Is detected. Accordingly, the control means causes the clock supply circuit to supply the clock frequency f1.
To the clock frequency f2 and outputs the first control signal instructing to output the system clock to the target circuit.

Next, the power supply voltage supply circuit is supplied with a second control circuit for instructing the power supply voltage value to be lowered (lowered) to a power supply voltage value capable of operating at the clock frequency f2. As a result, the power supply voltage supply circuit supplies the target circuit with the power supply voltage set to the lowest value that can guarantee the operation at the clock frequency f2. Then, the timer from the control means, from the time t _f2 which selects and outputs the clock frequency f2 up time t _set time obtained by subtracting (t _f2 -t _set) is set. When the timer time (t _f2 -t _set) is measured, the control of the frequency and the power supply voltage within a unit time is completed.

[0027]

1 is a block diagram showing an embodiment of an electronic circuit system to which a frequency control circuit according to the present invention is applied.

As shown in FIG. 1, the circuit system 10 has a target circuit 11, a clock supply circuit 12, a power supply voltage supply circuit 13, a timer 14, and a control circuit 15.

The target circuit 11 constitutes a system to be controlled by the clock frequency and the power supply voltage V _DD ,
As will be described later, the power supply voltage V _DD is supplied from the power supply voltage supply circuit 13 capable of supplying the lowest power supply voltage that guarantees the system operation at the clock frequency, and the multi-tone clock frequency is generated. System clock SYSC supplied from the clock supply circuit 12
It operates in synchronization with LK and performs desired processing.

The clock supply circuit 12 can generate a system clock SYSCLK having a clock frequency of multiple gradations, and the control circuit 15 outputs a first control signal S15.
The system clock SYSCLK having the clock frequency designated by 1 is supplied to the target circuit 11.

FIG. 2 is a diagram showing a concrete configuration example of the clock supply circuit of FIG. This clock supply circuit 12
2, a phase locked loop circuit (PLL circuit) 121 that oscillates a clock of a predetermined frequency, a plurality of, for example, four types of clock frequencies f0, f1, with a plurality of frequency division ratios.
It is composed of a frequency divider 122 for generating clocks f2 and f3, and a selector 123 for selecting and outputting a system clock having a clock frequency designated by the first control signal S151 by the control circuit 15.

In the clock supply circuit 12 according to the present embodiment, as shown in FIG. 3, T0, T1, T2, T3.
Clock frequencies that realize the throughput of f0, f
1, f2 and f3. For example, these four throughputs T0, T1, T2, T3 are 100% and 75%, respectively.
%, 50%, 25%, the oscillation clock of the PLL circuit 121 is, for example, 1/3, 1/4, 1/6, 1 /
By dividing with a division ratio of 12, a desired clock frequency can be generated. For example, when the specified maximum frequency is 100 MHz and the output frequency of the PLL circuit 121 is 300 MHz, each clock frequency f0, f
1, f2 and f3 are as follows.

[0033]

[Equation 1]             f0 = 300MHz / 3 = 100MHz             f1 = 300MHz ÷ 4 = 75MHz             f2 = 300MHz ÷ 6 = 50MHz             f3 = 300MHz ÷ 12 = 25MHz                                                             … (1)

In this clock supply circuit 12, P
An oscillation clock having a frequency of 300 MHz, for example, of the LL circuit 121 is supplied to the frequency divider 122. In the frequency divider 122, a plurality of frequency division ratios, for example, 1/3, 1/4, 1/6,
By dividing the oscillation clock of the PLL circuit 121 with a division ratio of 1/12, for example, f0 (= 100 MH)
z), f1 (= 75 MHz), f2 (= 50 MHz),
A clock having a clock frequency of f3 (= 25 MHz) is generated and supplied to the selector 123. Then, in the selector 123, a clock having a desired frequency is selected according to the first control signal S151 from the control circuit 15, and is supplied to the target circuit 11 as the system clock SYSCLK.

The source voltage supply circuit 13 can supply a multi-tone power supply voltage V _DD, the power supply voltage V _DD of the second value corresponding to the control signal S152 of the control circuit 15 to the target circuit 11 Supply.

The timer 14 is a clock F whose frequency is fixed.
By operating in synchronization with XCLK, a fixed time is measured, and the measurement result is output to the control circuit 15 as the coincidence signal S14 each time.

FIG. 4 is a diagram showing a specific configuration example of the timer shown in FIG. This timer 14 is, as shown in FIG.
Counter 14 that operates in synchronization with clock FXCLK
1, a compare register 142 for holding a comparison value VCMP to be compared with the count value VCNT of the counter 141,
The comparator 143 is configured to compare the count value VCNT of the counter 141 and the comparison value VCMP held in the compare register 142.

In the timer 14, the comparison value VCMP held in the compare register 142 is the control circuit 15
When the count value VCNT of the counter 141 coincides with the comparison value VCMP, the coincidence signal S14 for notifying the coincidence is output from the comparator 143 to the control circuit 15.

The control circuit 15 can measure the time based on the coincidence signal S12 from the timer 12, and one clock frequency that realizes a throughput of T or more, for example, in order to realize the required throughput T, One clock frequency that realizes a throughput less than T is selected, and these are switched within the unit time t _UNIT at a period determined by the internal division ratio of the throughput to change the system clock S.
A second control signal S151 instructing to output as YSCLK is output to the clock supply circuit 12, and a second control signal S151 instructing to supply the lowest power supply voltage V _DD that guarantees the operation of the system at the selected clock frequency. The control signal S152 is output to the power supply voltage supply circuit 13.
Further, as described above, the control circuit 15 outputs the comparison value VCMP to be set in the compare register 142 of the timer 14 to the timer 14 as the signal S153.

As described above, the control circuit 15 selects one clock frequency that realizes the throughput of T or more and one clock frequency that realizes the throughput of less than T in order to realize the required throughput T. But,
Preferably, it is desirable to select one clock frequency that achieves a minimum throughput of T or higher and one clock frequency that achieves a maximum throughput of less than T. The reason is that if two clock frequencies that realize a throughput higher and a throughput smaller than the required throughput T are used, the same operation and the desired effective frequency can be achieved, but a clock that satisfies the above conditions must be used. This is because the power consumption can be minimized by making a selection.

For example, assuming that T3 <T2 <T≤T1 <T0, the throughput T is realized even if two clock frequencies such as clock frequencies f0 and f2, f0 and f3, f1 and f3 are selected. Although it is possible, selecting the clock frequencies f1 and f2 is the minimum in terms of power.

In the present embodiment, the selected 2
Of the two clock frequencies, the one with the higher clock frequency is selected and output. In the above example, the unit time t
_{In unit} , the clock frequency f1 is selected for a predetermined period t _f1 , and subsequently the clock frequency f2 is selected for a predetermined period t _f2 . As described above, by selecting one having a higher clock frequency, the realized effective throughput is always higher than the required throughput, and the demand can be satisfied.

Further, the control function of the control circuit 15 will be described with reference to the timing chart of FIG.

Here, as described above, the clock supply circuit 12 has four clock frequencies f0, f1 and f.
2, f3 can be generated and, as shown in FIG. 3, T0, T1, T2, T at each clock frequency.
The throughput of 3 can be realized, and the power supply voltage supply circuit 13
Can supply the lowest power supply voltage that guarantees the operation of the system at each clock frequency, and maximum P0, P1, P2, at each clock frequency.
It is assumed that the power consumption is P3.

For example, as described above, when the required throughput T of the system is between T1 and T2, it is required by combining the minimum clock frequency f1 that satisfies T and the frequency f2 that is one step lower than f1. Throughput T can be realized.

Then, as shown in FIGS. 5A and 5B, the control circuit 15 sets the period t _f1 where the clock frequency is _f1 and the clock frequency f2 in order to realize the required throughput T. Unit time t _unit in period t _f2
Split. Each period is as shown in the following formula,
It is determined by the internal division ratio of the throughput.

[0047]

## EQU2 ## t _f1 = {(T-T2) / (T1-T2)} × t _unit (2)

[0048]

## _EQU3 ## t _f2 = {(T1-T) / (T1-T2)} × t _unit (3)

As a result, the required effective throughput T _eff can be realized.

[0050]

## _EQU00004 ## T _eff = (t _f1 × T1 + t _f2 × T2) / t _unit (4)

When the throughput T is requested, the control circuit 15 determines two clock frequencies and respective periods from the value of T and the throughput value that can be realized from the clock frequency that can be generated by the clock supply circuit 12, and the timer 14
The required throughput T is realized by controlling the frequency switching using.

When the control circuit 15 switches from a low frequency to a high frequency in consideration of the setup time t _set required for the power supply voltage supply circuit 13 to change the power supply voltage, as shown in FIG. 5 (C). The second control signal S152 instructs the power supply voltage supply circuit 13 to increase the power supply voltage according to the high frequency at a time point earlier than that timing by the setup time t _set . Also,
When switching from the high frequency to the low frequency, the power supply voltage supply circuit 13 is instructed by the second control signal S152 to lower the power supply voltage according to the low frequency at the timing. By controlling the power supply voltage at this timing, the operation of the system can be guaranteed even if the frequency is switched. The control circuit 15 can control the power supply voltage at an appropriate timing by measuring the time using the timer 14.

Next, the operation of the control circuit 1 will be described.
The control operation of No. 5 will be mainly described in association with the flowchart of FIG. 7.

When the throughput T is required, the control circuit 15 determines two clock frequencies in order to realize the throughput T. The control circuit 15 selects one clock frequency that achieves a minimum throughput of T or more and one clock frequency that achieves a maximum throughput of less than T. In the present embodiment, since it is assumed that T3 <T2 <T ≦ T1 <T0, the clock frequency f1 that can realize the throughput T1 and the clock frequency f2 that can realize the throughput T2 are selected (ST1. ).

Next, according to the above equations (2) and (3), a period t _{f1 in} which the clock frequency is f1 and a period t _{f2 in} which the clock frequency is _f2 are calculated (ST2).

Next, it is determined whether or not the higher clock frequency f1 of the selected clock frequencies is higher than the current clock frequency (ST3). Step ST
In 3, when the clock frequency f1 is higher than the current clock frequency, the process proceeds to the next step ST4, and when it is lower, the process proceeds to step ST6.

In step ST4, the power supply voltage supply circuit 13 is supplied with the second control circuit S152 for instructing to increase (increase) the power supply voltage value in order to operate at the clock frequency f1. As a result, the clock frequency f is supplied from the power supply voltage supply circuit 13 to the target circuit 11.
The power supply voltage V _DD set to a value that can guarantee the operation at 1 is supplied. Then, the signal S15 for setting the setup time t _set from the control circuit 15 to the timer 14.
3 is output. As a result, the setup time t _set is held in the compare register 142 of the timer 14.

Then, in the timer 14, the counter 1
The setup time t _set in which the count value VCNT of 41 is held in the compare register 142 (comparison value VCMP)
A match signal S for notifying the match when
14 is output from the comparator 143 to the control circuit 15 (ST5), and the process proceeds to the next step ST6.

In the control circuit 15, when it is detected that the setup time t _set has elapsed after the coincidence signal S14 from the timer 14 is input and the instruction to increase the power supply voltage V _DD is received, the clock supply circuit 12 is notified. , A first control signal S151 for instructing to select the clock frequency f1 and output it as the system clock SYSCLK to the target circuit 11 is output (ST6). Then, the signal S153 for setting the period t _f1 for selecting and outputting the clock frequency f1 from the control circuit 15 to the timer 14.
Is output. As a result, the compare register 142 of the timer 14 holds the period t _f1 of the clock frequency f1.

Then, in the timer 14, the counter 1
The count value VCNT of 41 is held in the compare register 142 during the period t _{f1 of the} clock frequency _f1 (the comparison value VC
MP), a match signal S14 for notifying the match is output from the comparator 143 to the control circuit 15 (ST7), and the process proceeds to the next step ST8.

When the control circuit 15 detects that the period t _f1 has elapsed from the time when the coincidence signal S14 from the timer 14 is input and the instruction to select and output the clock frequency f1 is detected, the clock supply circuit 12 is notified. On the other hand, the first control signal S151 for instructing to change the clock frequency f1 to the clock frequency f2 and output the system clock SYSCLK to the target circuit 11 is output (ST.
8).

Next, the second control circuit S for instructing the power supply voltage supply circuit 13 to lower (lower) the power supply voltage value to a power supply voltage value capable of operating at the clock frequency f2.
152 is supplied (ST9). As a result, the power supply voltage supply circuit 13 supplies the target circuit 11 with the power supply voltage V _DD set to the minimum value that can guarantee the operation at the clock frequency f2. Then, with respect to the control circuit 15 timer 14, a signal S153 for setting the time period t _f2 time obtained by subtracting the set-up time t _set from (t _f2 -t _set) for selecting and outputting a clock frequency f2 is output It As a result, the compare register 1 of the timer 14
At 42, the time (t _f2 −t _set ) is held.

Then, in the timer 14, the counter 1
When the count value VCNT of 41 coincides with the time (t _f2- t _set ) (comparison value VCMP) held in the compare register 142, a coincidence signal S1 for notifying the coincidence
4 is output from the comparator 143 to the control circuit 15 (ST10), and the process returns to step ST4.

FIG. 7 is a diagram showing the relationship between throughput and power consumption of the circuit system of FIG. 1 according to this embodiment.
In FIG. 7, the horizontal axis represents throughput and the vertical axis represents power consumption.

The power consumption P when the throughput T is requested is represented by the internal division ratio of the power when two frequencies are used, as shown in the following equation.

[0066]

(5) P = (t _f1 × P1 + t _f2 × P2) / t _unit (5)

Therefore, the circuit system of FIG. 1 according to the present embodiment has the characteristics shown by 10-5 in FIG.
Lower power consumption closer to the theoretical characteristic 10-2 is realized than the characteristic 10-1, 10-3, 10-4 by the conventional method.

The number of clock frequencies is 4 as an example.
It is not limited to the above, and is determined by considering the performance of the clock supply circuit and the frequency division according to the theoretical characteristic 10-2.

As described above, according to the present embodiment, it is possible to supply the system clocks having a plurality of clock frequencies that respectively realize different throughputs, and to the target circuit 11 that performs processing in synchronization with the system clock, A clock supply circuit 12 for supplying a system clock having a clock frequency according to the first control signal S151.
And a power supply voltage supply circuit 13 that supplies a power supply voltage having a value according to the second control signal S152 to the target circuit 11,
When the throughput T is required, two clock frequencies and respective periods are determined from the value of the throughput T and the throughput value that can be realized from the clock frequency that can be generated by the clock supply circuit 12, and the two clock frequencies are determined. Output the first control signal S151 to the clock supply circuit 12 to instruct the clock supply circuit 12 to select and output as a system clock for each period, and to operate the target circuit at each of the two clock frequencies instructed to the clock supply circuit 12. Since the control circuit 15 that outputs the second control signal S152 to the power supply voltage supply circuit 13 is provided so as to supply the power supply voltage that guarantees the power consumption, the power consumption can be reduced without increasing the variation of the clock frequency. There is an advantage that can be.

Further, according to the present embodiment, the control circuit 15
In consideration of the setup time t _set required for the power supply voltage supply circuit 13 to change the power supply voltage, when switching from a low frequency to a high frequency, the power supply voltage supply circuit 1 is advanced from that timing by the setup time t _set.
3 is instructed by the second control signal S152 to increase the power supply voltage according to the high frequency, and when switching from the high frequency to the low frequency, to the power supply voltage supply circuit 13 at the timing, Since the second control signal S152 instructs to lower the power supply voltage according to the low frequency and the power supply voltage is controlled at this timing, the system operation can be guaranteed even if the frequency is switched. The control circuit 15 can control the power supply voltage at an appropriate timing by measuring the time using the timer 14.

[0071]

As described above, according to the present invention,
With the combination of a small number of clock frequencies, there is an advantage that the power consumption can be reduced while realizing the throughput required for the system.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of an electronic circuit system to which a frequency control circuit according to the present invention is applied.

FIG. 2 is a diagram showing a specific configuration example of a clock supply circuit according to the present embodiment.

FIG. 3 is a diagram showing an example of a relationship between a throughput and a clock frequency for realizing this in the present embodiment.

FIG. 4 is a diagram showing a specific configuration example of a timer according to the present embodiment.

FIG. 5 is a timing chart for explaining the operation of the control circuit according to the present embodiment.

FIG. 6 is a flowchart for explaining an operation according to this embodiment.

FIG. 7 is a diagram showing a relationship between throughput and power consumption of the electronic circuit system according to the present embodiment.

FIG. 8 is a diagram showing a relationship between throughput and power consumption of a general electronic circuit system.

FIG. 9 is a diagram showing a relationship between throughput and power consumption in a system including a clock supply circuit capable of generating a plurality of clock frequencies and a power supply voltage supply circuit capable of supplying a power supply voltage according to the clock frequencies. is there.

[Explanation of symbols]

10 ... Electronic circuit system, 11 ... Target circuit, 12
... clock supply circuit, 121 ... phase synchronization circuit (PLL circuit), 122 ... frequency divider, 123 ... selector, 13 ... power supply voltage supply circuit, 14 ... timer, 141 ... counter, 14
2 ... compare register, 143 ... comparator, 15 ...
Control circuit.

Claims (19)

[Claims] 1. A system clock having a clock frequency according to a control signal can be supplied to a target circuit that is capable of supplying a plurality of system clocks having different clock frequencies to achieve different throughputs and that performs processing in synchronization with the system clock. When a throughput T is required and a value of the throughput T and a throughput value that can be realized from the clock frequency that can be generated by the clock supply circuit, two clock frequencies and respective periods are determined, A frequency control circuit having a control means for outputting the control signal for instructing to select two clock frequencies for each determined period and output as the system clock. 2. The frequency control circuit according to claim 1, wherein said control means determines a period for selecting two clock frequencies based on an internal division ratio of throughput. 3. The control means, when a throughput T is required, selects one clock frequency that realizes a throughput of T or more and one clock frequency that realizes a throughput of less than T. Frequency control circuit. 4. The frequency control circuit according to claim 1, wherein the control means selects one clock frequency that achieves a minimum throughput of T or more and one clock frequency that achieves a maximum throughput of less than T. 5. The control means instructs by a control signal to select and output a clock having a higher clock frequency from the selected two clock frequencies.
The frequency control circuit described. 6. The frequency control circuit according to claim 4, wherein the control means instructs by a control signal to output from a clock having a higher clock frequency of the selected two clock frequencies. 7. The frequency control circuit according to claim 1, further comprising a timer capable of setting a measurement time, wherein the control means sets the determined period in the timer to switch clocks of two frequencies. 8. The frequency control circuit according to claim 4, further comprising a timer capable of setting a measurement time, wherein said control means sets the determined period in said timer to switch clocks of two frequencies. 9. The frequency control circuit according to claim 6, further comprising a timer capable of setting a measurement time, wherein said control means sets the determined period in said timer to switch clocks of two frequencies. 10. A system having a clock frequency corresponding to a first control signal to a target circuit capable of supplying a plurality of system clocks having different clock frequencies to achieve different throughputs and performing processing in synchronization with the system clock. A clock supply circuit for supplying a clock, a power supply voltage supply circuit for supplying a power supply voltage having a value corresponding to a second control signal to the target circuit, and a throughput T value and the clock From the value of the throughput that can be realized from the clock frequency that can be generated by the supply circuit, two clock frequencies and their respective periods are determined, and the two clock frequencies are selected for each determined period and output as the system clock. The first control signal is output to the clock supply circuit and the clock A frequency control circuit that outputs the second control signal to the power supply voltage supply circuit so as to supply a power supply voltage that guarantees the operation of the target circuit at each of the two clock frequencies instructed to the supply circuit. . 11. The second control is such that, when an instruction to increase the frequency is issued, the control means previously raises the power supply voltage that can guarantee the operation of the system to the frequency to be changed next. 11. The frequency control circuit according to claim 10, wherein the power supply voltage supply circuit is instructed by a signal, and then the clock supply circuit is instructed by the first control signal to increase the frequency. 12. The control means, when instructing to lower the frequency, instructs the clock supply circuit to lower the frequency by the first control signal, and sets the system to the frequency to be changed next. 11. The frequency control circuit according to claim 10, wherein the power supply voltage supply circuit is instructed by the second control signal so as to reduce the power supply voltage so that the operation can be guaranteed. 13. When the control means gives an instruction to increase the frequency, the second control is performed so that the power supply voltage that can guarantee the operation of the system is increased in advance for the frequency to be changed next. When the power supply voltage supply circuit is instructed by the signal, the clock supply circuit is instructed by the first control signal to increase the frequency, and when the frequency is instructed, the first frequency is set to be low. 11. The power supply voltage supply circuit is instructed by the control signal, and the power supply voltage supply circuit is instructed by the second control signal to lower the power supply voltage that can guarantee the operation of the system for the frequency to be changed next. The frequency control circuit described. 14. The frequency control circuit according to claim 10, wherein the control means determines a period to be selected between the two clock frequencies based on an internal division ratio of throughput. 15. The control means, when a throughput T is required, selects one clock frequency that realizes a throughput of T or more and one clock frequency that realizes a throughput of less than T. Frequency control circuit. 16. The frequency control circuit according to claim 10, wherein the control means selects one clock frequency that achieves a minimum throughput of T or more and one clock frequency that achieves a maximum throughput of less than T. 17. The frequency control circuit according to claim 10, wherein the control means instructs a control signal to select and output a clock having a higher clock frequency from the selected two clock frequencies. 18. The frequency control circuit according to claim 16, wherein said control means instructs by a control signal to output from a clock having a higher clock frequency of the two selected clock frequencies. 19. The frequency control circuit according to claim 10, further comprising a timer capable of setting a measurement time, wherein said control means sets a determined period in said timer to switch clocks of two frequencies.