JP2003134046A - Apparatus and method for transmitting and receiving uplink transmission power offset and high-speed downlink shared channel power level in communication system employing high-speed downlink packet access system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an apparatus and a method for transmitting and receiving uplink transmission power offset and a high-speed downlink shared channel power level in a communication system employing a high-speed downlink packet access system. SOLUTION: An apparatus for controlling uplink transmission power in the high-speed packet data communication system is constituted of a channel condition determiner that measures a signal-to-interference ratio of a first uplink dedicated channel signal received from a UE and calculates a difference between the measured signal-to-interference ratio and a preset target signal-to-interference ratio, a transmission power determiner that compares the difference with preset thresholds and determines an uplink power offset to be applied to a second uplink dedicated channel transmitting control information for packet data received at the UE according to a result of the comparison, and a transmitter that transmits over a downlink the determined uplink power offset to the UE.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to High Speed Downlink Packet Access (H)
More specifically, the present invention relates to an apparatus and method for transmitting and receiving a reverse power offset and a forward common channel power level.

[0002]

2. Description of the Related Art Generally, high-speed data packet connection (Hig
h Speed Data Packet Access: hereinafter referred to as HSDPA) is based on UMTS (Universal Mobile Terrestrial S
In a communication system, a high speed forward downlink common channel (High Speed-Downlink Shared Channel) is a forward data channel for supporting forward high speed packet data transmission.
annel: hereinafter referred to as HS-DSCH) and a control channel related thereto, is a general term for a data transmission method for transmitting high-speed data to a terminal. In order to support the HSDPA scheme, adaptive modulation and coding (Adaptive
Modulation and Coding: hereinafter referred to as AMC) method,
Hybrid Retransmission Reques
t: hereinafter referred to as HARQ) and fast cell selection (F
ast Cell Select: hereinafter referred to as FCS) system has been proposed.

First, the AMC method will be described. The AMC method includes a base station (Node B) and a terminal (User Eq).
uipment: hereinafter referred to as UE) is a data transmission method that improves the overall usage efficiency of the Node B by determining a modulation method and a coding method for different data channels depending on the channel state. Therefore, the AMC scheme has a plurality of modulation and coding schemes (hereinafter referred to as MCS), and a data channel signal is modulated and coded by combining the modulation scheme and the coding scheme. Generally, each combination of the modulation scheme and the coding scheme is referred to as a Modulation and Coding Scheme (hereinafter referred to as MC).
S) and the level (le
(vel) 1 to level n MCSs can be defined. That is, the AMC scheme improves the overall system efficiency of the Node B by adaptively selecting the level of the MCS according to the channel conditions between the UE and the Node B currently in radio connection.

Second, the HARQ system, in particular (especially, n
N-channel Stop And Wai
t Hybrid Automatic Retransmission Request:
n-channel SAW HARQ). The HARQ method uses ARQ (Automatic R
In order to increase the transmission efficiency of the etransmission Request method, the following two schemes are applied. The first method performs an ARQ request and response between the UE and the Node B, and the second method temporarily stores the data in which the error occurs and combines it with the corresponding retransmission data (C).
ombining). Further, the HSDPA method is a conventional Stop-and-wait ARQ (SA) method.
The method called n-channel SAW HARQ was introduced in order to complement the disadvantage of the method (referred to as WARQ). In the SAW ARQ method, Node B
ACK (Acknowledge
ment) is received, the next packet data is not transmitted. Therefore, even if the packet data can be transmitted now,
There is a problem that the Node B has to wait for the ACK. The n-channel SA
In the W HARQ scheme, it is possible to improve channel use efficiency by continuously transmitting a plurality of packet data before receiving an ACK for the previous packet data. That is, n logical channels (Logical Channel) are set between the UE and the Node B,
If the n channels can be identified by a specific time or channel number, the UE may recognize a logical channel on which the packet data is transmitted at any time when the packet data is received. it can. Therefore, the UE can reassemble the packet data according to the reception order or soft combine the packet data.

Finally, the FCS method will be described. The FCS method is a U that uses the HSDPA method.
When E enters a cell overlapping region or a soft handover region, it is a method of quickly selecting a cell having a good channel state among a plurality of cells. Specifically, the FCS method is
The UE using the HSDPA is the previous Node
When entering the cell overlapping area between the B and the new Node B, the UE has multiple cells, that is, multiple Nos.
Set up a radio link with de B. At this time, a set of cells in which a radio link is set with the UE is referred to as an active set. The UE receives packet data for HSDPA only from cells that maintain the best channel state among cells included in the active set in order to reduce overall interference. Here, the cell having the best channel state among the cells in the active set and transmitting the HSDPA packet data is the best cell.
Called. The UE periodically checks the channel state of cells belonging to the active set. The UE is
When a cell having a better channel condition than the current best cell is detected, a best cell indicator (Best Cell Indicat) is added to all cells in the active set to replace the current best cell with a new best cell.
or) is transmitted. The best cell indicator includes an identifier of the selected new best cell. When the cell belonging to the active set receives the best cell indicator, the cell identifier included in the received best cell indicator is analyzed, and the received best cell indicator is the best cell indicator corresponding to itself. Inspect for presence. The result of the inspection,
The cell selected as the best cell transmits packet data to the UE using HS-DSCH.

As described above, the HSDPA system is
In order to support the newly introduced AMC scheme, HARQ scheme and FCS scheme, it is necessary to exchange the following new control signals between the UE and the Node B. First, in order to support the AMC scheme, the UE
Should inform the Node B about the channel condition between the UE and the Node B, and the N
The Node B should use the channel information received from the UE to inform the UE of the MCS level determined by the channel condition. Second, the n
-In order to support the channel SAW HARQ scheme, the UE may send ACK or NACK (Nega (Nega)) to the Node B.
tive Acknowledgment) signal should be transmitted. Third
In order to support the FCS scheme, the UE provides a channel with the best channel condition.
B, that is, the best cell indicator indicating the best cell should be transmitted to the Node B. Furthermore, if the best cell is changed according to the channel condition, the UE should inform the Node B of the packet data reception status at that time, and the Nod
The eB should provide the necessary information so that the UE can select the best cell correctly.

FIG. 1 is a schematic diagram showing a forward channel structure of a communication system using a conventional HSDPA method. Referring to FIG. 1, a downlink dedicated physical channel (hereinafter referred to as DPCH) is an existing code division multiple access (CDMA: Code D).
ivision Multiple Access: hereinafter referred to as CDMA) communication system, for example, a field defined in Release-99, and H received by the UE
It includes an HS-DSCH indicator (HS-DSCH Indicator: hereinafter referred to as HI) indicating the presence or absence of SDPA packet data. The HS-DSCH indicator transmitted through the forward DPCH informs a corresponding UE whether or not HSDPA packet data is received. Further, the HS-DSCH indicator may be the HSD.
If PA packet data exists, the H
HS-DS where SDPA packet data is actually transmitted
Common control channel (S
Hared Control Channel: Hereinafter, a channelization code of SHCCH is notified.
Further, if necessary, a part of the HS-DSCH control information, for example, control information such as MCS level may be transmitted to the HS.
-Can be transmitted through the DSCH indicator.

For example, when the HSDPA packet data is transmitted in a cycle of N (= N ₁ + N ₂ ) slots (that is, HSDPA transmission time interval (Transmission Time Inter
val: hereafter referred to as TTI) = N slots), said TTI
If the slot structure is fixed in the
The HS-DSCH indicator is transmitted by being divided into N ₁ slots and the H in the remaining N ₂ slots.
The part that transmits the S-DSCH indicator is processed by discontinuous transmission (DTX). In FIG. 1, the HS is transmitted through one slot.
If the DSCH indicator is transmitted, ie N
Assume that ₁ = 1.

The Node B is an MCS level which is information for controlling the HS-DSCH (hereinafter referred to as HS-DSCH control information), an HS-DSCH channelization code,
A HARQ processor number, a HARQ packet number, etc. are transmitted to the UE through the SHCCH. Hereinafter, the HS-DSCH control information will be described. (1) MCS level: Indicates a modulation method and channel coding method used by HS-DSCH. (2) HS-DSCH channelization code: HS-DSCH
Is the channelization code used by the particular UE for the particular UE. (3) HARQ processor number: n-channel S
When the AW HARQ method is used, it indicates a channel belonging to a specific packet among logical channels for the HARQ method. (4) HARQ packet number: A unique number of downlink packet data so that the UE can notify the newly selected best cell of the transmission state of HSDPA data when the best cell is changed in the FCS method. To the UE.

The SHCCH can be assigned one or more channelization codes. The HS
-DSCH is a channel for transmitting HSDPA packet data transmitted from the Node B to the UE. In FIG. 1, before the UE reads the HS-DSCH indicator and detects corresponding information,
Since it cannot recognize whether the remaining two channels are data corresponding to the UE, the forward direction D
The start time of the PCH is the SHCCH and the HS-DS.
Earlier than the start of CH. Therefore, since the UE should temporarily store data in the buffer, the UE may receive the remaining two channels by giving enough time to read the HS-DSCH indicator. The load on the buffer is reduced. As a result, the UE may change the HS of the forward DPCH.
Check if there is HSDPA packet data that it receives by reading the DSCH indicator. When there is HSDPA packet data to be received, the UE may use the HS-DSCH of the SHCCH.
After reading the control information, the HS-
The HSDPA packet data is received through the DSCH.

FIG. 2 is a diagram showing a forward DPCH structure of a communication system using a conventional HSDPA method.
Referring to FIG. 2, the forward DPCH is an existing HSDP.
A CDMA communication system that does not support A, eg, Rel
It has a structure of a forward DPCH defined in ease-99, and the structure has the following fields. The Data1 and Data2 fields carry data for supporting the operation of an upper layer or data for supporting a voice-only service. Transmission power control
(Transmission Power Control: hereinafter referred to as TPC)
The field transmits a forward TPC command for controlling the uplink transmission power, and the Transmission Format Combination Indicator (hereinafter, referred to as TFCI) field is used for the Data1.
And TFCI information of the Data2 field is transmitted.
The Pilot field is a field that carries a pilot symbol sequence predefined by the system, and is used by the UE to estimate the forward channel condition. HS-D for the HSDPA service
As shown in FIG. 2, the SCH indicator indicates that the existing Re
It is transmitted to the UE through a newly defined field in the lease-99 forward DPCH.

FIG. 2 shows a case where the HS-DSCH indicator is transmitted through a newly defined field in an existing forward DPCH. However, FIG. 3 shows a case where the HS-DSCH indicator is transmitted through a new forward DPCH instead of a specific field of the existing forward DPCH.

FIG. 3 shows another example of the forward DPCH structure of a communication system using the conventional HSDPA method.
Referring to FIG. 3, the HS-DSCH indicator is transmitted through a new forward DPCH that assigns a separate channelization code instead of a specific field in the existing forward DPCH. Two forward DPCs
H, that is, a first dedicated physical channel (Primary DPCH: hereinafter referred to as P-DPCH) and a second dedicated physical channel
(Secondary DPCH: hereinafter referred to as S-DPCH) is assigned. Here, since the S-DPCH for transmitting the HS-DSCH indicator has a different amount of data to be transmitted from the P-DPCH, the P-DPCH has a spreading factor (hereinafter, referred to as SF). The value N is assigned and the SF value M is assigned to the S-DPCH. When the amount of data of the transmitted HS-DSCH indicator is small, by setting the SF value M of the S-DPCH to a relatively large value, for example, M = 512,
The efficiency of use of the forward channelization code can be improved.

FIG. 4 is a diagram showing a reverse DPCH structure of a communication system using a conventional HSDPA method.
Referring to FIG. 4, an existing CDMA communication system, for example, a Dedicated Physical Data Channel (hereinafter, referred to as DPDCH) and a Dedicated Physical Control Channel (Dedicated Physical Control Channel) for supporting Release-99. : Below, D
PCCH) and a high-speed dedicated physical control channel (High Speed Dedicated) for supporting the HSDPA.
Physical Control Channel: hereinafter referred to as HS-DPDCH), a separate channelization code is assigned and transmitted independently. In the reverse direction (uplink), the orthogonal variable spreading factor (Orthogonal Variable length Sp
(reading Factor: hereinafter referred to as OVSF) code is allocated, so that channelization code resources are sufficient. When modifying the existing reverse control channel, compatibility with the existing system may be problematic and the complexity of the channel structure may be increased. Therefore, rather than modifying the channel structure, it is preferable to define a new reverse control channel by using a separate new channelization code.

One frame of the reverse DPDCH (f
UE and Node B through slots that make up a rame)
The upper layer data transmitted from the above is transmitted, and slots constituting one frame of the reverse DPCCH are pilot (Pilot) symbols, TFCI symbols, feedback information (Feed Back Information: hereinafter referred to as FBI) symbols, and It is composed of TPC symbols. The pilot symbol is transmitted from the UE to the No.
It is used as a channel estimation signal when demodulating data transmitted to de B. The TFCI symbol is a TFC (Transmission Format C) used for data transmission by a channel transmitted during a current frame.
combination). The FBI symbol carries feedback information when a transmission diversity technique is used. The TPC symbol is a symbol for controlling the transmission power of the forward channel. The reverse DPCCH is transmitted after being spread using the OVSF code, and the SF used at this time is fixed to 256.

In the HSDPA, the UE is Nod
e B, the data received from E B is checked for an error, and A
Transmit CK or NACK. The ACK and NAC
K is an HS-DPCC for supporting the HSDPA.
Transmitted through H. If the UE does not need to send an ACK / NACK to the Node B because there is no data received, the UE may use the Node through the HS-DPCCH to support AMC scheme.
Channel Quality Information:
CQI) or other information such as a best cell indicator indicating a Node B providing the best channel to the UE through the HS-DPCCH to support the FCS scheme. As shown in FIG. 4, HS-DP for the HSDPA service is provided.
When the DCH is assigned to another channelization code, the same transmission power control as the existing DPCCH is performed. That is, the DPCCH and the HS-DPCCH
Has a constant power ratio, and when the transmission power of the DPCCH is increased or decreased, the transmission power of the HS-DPCCH is also increased or decreased.

Next, the AMC method for the HS-DSCH will be described with reference to FIGS. 5A to 5C.
5A to 5C show an AMC scheme for HS-DSCH in a communication system using a general HSDPA scheme. FIG. 5A shows QPSK (Quadrature Phase Shift Key).
ing: Hereinafter, referred to as QPSK)
nstellation). The QPSK modulation method is shown in FIG.
As shown in (2), this is a method in which two transmission bits are converted into one complex number signal. For example, it is a method of modulating the bit “00” into a complex signal “1 + j”. Here, the four complex signals have the same transmission power level because they are located in a circle centered on the origin. On the other hand, the receiver uses the quadrant of the QPSK-modulated signal among the quadrants formed by the X-axis and the Y-axis on the signal constellation to determine the QPS.
Demodulate the K modulated signal. For example, if the received QPSK modulated signal is in one quadrant, the transmitted signal is demodulated to bits "00". That is, in the QPSK modulation method, the decision line of the transmission signal is the X axis and the Y axis.

FIGS. 5B and 5C show 16QAM (Quadr) for modulating / demodulating four transmission bits into one complex number signal.
ature Amplitude Modulation: Hereinafter referred to as QAM)
5C shows the signal constellation diagram of FIG. 5C, in which the channel gain of HS-DSCH is larger than that of FIG. 5B. Since the channel gain of the HS-DSCH of FIG. 5C is larger than that of FIG. 5B, the distance of the complex number signal from the origin on the signal constellation diagram of FIG. 5C is larger than the distance of the complex number signal from the origin on the signal constellation diagram of FIG. 5B. 16 QAM (16-ary QAM) modulates 4 bits into one complex number signal corresponding to a signal constellation,
The signal modulated by the 16QAM method is shown in FIG.
And the decision region (Decisio) formed by the dotted line in FIG. 5C.
n boundary). As shown in FIGS. 5A to 5C, since the 16QAM-modulated signal has a decision line that differs depending on the channel gain at the time of demodulation, the receiver transmits the signal to demodulate the 16QAM-modulated signal. Should recognize the channel gain of the vessel. Of course, in the QPSK method, since the decision line is determined regardless of the transmission power, the receiver can perform demodulation without knowing the channel gain of the transmitter. Therefore, the N-ary QAM (NQAM) method requires a process of transmitting control information indicating a channel gain from a transmitter or a Node B to a receiver or a UE. That is, the control information related to the channel gain transmitted from the Node B to the UE is “HS-DSCH”.
"HS-DSC" referred to as "power level".
H power level is HS-DSCH for one code
Power and Common Pilot Channel:
Hereinafter, it is referred to as CPICH. Ratio to power (or dB)
It is defined as the power difference in units. The HS-DSCH power for the one code is a power that can be allocated to a specific UE divided by a specific channelization code among the total power allocated for the HSDPA service.

FIG. 6 shows a method for determining the HS-DSCH power level in a communication system using the conventional HSDPA method. Referring to FIG. 6, the HS-DS
In order to express the CH power level by P bits, the transmittable power of the HS-DSCH for one code is divided into 2 ^P regions defined from the transmission power 0 to the CPICH power (CIPCH power). In FIG. 6, the HS-DS
In order to express the CH power level by 2 bits, the HS
-The DSCH power level is divided into four areas (1), (2), (3) and (4). For example, if the HS-DSCH transmission power for one channelization code belongs to the region (2), the Node B sets the HS-DSCH power level to A, and the bit "10" indicating the HS-DSCH power level A. Is transmitted through the downlink. In general, CPICH should be transmitted to the entire cell, so CPICH power is much higher than HS-DSCH power for one channelization code. Therefore, HS-DSCH power and CPI for one channelization code
If the difference with the CH power is large, multiple transmission bits are required to accurately represent the HS-DSCH power level. Therefore, in order to demodulate the QAM modulated signal from the UE, a method of determining the HS-DSCH power level by the Node B is required. Furthermore, the H
A scheme for transmitting information about the S-DSCH power level to the UE is required.

As described with reference to FIG. 4, when the DPCCH and the HS-DPCCH are transmitted (or controlled) at a constant power ratio, a problem of transmission power may occur. This will be explained with reference to FIG.

FIG. 7 is a schematic diagram showing a channel allocation structure in the case where a UE exists in a soft handover region in a communication system using a normal HSDPA system. FIG. 7 shows a channel allocation structure in the case where one UE is located in a soft handover area which is served by K Node Bs. If the UE has Node B # 1 to HSDP
Even if the UE is located in the soft handover area while receiving the A service, the UE may receive a new Nod.
It is not necessary to receive HSDPA service from all Node Bs including eB. That is, if the channel state is poor while continuously receiving packet data from the Node B # 1, the UE may be assigned to another Node B having the best channel condition, that is, the best cell to the UE itself. After informing the packet data transmission status and then disconnecting from the Node B # 1, the new Node B having the best channel environment can be sent to HSDP.
A handover (hard handov)
er). As a result, the UE has one Nod.
Only e B receives packet data for the HSDPA service. However, voice services
As shown in FIG. 7, the UE receives a channel for the HSDPA service from the Node B # 1 and performs a voice call since the UE performs an existing soft handover to maintain connection with a plurality of Node Bs. Channel for service, ie existing Release-99D
PCH to all Nos in the soft handover area
It is received from de B (Node B # 2 to Node B # K). In addition, the UE may use all N in the uplink.
The DPDCH and DPCCH are transmitted to the Node B,
The HS-DPCCH including HSDPA service related information such as ACK / NACK is transmitted only to the Node B # 1 that receives the HSDPA service.

The transmission power control by the UE for the Node B applying the existing Release-99 scheme is as follows. Node B is the reverse DPC
The signal-to-interference ratio (Signa
l-to-Interference Ratio: hereinafter referred to as SIR), and the measured SIR is the target SIR.
Compare with. According to the result of the comparison, if the measured SIR is smaller than the target SIR, the Node
B transmits a power increase command for reverse transmission power to the UE through the TPC field of the forward DPCH. On the contrary, if the measured SIR is greater than the target SIR, the Node B determines the forward DPC.
A power reduction command for reverse transmission power is transmitted to the UE through the TPC field of H. Here, the fact that the measured SIR is smaller than the target SIR means that the channel condition is bad, and thus the Node B transmits a power increase command for reverse transmission power. . On the contrary, if the measured SIR is larger than the target SIR, it means that the channel condition is relatively good, so that the power reduction command for the reverse transmission power is transmitted.

In FIG. 7, the UE also controls the reverse channel transmission power in the same manner as in Release-99. Specifically, all Nodes
If at least one of the reverse transmission power control commands transmitted from B through the TPC field of the forward DPCH includes a power reduction command for reverse transmission power, the UE decreases the reverse transmission power. For example, Nod
If the reverse channel environment for e B # 1 is bad, the Node B # 1 may issue a power increase command for reverse transmission power to the UE, but the N
N of one of the other Node Bs other than the Node B # 1
Even in the node B, when the power reduction command for the reverse transmission power is transmitted to the UE, the UE reduces the reverse transmission power. Therefore, as shown in FIG. 7, even if the Node B # 1 providing the HSDPA service continuously issues a power increase command for the reverse transmission power, the transmission power of the reverse DPCCH is reduced by another Node B. There is a possibility that the transmission power of the HS-DPCCH performing power control while maintaining a constant ratio with the reverse DPCCH may be reduced.

When the UE is located in the soft handover area, the reverse DPDCH and DPCCH for the Release-99 are transmitted to all Node Bs and combined in the upper layer to obtain the soft handover effect. You can In this case, no problem occurs even if the transmission power is reduced to some extent. However, the ACK required for the HSDPA service
The HS-DPCCH of FIG. 4 carrying / NACK or other control information for the HSDPA service is only one.
Since the data is transmitted to only one Node B, that is, Node B # 1, the reliability decreases as the reverse transmission power decreases.

[0025]

Therefore, an object of the present invention is to provide a communication system using the HSDPA system,
An object of the present invention is to provide an apparatus and method for controlling transmission power of a reverse HS-DPCCH.

Another object of the present invention is to provide a reverse HS-DPCCH in a communication system using the HSDPA system.
It is an object of the present invention to provide an apparatus and a method for determining a transmission power offset for controlling the transmission power of a signal.

Another object of the present invention is to provide reverse HS-DPC in a communication system using the HSDPA system.
An object of the present invention is to provide an apparatus and method for transmitting a transmission power offset determined to control the transmission power of CH.

Another object of the present invention is to provide an apparatus and method for determining the power level of HS-DSCH in a communication system using the HSDPA method.

Another object of the present invention is to provide an apparatus and method for transmitting the power level of HS-DSCH in a communication system using the HSDPA system.

[0030]

According to a feature of the present invention for solving the above-mentioned object, there is provided an apparatus for controlling reverse transmission power in a high speed packet data communication system. The apparatus measures a signal to interference ratio of a first reverse dedicated channel signal received from a UE and calculates a difference between the measured signal to interference ratio and a preset target signal to interference ratio. Applied to the second reverse dedicated channel for comparing the difference with a preset threshold value and transmitting control information for packet data received by the UE according to the comparison result. And a transmitter for determining the reverse power offset to be transmitted to the UE through the forward direction.

According to another aspect of the invention, there is provided an apparatus for transmitting a forward data channel power level in a high speed packet data communication system. The apparatus is a modulation scheme determiner that determines a modulation scheme to be applied to a forward data channel that transmits packet data according to a channel state set with the UE, and the determined modulation scheme is a high-order modulation scheme. In this case, the forward data channel power level determiner determines a forward data channel power level, which is channel gain related control information of the forward data channel, and the UE through the determined forward data channel power level in the forward direction. And a transmitter that causes the UE to demodulate the packet data using the forward data channel power level.

According to yet another aspect of the invention, there is provided a method of controlling reverse transmit power in a high speed packet data communication system. The method comprises measuring a signal-to-interference ratio of a first reverse dedicated channel signal received from a UE and a difference between the measured signal-to-interference ratio and a preset target signal-to-interference ratio. And comparing the difference with a preset threshold value, and according to a result of the comparison, a reverse direction applied to a second reverse direction dedicated channel for transmitting control information for packet data received by the UE terminal. The process comprises determining a power offset and transmitting the determined reverse power offset to the UE in the forward direction.

According to yet another aspect of the invention, there is provided a method of transmitting a forward data channel power level in a high speed packet data communication system. A process of estimating a channel state set as a UE and determining a modulation scheme applied to a forward data channel for transmitting packet data according to the estimated channel state, and the determined modulation scheme is a high-order modulation And a method of determining a forward data channel power level that is channel gain related control information of the forward data channel, and transmitting the determined forward data channel power level to the UE through the forward direction. , Causing the UE to demodulate the packet data using the forward data channel power level.

[0034]

Preferred embodiments according to the present invention will be described in detail below with reference to the accompanying drawings. In the following description, for the purpose of clarifying only the gist of the present invention,
A detailed description of related known functions or configurations will be omitted.

FIG. 8 shows an HSD according to an embodiment of the present invention.
HS-DSC in a communication system using the PA method
It is a figure which shows the method of determining H power level. HSDP
In a communication system using the A system, HS-DSC
The power level of H is equal to one channelization code as described in the above-mentioned prior art.
HS-DSCH power and common pilot channel for
(Common Pilot Channel: hereinafter referred to as CPICH) It is defined as a ratio to power (or power difference in dB). As described in FIG. 6, when the power difference between the HS-DSCH power and the CPICH for one channelization code is large, a plurality of transmission bits are required to accurately represent the HS-DSCH power level. However, since the CPICH is a channel transmitted to the entire cell, the situation in which the HS-DSCH power level for one channelization code actually increases to the CPICH power level rarely occurs. Therefore, in the embodiment of the present invention, the HS-DSCH is used.
HS-DSCH for one channelization code without determining the power level based on the CPICH power level
A method of making a decision based on the maximum level of power is provided.
Of course, HS-for the one channelization code
The minimum level of power on the DSCH is never zero in actual radio channel conditions. Therefore, in the embodiment of the present invention, the HS-DS for one channelization code is used.
HS- using the minimum and maximum levels of CH power
Determine the DSCH power level.

Referring to FIG. 8, in order to transmit the HS-DSCH power level by P bits, the transmission power of the HS-DSCH power for one channelization code is H.
2 between minimum level and maximum size of S-DSCH power
^It is divided into ^P areas. In FIG. 8, the HS-
It is illustrated that the DSCH power level is transmitted by 2 bits. Therefore, in order to transmit the HS-DSCH power level by 2 bits, the HS-DSCH power level may be between (5) to (5) between the minimum level and the maximum level of the HS-DSCH power for one channelization code. 8) It is divided into regions. For example, if the HS-DSCH power for the one channelization code belongs to region (5) No
de B sets the HS-DSCH power level to B,
Bit "1" corresponding to the HS-DSCH power level B
1 ″ is transmitted in the downlink. As a result, it is possible to transmit a precise HS-DSCH power level using the same number of bits as used in the prior art. The UE accurately determines the HS-DSCH power level required for demodulation of the signal modulated by the QAM scheme, and improves the reliability of the QAM demodulation.

Meanwhile, the UE receives the bit indicating the HS-DSCH power level transmitted by the Node B, and receives the HS- for one channelization code.
Detect DSCH power level. Here, the UE is
It is necessary to make a contract with the Node B in advance regarding the minimum level and the maximum level of the HS-DSCH power, and the minimum level and the maximum level of the HS-DSCH power are transmitted to the UE as upper layer control information.
Further, the Node B predetermines the maximum transmit power and the assignable channelization code for the HSDPA of the total transmit power that can be transmitted through the cell. Therefore, when the Node B also transmits the two pieces of information as higher layer control information to the UE, the UE may use the HS-DSC for one channelization code.
The maximum level of H power can be identified. The details are as follows.

The Node B has H out of the total transmission power.
Suppose we have a transmit power S for SDPA and a maximum number N of channelization codes. If Node B allocates the same power for all channelization codes,
The power for one channelization code is S / N.
However, in the actual situation, the channel situation or the Modulation and Coding Scheme:
Hereinafter, power is allocated to the corresponding channelization code according to the (MCS) level, so that the same transmission power is not allocated to all the channelization codes. For example,
HS-DSC in which Node B is modulated by the QPSK method
Low transmission power is assigned to H, and high transmission power is assigned to HS-DSCH modulated by the QAM method. Therefore, the Node B variably allocates the transmission power for one channelization code by S (K / N). Here, the K is a variable value for variably assigning the transmission power between the HS-DSCH. Since it is not possible to allocate the total transmit power for the HSDPA to only one channel, the possible values of K are limited to limit the maximum power level for one channelization code. Similarly, the UE also receives the HSD from the Node B.
HS-DSCH for one channelization code by calculating the S (K / N) upon receiving upper layer information including the total transmission power for PA, the number of channelization codes that can be allocated, and the K value. Can recognize the maximum level of power.

FIG. 9 illustrates an HSDP according to an embodiment of the present invention.
FIG. 3 is a diagram showing a forward channel structure of a communication system using the A system. Referring to FIG. 9, as described with reference to FIG. 1, a channel capable of transmitting transmission power is a downlink (downlin) channel.
k) DPCH (Dedicated Physical Channel) and HS-D
It includes SHCCH (Shared Control Channel) for controlling SCH (High Speed-Downlink Shared Channel). However, since the SHCCH previously transmits control information such as the MCS level, HARQ processor number, and HARQ packet number for the HSDPA service, there is no room to transmit other control information.

However, as described in FIG. 1, one transmission time interval (hereinafter, T)
(Referred to as TI) has N (= N ₁ + N ₂ ) slots, the HS-DSCH indicator (HI) is transmitted in N ₁ slots and the HS-DSCH indicator (HI) is transmitted in the remaining N ₂ slots.
The part that transmits the DSCH indicator is discontinuous transmission
(DTX) is processed. Therefore, the HS-DSCH power level can be separately transmitted through the HS-DSCH indicator part of the slot that does not transmit the HS-DSCH indicator in the DPCH.
Since the position of the slot for transmitting the HS-DSCH indicator is variable, the position of the slot for transmitting the HS-DSCH transmission power level is also variable. Further, the HS-DSCH power level is set to No in the TTI cycle.
H that can be transmitted from de B to the UE and is transmitted
If there are many bits indicating the S-DSCH power level, it may be transmitted in slot periods or frame units. In FIG. 9, the first slot in the TTI (slot #
The HS-DSCH indicator is transmitted only in 0), and through the HS-DSCH indicator part of the second slot (slot # 1) and the Nth slot (slot # N-1) of the remaining (N-1) slots. The HS-DSCH power level is transmitted. Other forward channels, SHCCH and H
The S-DSCH has the same structure as the structure described in FIG. Meanwhile, the HS-DSCH power level is HSD.
Since it is a value for notifying the transmission power of HS-DSCH for PA, when the UE receives the HSDPA service, only when the HSDPA service data is present, that is, the HS-DSCH indicator is present,
Further, it is transmitted only when the HSDPA data is modulated by the QAM method. H determined by FIG.
If the number of bits indicating the S-DSCH power level is K bits and the number of bits that can be transmitted over N-1 slots is n bits as shown in FIG. 9, the HS-DSC is used.
H power level is (n, k) block code
It can be transmitted using an error correction code such as

FIG. 10 shows H according to another embodiment of the present invention.
Forward DPCH of communication system using SDPA method
It is a figure which shows a structure. Referring to FIG. 10, DPCH
Includes a structure of a CDMA communication system that does not support the existing HSDPA service, for example, a forward DPCH as defined in Release-99, and the structure has the following fields. Data1 and Dat
The a2 field transmits data for supporting the operation of the upper layer or data for supporting the voice-only service. Transmission power control
rol: The TPC field is the reverse (upl) field.
ink) Transmits the forward TPC command to control the transmission power and displays the transmission format combination (Transmission Format
Combination Indicator: hereinafter referred to as TFCI) field transmits the TFCI information of the Data1 and Data2 fields. The Pilot field is
A field that carries a pilot symbol sequence predefined by the system and is used by the UE to estimate the forward channel condition. The HSDPA
The HS-DSCH indicator for service and the HS-DSCH power level are transmitted to the UE through a newly defined field in the existing Release-99 forward DPCH, as shown in FIG. Figure 1
0 is the HS-DSCH indicator and the HS-
FIG. 6 shows a case where the DSCH power level is transmitted through a newly defined field in an existing forward DPCH.

On the other hand, referring to FIG. 11, the HS-D
6 illustrates a case where the SCH indicator and the HS-DSCH power level are not transmitted through a specific field in the existing forward DPCH, but through a new forward DPCH.

FIG. 11 shows H according to another embodiment of the present invention.
Forward DPCH of communication system using SDPA method
It is a figure which shows a structure. Referring to FIG. 11, the HS-
The DSCH indicator or the HS-DSCH power level is transmitted through a new forward DPCH that assigns a separate channelization code instead of a specific field in the existing forward DPCH. Two forward DPs
CH, that is, the first dedicated physical channel (Primary DPCH:
Hereinafter, P-DPCH) and a second dedicated physical channel (Secondary DPCH: hereinafter S-DPCH) are allocated. Here, S for transmitting the HS-DSCH indicator or the HS-DSCH power level.
-DPCH has the same amount of data as the P-DPCH.
Therefore, the P-DPCH has a spread coefficient (Spreadi).
ng Factor: hereinafter referred to as SF) value N is assigned, and SF value M is assigned to the S-DPCH. The transmitted HS-DSCH indicator or the HS-DSC
When the data amount of the H power level is small, the S-DPC
The SF value M of H is a relatively large value, for example, M = 512.
The use efficiency of the forward channelization code can be improved by setting to.

So far, the channel structure for transmitting the HS-DSCH power level through the forward DPCH has been described with reference to FIGS. 10 and 11. Next, FIG.
, The HS-DSCH using SHCCH
A channel structure for transmitting power levels will be described.

FIG. 12 shows H according to another embodiment of the present invention.
It is a figure which shows the SHCCH structure of the communication system which uses SDPA system. Referring to FIG. 12, the SHCC controlling the HS-DSCH as described in FIG.
H is an HS-DSCH channelization code, said HS-D
MCS level indicating the modulation and channel coding scheme used in SCH, and HARQ information, that is, HA
The RQ processor number and HARQ packet number are transmitted. Some of the fields for transmitting the control information are defined as fields for transmitting the HS-DSCH power level. M of the control information
If the CS level indicates that the HS-DSCH is modulated by the QAM scheme, the HS-DSCH power level value is transmitted through the SHCCH. The HS
If the DSCH is not modulated by the QAM scheme, the field carrying the HS-DSCH power level is DTX processed or a dummy field is added to the field.
my) bit is inserted. Generally, the HS-DSC
If H is not modulated by the QAM scheme, this means that the channel conditions are bad. Therefore, HARQ information requiring high reliability can be transmitted through the field in which the HS-DSCH power level is transmitted.

In FIG. 12, (a) shows the HS-DS.
HS-DSC when CH is modulated by QAM method
H channelization code and other information, MCS level, HA
S for transmitting RQ information and HS-DSCH power level
The HCCH structure is shown. Next, in (b), the MCS level does not need to transmit the HS-DSCH power level, or a QPSK method or 8-PSK (8-ary Phase Shift Keyin).
g) When indicating modulation, a SHCCH structure for performing DTX processing on a field for transmitting the HS-DSCH power level or inserting a dummy bit in the field is shown.
Finally, (c) means that when the QAM scheme is not used, this means that the channel condition is bad.
The original HARQ control information field is set to the HS-DSCH.
7 illustrates a transport SHCCH structure for transporting HARQ related control information by extending to a field for transporting a power level. FIG. 12 shows the HS-D in the forward DPCH.
The SCH indicator field indicates a channel structure, but the HS-DS is transmitted through another channel to which a channelization code different from that of the DPCH is assigned.
It is also possible to use a channel structure in which the CH indicator is transmitted.

FIG. 13 shows an HSD according to an embodiment of the present invention.
FIG. 1 is a block diagram showing a transmitter structure of a Node B of a communication system using a PA method, in particular, one DPC.
HS-DSCH indicator and HS-D using H
2 shows a Node B transmitter structure for transmitting SCH power level.

Referring to FIG. 13, HS-DSCH data packet (or HSDPA data packet) 130.
1 is input to the encoder 1302. The encoder 1302 uses a preset coding method,
For example, the HS-DSCH data packet is encoded by a turbo coding method to generate an encoded symbol, and the generated encoded symbol is provided to a rate matcher 1303. The rate matcher 1303 may perform symbol repetition and puncturing to transmit a signal in TTI.
The signal output from the encoder 1302 through (puncturing) is symbol rate matched (rate match i).
ng) and provides the rate-matched signal to an interleaver 1304. The interleaver 1304 includes a rate matching unit 1303.
The signal output from the
ator) 1305. The modulator 1305 modulates the signal output from the interleaver 1304 with a preset modulation method, that is, QPSK, 8PSK, M-.
It is modulated according to the ary QAM method and is converted into a serial to parallel converter in the form of a bit stream.
arallel converter) 1306. The serial / parallel converter 1306 parallel-converts the received bitstream into two bitstreams, that is, a bitstream I and a bitstream Q, and a spreader.
r) 1307. The spreader 1307 has orthogonality between the two bit streams output from the serial / parallel converter 1306 and another signal using another channelization code, using the same channelization code C _OVSF. The spread bit stream I is provided to the adder 1309, and the bit stream Q is provided to the multiplier 1308. The multiplier 1308
Multiplies the bit stream Q by j to adder 1
309 to provide. The adder 1309 outputs the signal output from the multiplier 1308 and the bit stream I
Are added to generate one complex bit stream, and the generated complex bit stream is multiplied by a multiplier 1310.
To provide. The multiplier 1310 is the adder 130.
The signal output from 9 is multiplied by a preset scrambling code C _SCRAMBLE to scramble
(scrambling) and outputs the output to the multiplier 1311. Here, the multiplier 1310 is a scrambler (s).
crambler). The multiplier 1311 outputs the signal output from the multiplier 1310 with a channel gain of 1
It is multiplied by 312 and provided to the adder 1343. Here, the channel gain 1312 is a parameter that determines the power level of the HS-DSCH, has a large value when the SF is small, and varies depending on the type of user data to be transmitted. When the HS-DSCH data is modulated by the QAM scheme in the modulator 1305, the Node B may determine the HS-DSCH power level for the channelization code so that the UE can efficiently perform QAM demodulation. To the UE. Further, the HS-DSCH power level determiner 1315
Is the HS-DSC from the channel gain 1312.
H-power and HS-D for one channelization code
HS using maximum and minimum levels of SCH power
-Determining the DSCH power level and determining the determined HS-
Generate bit 1321 corresponding to the DSCH power level.

User data 1316 transmitted through the DPCH is input to the encoder 1317. The encoder 1317 encodes the user data 1316 according to a preset coding method and outputs the encoded user data 1316 to the rate matching unit 1318. The rate matching device 13
18 performs rate matching on the signal output from the encoder 1317 by symbol repetition or puncturing, so that the number of output bits corresponds to the number of bits actually transmitted through a physical channel. Matching is performed and the rate-matched signal is provided to the interleaver 1319. The interleaver 1319 includes the rate matching unit 131.
The signal outputted from the signal No. 8 is interleaved by a preset method and outputted to the modulator 1320. The modulator 1320 modulates the signal output from the interleaver 1319 according to a preset modulation method and provides the modulated signal to a multiplexer 1327. The multiplexer 1327 has an HS-DSCH indicator 1322 whose transmission time is divided by a switch 1323.
And HS-DSCH power level 1321, TFCI13
24, Pilot for estimating the forward channel state
1325 and TPC 13 for reverse transmit power control
By multiplexing 26, one bitstream is generated and the generated bitstream is provided to the serial / parallel converter 1328. Here, the switch 132
3 is the HS-DSCH indicator 1 at the time when the HS-DSCH indicator 1322 is to be transmitted.
322 to the HS-DSCH power level 13
21 is connected to the HS-DSCH power level 1321 at the time when it should be transmitted, so that the HS-DSC is
The transmission time of the H indicator 1322 and the HS-DSCH power level 1321 is controlled.

The serial / parallel converter 1328 converts one bit stream output from the multiplexer 1327 into two bit streams, that is, a bit stream I and a bit stream Q, and spreads them.
9 to provide. The spreader 1329 is composed of two multipliers, and provides the two bitstreams output from the serial / parallel converter 1328 to the two multipliers, respectively, so that the bitstreams are used for other channels. The spread bit stream I and the spread bit stream Q are multiplied by the channelization code C _OVSF so as to have orthogonality with other signals using the spread code.
To generate. Here, the spreader 1329
Multiplies the spread bit stream Q by a multiplier 133.
0, and the spread bitstream I is provided to the adder 1331. The multiplier 1330 multiplies the bit stream Q output from the spreader 1329 by j and provides the result to the adder 1331. The adder 13
31 adds the multiplier 1330 to the bit stream I.
The signals output from are added to generate one complex bit stream, and the generated complex bit stream is provided to the multiplier 1332. The multiplier 1332
Supplies the complex number bit stream output from the adder 1331 with a scrambling code C _{SCRAM BLE} on a chip-by-chip basis to scramble, and provides the output to the multiplier 1333. Here, the multiplier 1332 operates as a scrambler. The multiplier 1333 multiplies the signal output from the multiplier 1332 by the channel gain 1334 and provides the result to the adder 1343.

On the other hand, HS-DSCH control information 1335
Is input to the serial / parallel converter 1336. The serial / parallel converter 1336 converts the HS-DSCH control information 1335 into two bitstreams and outputs the bitstreams to the spreader 1337. The spreader 1337 is composed of two multipliers, and the two bit streams are input to the two multipliers, respectively, and the channelization code C is input.
_The spread bitstream I multiplied by _OVSF
And generate a spread bitstream Q. Here, the spreader 1337 provides the spread bitstream Q to the multiplier 1338 and the spread bitstream I to the adder 1339. The multiplier 1338 multiplies the bit stream Q output from the spreader 1337 by j and provides the result to the adder 1339. The adder 1339 outputs the bitstream I
To generate a single complex bitstream and provide it to the multiplier 1340. The multiplier 1340 scrambles the complex bit stream output from the adder 1339 in chip units.
_It is multiplied by _SCRAMBLE and scrambled, and its output is provided to the multiplier 1341. Here, the multiplier 134
0 acts as a scrambler. The multiplier 13
41 multiplies the signal output from the multiplier 1340 by a channel gain 1342 and outputs the signal to the adder 1343. The adder 1343 outputs the generated DPCH signal (that is, the signal output from the calculator 1333) and the generated SHCCH signal (that is, the multiplier 13
41, and the generated HS-
The DSCH signal (that is, the signals output from the multiplier 1311 are summed and provided to the filter 1344. The filter 1344 filters the signal output from the summer 1343 to perform RF (Radio Frequency).
ency) processor 1345 to provide the RF processor 134.
5 outputs the signal output from the filter 1344 to RF
It is converted to a band signal and transmitted on the air through the antenna 1346.

As described with reference to FIG. 11, the HS
If the DSCH indicator and the HS-DSCH power level are transmitted through a separate DPCH, that is, the S-DPCH, the Node B of FIG.
H, that is, the channelization code that is distinguished from the channelization code used for P-DPCH is the S-DP
It should be changed to assign to CH.

Up to now, referring to FIG. 13, the HS-D
The transmitter structure of the Node B that transmits the SCH indicator and the HS-DSCH power level through the DPCH has been described. Next, the transmitter structure of the Node B that transmits the HS-DSCH indicator and the HS-DSCH power level through SHCCH will be described with reference to FIG.

FIG. 14 shows an H according to another embodiment of the present invention.
Node in a communication system using the SDPA method
It is a block diagram which shows the transmitter apparatus structure of B. Since the operation of the components represented by reference numerals 1401 to 1415 in FIG. 14 is the same as the operation of the components represented by reference numerals 1301 to 1315 in FIG. 13, detailed description thereof will be omitted.

HS-DSCH power level determiner (power l
HS-D determined by evel determiner 1415
The SCH power level 1418 is the HS-DSCH channelization code and other control information 1416, the MCS level 14
17 and HARQ control information 1419 together with multiplexer 1420. The multiplexer 1420 outputs the HS-DSCH power level 1418, HS-DSCH channelization code and other control information 1416, MCS level 1417, and HARQ control information 1419 to the SH.
The signals are multiplexed and provided to the serial / parallel converter 1421 so as to be suitable for the CCH slot format.
The serial / parallel converter 1421 is connected to the multiplexer 142.
One bit stream output from 0 is converted into two bit streams, that is, a bit stream I and a bit stream Q in parallel and provided to the spreader 1422. The spreader 1422 includes two multipliers. The two bitstreams output from the serial / parallel converter 1421 are input to the two multipliers, and the bitstream is converted into another channel. The spread bit stream I and the spread bit stream Q are generated by multiplying the code by the channel division code C _OVSF so as to have orthogonality with other signals using the code. Here, the spreader 1422 provides the spread bit stream Q to a multiplier 1423 and the spread bit stream I to an adder 1424. The multiplier 1423 multiplies the bitstream Q output from the spreader 1422 by j and adds the bitstream Q to the adder 1
424. The adder 1424 adds a signal output from the multiplier 1423 to the bitstream I to generate one complex bitstream and provides the complexbitstream to the multiplier 1425. The multiplier 1425
Is a scrambling code C for each chip of the complex number bit stream output from the adder 1424.
Multiply by _SCRAMBLE to scramble and provide the output to multiplier 1426. Here, the multiplier 142
5 operates as a scrambler. The multiplier 14
26 multiplies the signal output from the multiplier 1425 by a channel gain 1427 and provides the signal to a summer 1445.

The user data 1428 transmitted through the DPCH is input to the encoder 1429 and the encoder 1
429 encodes the user data 1428 according to a preset coding method and provides it to the rate matching unit 1430. The rate matching device 1
The interleaver 430 performs rate matching on the signal output from the encoder 1429 through symbol repetition or puncturing so that the number of output bits matches the number of bits actually transmitted through the physical channel. 1431. The interleaver 1431 interleaves the signal output from the rate matching unit 1430 according to a preset method and provides the interleaver 1431 to the modulator 1432. The modulator 1
432 modulates the signal output from the interleaver 1431 according to a preset modulation method and provides it to the multiplexer 1437. The multiplexer 1437 is
HS-DSCH indicator 1433, TFCI143
4 and pilot 1435 for estimating the forward channel condition and TPC1 for reverse transmit power control
By multiplexing 436, one bit stream is generated and provided to the serial / parallel converter 1438.

The serial / parallel converter 1438 is the
One bit stream output from the duplexer 1437
To two bitstreams, that is, bitstreams
I and bit stream Q are converted in parallel to spreader 1439
Output to. The spreader 1439 comprises two multipliers.
Output from the serial / parallel converter 1438
Two bitstreams to each of the two multipliers
Provide with other signals that use other channelization codes
Channel division code C so as to have orthogonality _OVSF
And the spread bitstream I and spread
Generate a scattered bitstream Q. Where the
The spreader 1439 receives the spread bit stream Q.
To a multiplier 1440, the spread bitstream
Ream I is output to adder 1441. The multiplier 1
440 is the bit stream output from the spreader 1439.
Multiply by the stream Q and j and provide to the adder 1441.
It The adder 1441 converts the bitstream I into
Adding the signals output from the multiplier 1440
1 complex number bit stream is generated by the multiplier 14
42. The multiplier 1442 is the adder 1
The complex bit stream output from
Scrambling code C_{SCRA MBLE}
And scramble it, and output the result to the multiplier 1443.
provide. Here, the multiplier 1442 scrambles
Act as Ra. The multiplier 1443 uses the multiplication
Channel gain 1444
And outputs it to the totalizer 1445.

The adder 1445 generates the generated D
PCH signal (that is, the signal output from the multiplier 1443), the generated SHCCH signal (that is, the signal output from the multiplier 1426), and the generated HS-DSCH signal (that is, the multiplication Vessel 1411
(The signals output from the above) are summed and provided to the filter 1446. The filter 1446 is the summing device 1445.
RF processor 1 by filtering the signal output from
Then, the RF processor 1447 converts the signal output from the filter 1446 into an RF band signal and transmits the RF band signal through the antenna 1448 over the air.

On the other hand, as described with reference to FIG. 12, in the case where the HS-DSCH indicator has a channel structure that is transmitted through a separate channel using a channelization code different from that of the DPCH, the present invention provides the information through the SHCCH. A transmitter for transmitting the HS-DSCH power level can be provided.

FIG. 15 is a block diagram showing a receiver structure of a UE corresponding to the transmitter of the Node B shown in FIG. Referring to FIG. 15, the RF band signal received through the antenna 1501 is input to the RF processor 1502. The RF processor 1502 converts the received RF band signal into a baseband signal and outputs the baseband signal to the filter 1503. The filter 1503 filters the signal output from the RF processor 1502 and provides it to the multipliers 1504, 1516, 1527. Here, the multipliers 1504, 1516, 1527
Operates as a descrambler and multiplies the input signal by the channelization code for the channel transmitted by the Node B transmitter. As a result, the multiplier 1504 outputs an HS-DSCH signal, which is a forward data channel, and the multiplier 1516 outputs the HS-DSCH signal.
Outputs a forward DPCH signal, and the multiplier 1527
Outputs the SHCCH signal.

The complex number signal output from the multiplier 1504 is input to the complex to I and Q streams section 1505. The complex to I and Q streams section 1505
Is a despreader 150 that separates the signal output from the multiplier 1504 into a real number signal I and an imaginary number signal Q.
6 to provide. The despreader 1506 is the complext.
The real number signal I and the imaginary number signal Q output from the I and Q streams section 1505 are multiplied by the channelization code C _OVSF used in the transmission device of the Node B and despread, and the output is a channel compensator.
r) Provide to 1510. Similarly, the complex number signal output from the multiplier 1516 is a complex to Iand Q stream.
s section 1517 is input to the complex to I and Q stre
The ams unit 1517 separates the signal output from the multiplier 1516 into a real number signal I and an imaginary number signal Q, and despreads the same.
18 to provide. The despreader 1518 is the comple
The real number signal I and the imaginary number signal Q output from the x toI and Q streams unit 1517 are multiplied by the channelization code C _OVSF used in the transmission device of the Node B and despread, and then the channel compensator 1519 and the demultiplexer. Bowl (d
emultiplxer) 1507. Also, the multiplier 1
The complex signal output from 527 is complex to I and
Input to Q streams section 1528, said complex to I an
The d Q streams section 1528 separates the signal output from the multiplier 1527 into a real number signal I and an imaginary number signal Q, and supplies the real number signal I and the imaginary number signal Q to the despreader 1529. The despreader 1529 multiplies the real number signal I and the imaginary number signal Q output from the complex to I and Q streams section 1528 by the channelization code C _OVSF used in the transmission device of the Node B to despread the signal. To channel compensator 1530. The output signals I and Q of the despreader 1518 are provided to the demultiplexer 1507. The demultiplexer 15
07 demultiplexes the signal output from the despreader 1518 and outputs a pilot 1508. The output pilot 1508 is a channel estimator.
stimator) 1509. The channel estimator 1509 detects a channel estimation value through distortion estimation based on a radio channel, and the channel compensators 1510 and 110.
519, 1530.

The channel compensators 1510, 1519,
1530 compensates the distortion of the signals output from the despreaders 1506, 1518, and 1529 using the channel estimation values, respectively. That is, the channel compensator 1510 outputs HS-DSCH data to two bit streams, and the channel compensator 1519 outputs DP-data.
The CH data is output to two bit streams, and the channel compensator 1530 outputs the SHCCH data to two bit streams. The channel compensator 151
The signals output from 0, 1519, and 1530 are parallel to serial converters 1 respectively.
The parallel / serial converters 1511, 1520, 1531 input to 511, 1520, 1531 serially convert the signals output from the channel compensators 1510, 1519, 1530 into one bit stream, respectively.

The signal output from the parallel / serial converter 1531 is finally output as HS-DSCH control information, and the signal output from the parallel / serial converter 1520 is output by the demultiplexer 1521 to the TPC 1522. ,
TFCI 1523 and HS-DSCH indicator 1524 and HS- separated by switch 1525.
Demultiplexed to DSCH power level 1526. The demultiplexer 1521 further outputs a forward data signal, which is demodulated by a demodulator 1533, a deinterleaver 1534, and a decoder 1535.
Channel decoded by the forward user data 15
It is output as 36. In addition, the parallel / serial converter 1
The signal output from 511 is channel-decoded by a demodulator 1512, a deinterleaver 1513, and a decoder 1514, and finally a forward data packet 1515.
Is output as. Here, the decoder 1514 may use the received HS-DSCH power level 1526 when the forward data packet 1515 is modulated by a QAM scheme.
15 is modulated by the QAM method.

FIG. 16 shows H according to another embodiment of the present invention.
It is a block diagram which shows the receiver of UE in the communication system which uses a SDPA system. Particularly, the structure corresponding to the transmission device of the Node B described in FIG. 14 is shown.

Referring to FIG. 16, the RF band signal received through the antenna 1601 is processed by the RF processor 1602.
Entered in. The RF processor 1602 converts the received RF band signal into a base band signal and filters the signal.
603. The filter 1603 is the RF
The signal output from the processor 1602 is filtered and output commonly to the multipliers 1604, 1616, 1625. Here, the multipliers 1604, 1616, 1625
Operates as a descrambler (descrambler), multiplied with the Node signal code _{C D ESCRAMBLE} is the input for the transmission channel from the transmission apparatus B. As a result, the multiplier 1604 outputs a forward data channel HS-DSCH signal, the multiplier 1616 outputs a forward DPCH signal, and the multiplier 1625 outputs a SHCCH signal.

The complex number signal output from the multiplier 1604 is input to the complex to I and Q streams section 1605. Said complex to I and Q streams section 1605
Separates the signal output from the multiplier 1604 into a real number signal I and an imaginary number signal Q and outputs them to the despreader 1606. The despreader 1606 is connected to the complex to I and Q.
The real number signal I and the imaginary number signal Q output from the streams section 1605 are multiplied by the channelization code C _OVSF used in the transmission device of the Node B and despread, and the output is provided to the channel compensator 1610. Similarly, the complex signal output from the multiplier 1616 is complex to I
It is input to the and Q streams section 1617. The complex
The to I and Q streams section 1617 is the multiplier 1616.
The signal output from is separated into a real number signal I and an imaginary number signal Q and provided to the despreader 1618. The despreader 1618
Outputs the real number signal I and the imaginary number signal Q output from the complex to I and Q streams section 1617 to the Node B.
It is multiplied by the channelization code C _OVSF used in the transmission apparatus of 1 to despread and then output to the channel compensator 1619 and the demultiplexer 1607. In addition, the multiplier 1625
The complex signal output from is complex to I and Q str
It is input to the eams unit 1626. Said complex to Iand Q
The streams section 1626 separates the signal output from the multiplier 1625 into a real number signal I and an imaginary number signal Q, and outputs them to the despreader 1627. The despreader 1627 is connected to the co
The real number signal I and the imaginary number signal Q output from the mplex to I and Q streams section 1626 are multiplied by the channelization code C _{O VSF} used in the transmission device of the Node B to despread and then output to the channel compensator 1628. To do. The output signals I and Q of the despreader 1618 are provided to the demultiplexer 1607. The demultiplexer 1607 demultiplexes the signal output from the despreader 1618 and outputs a pilot. The output pilot is
It is input to the channel estimator 1609. The channel estimator 1609 detects a channel estimation value through distortion estimation based on a wireless channel and detects the channel compensator 161.
0, 1619, 1628.

The channel compensators 1610, 1619,
1628 compensates the distortion of the signals output from the despreaders 1606, 1618, 1627, respectively, using the channel estimation value. That is, the channel compensator 1610 outputs the HS-DSCH data into two bitstreams, and the channel compensator 1619 outputs the DPC data.
The H data is output to two bit streams, and the channel compensator 1628 outputs the SHCCH data to two bit streams. The channel compensators 1610, 1
The signals output from 619 and 1628 are input to parallel / serial converters 1611, 1620, and 1629, respectively, and the parallel / serial converters 1611, 1620, and 162 are input.
9 are the channel compensators 1610 and 161 respectively.
The signals output from 9, 1628 are serially converted into one bit stream.

The signal output from the parallel / serial converter 1629 is input to the demultiplexer 1630. The demultiplexer 1630 converts the signal output from the parallel / serial converter 1629 into an HS-DSCH channelization code and other control information 1631, an MCS level 1632, an HS.
-DSCH power level 1633, and HARQ information 16
Demultiplex to 34. The signal output from the parallel / serial converter 1620 is demultiplexed by the demultiplexer 1621 into a TPC 1622, a TFCI 1623, and an HS-DSCH indicator 1624. The demultiplexer 1
621 further outputs a forward data signal, which is demodulated by the demodulator 1625 and the deinterleaver 1.
636, and channel decoding by the decoder 1637, and finally output as forward user data 1638. The signal output from the parallel / serial converter 1611 is used as a demodulator 1612 and a deinterleaver 161.
3 and channel decoded by decoder 1614,
It is finally output as the forward data packet 1615. Here, the decoder 1614 may receive the received HS-DSCH power level 163 when the forward data packet 1615 is modulated by QAM.
3 is used to perform modulation by the QAM method.

FIG. 17 shows an HSD according to an embodiment of the present invention.
6 is a flowchart showing an operation process of a Node B in the PA system. In particular, by Node B, HS
-Describes the process of determining and transmitting the DSCH power level.

Referring to FIG. 17, in step 1702, N
node B is H indicating the presence or absence of HSDPA data packet
Determine the S-DSCH indicator and proceed to step 1703. Here, the HS-DSCH indicator is
As described with reference to FIG. 9, the information is necessary only when the UE receives the HSDPA service, and the Node B is
H only when the HS-DSCH indicator is present
Determine and transmit S-DSCH power level. In particular,
"Determining the HS-DSCH indicator" means deciding whether to turn the HS-DSCH indicator on or off. HS transmitted through the HS-DSCH
If DPA data is present, the HS-DSCH is turned on. HS transmitted through the HS-DSCH
If there is no DPA data, the HS-DSCH is turned off. In step 1703, the Node B checks whether the HS-DSCH indicator is on. If the result of the check is that the HS-DSCH indicator is not on, that is, the HS-DSCH is off, the Node B proceeds to step 1704, waits until the next TTI, and then proceeds to step 1704. 17
Return to 02.

At step 1703, if the HS-DSCH indicator is on, the Node B proceeds to step 1705. In step 1705, the Node
B is an HSDP transmitted through the HS-DSCH.
Determine the MCS level that determines the modulation scheme and channel coding scheme for A data. In step 1706,
The Node B refers to the determined MCS level so that the HS-DSCH modulation scheme is QAM.
Check whether it is a system. As a result of the inspection, the H
If the S-DSCH modulation scheme is not the QAM modulation scheme, the Node B returns to step 1704. The HS-
If the DSCH modulation scheme is the QAM modulation scheme, the Node B proceeds to step 1707. Step 170
7, the Node B QA the HS-DSCH.
Since the modulation is performed by the M modulation method, the HS-that can be assigned to one channelization code by the Node B
After determining the maximum and minimum DSCH power levels, proceed to step 1708. In step 1708, the N
The Node B determines the HS-DSCH power level based on the maximum and minimum levels of the HS-DSCH power, and then proceeds to step 1709. In step 1709,
The Node B terminates the process after transmitting the determined HS-DSCH power level on the DPCH or SHCCH.

FIG. 18 shows H according to another embodiment of the present invention.
7 is a flowchart illustrating an operation process of a UE in the SDPA system. In particular, FIG.
Receiving a DSCH power level, said received HS-D
FIG. 6 is a diagram illustrating an operation of decoding data based on a SCH power level.

Referring to FIG. 18, in step 1802, U
After detecting the HS-DSCH indicator from the received DPCH signal, E proceeds to step 1803. In step 1803, the UE detects the detected HS-DSC.
Check if the H indicator is on. If the result of the check is that the HS-DSCH indicator is not on, that is, the HS-DSCH is off, the UE proceeds to step 1804. Step 180
At 4, the UE waits until the next TTI, and then
Return to step 1802.

In step 1803, if the HS-DSCH indicator is on, the UE determines in step 1805.
Proceed to. In step 1805, the UE determines whether the HS-
After detecting the MCS level transmitted on the SHCCH in the next slot in the TTI with the DSCH indicator turned on, proceed to step 1806. Step 18
At 06, the UE detects that the detected MCS level is Q.
Check whether it shows AM modulation. If the result of the check is that the MCS level does not indicate the QAM modulation, the UE returns to step 1804. However,
If the MCS level indicates the QAM modulation as a result of the check, the UE proceeds to step 1807. In step 1807, the UE detects the HS-DSCH power level from the SHCCH if the MCS level has a QAM modulation scheme and thus has the channel structure described in FIG. In step 1808, the UE determines the HS-DSCH power level according to the detected HS-DSCH power level.
After demodulating the DSCH, the process ends.

So far, the process of determining the HS-DSCH power level for reliable demodulation of the HS-DSCH and transmitting and receiving the determined HS-DSCH has been described.
Next, the reverse high speed dedicated physical control channel (High Speed Dedicated
dedicated Physical Control Channel: Below, HS-DP
A process of determining a reverse transmission power offset (Uplink Power Offset) for controlling a transmission power level of the CCH) and transmitting and receiving the determined reverse transmission power offset will be described.

FIG. 19 illustrates a scheme for determining reverse power offset according to an embodiment of the present invention. As described with reference to FIG. 7, in the communication system using the HSDPA method, when the UE is located in the soft handover area,
The reverse transmission power of HS-DPCCH may be reduced. However, it is difficult for the Node B to continuously monitor whether the UE is located in the soft handover area. Therefore, in the embodiment of the present invention, the target signal to interference ratio (SIR) S that is preset in the Node B is set.
_IR targe _t and reverse dedicated physical control channel from UE (Dedicated Physical Control Channel: less, DP
Measurement SIR (Estimation SIR) SI measured based on pilot bits received through CCH)
If the difference from R _est is larger than the preset threshold value # 1, then the state of the corresponding channel is determined to be bad. Then, the present invention compares the SIR difference with a threshold value to determine a transmission power offset according to a reverse channel condition. That is, the reverse transmission power is compensated not only when the UE is simply located in the soft handover area but also when the reverse channel environment is bad.
19, the Node B is _{SIR targ et} and S
An example of determining the reverse transmission power offset using the difference between IR _est is shown. The critical value is the Node
It can be arbitrarily determined by B, but FIG.
, It is assumed that the critical value is set to a multiple of 2 dB. That is, SIR for a critical value of 2 dB
_If the difference between _target and SIR _est is greater than or equal to 2 dB and less than or equal to 4 dB, the reverse transmission power offset is 2
dB, the Node B transmits the determined reverse transmission power offset to the UE. Upon receiving the reverse transmission power offset from the Node B, the UE increases the reverse transmission power by the received reverse transmission offset of 2 dB.

On the other hand, in the present invention, SIR
The difference between the _{SIR es t} of _target and the uplink DPCCH is defined as the uplink power offset, reverse HS-D
The transmission power of only the PCCH is increased by the amount of the reverse power offset, and the other channels DPCCH and DP
The existing transmission power scheme is applied to DCH. The HS-D
The transmission power of the PCCH is increased by the reverse power offset only when the channel condition is bad based on the power determined by the ratio with the transmission power of the existing DPCCH each time.

FIG. 20 is a table showing bit values for transmitting a reverse power offset according to an embodiment of the present invention. FIG. 20 shows bits that transmit the reverse power offset when the Node B transmits the reverse power offset determined as described in FIG. 19 to the UE. If the reverse channel environment is good and it is not necessary to transmit the reverse power offset in the forward direction, that is, if the reverse power offset is 0 dB, the DTX process is performed. This is to transmit the reverse power offset in the forward direction only when the reverse channel environment is bad, and perform DTX processing when the reverse channel environment is good, thereby channeling the reverse power offset. It means adaptive transmission depending on the situation. Here, if the reverse power offset is 0 dB, the reliability of the reverse HS-DPCCH can be guaranteed because the channel environment is good, and thus the forward TPC can be maintained while maintaining a constant power ratio with the existing DPCCH. It means that the reverse transmission power can be controlled only by the command. As described above, the Node B transmits the reverse power offset and performs the reverse power control according to the reverse power offset only when the channel condition is poor. In order to transmit the reverse power offset to the UE, if the number of the reverse power offset is 2 ^K with respect to the reverse power offset other than 0 dB as shown in FIG. The number of forward transmission bits to transmit can be set to K. In FIG. 20, since the reverse power offsets other than 0 dB are 2 dB, 4 dB, 6 dB, and 8 dB,
It can be represented by 2 bits. For example, the reverse power offset can be represented by forward transmission bits of 00, 01, 10, 11.

FIG. 21 shows H according to another embodiment of the present invention.
1 is a schematic diagram showing a forward channel structure of a communication system using an SDPA scheme. Referring to FIG. 21, as described with reference to FIG. 1, a downlink DPCH and an HS-D are included in a channel capable of transmitting a reverse power offset.
There is an SHCCH for controlling the SCH. However, the SHCCH is the MCS level for the HSDPA service, the HS-DSCH channelization code,
Since the control information such as the HARQ processor number and the HARQ packet number is transmitted, there is no room to transmit other control information.

However, as shown in FIG. 1, when one TTI has N (= N ₁ + N ₂ ) slots, H
The S-DSCH indicator is transmitted in N ₁ slots and transmitted in the remaining N ₂ slots.
The part that transmits the H indicator is DTX processed. Therefore, the reverse power offset may be separately transmitted through the HS-DSCH indicator portion of the slot that does not transmit the HS-DSCH indicator on the DPCH. Since the position of the slot transmitting the HS-DSCH indicator is variable, the position of the slot transmitting the reverse power offset is also variable. Also, the reverse power offset is TTI.
It can also be transmitted from the Node B to the UE on a periodic basis, or can be transmitted on a fixed slot period basis or on a frame-by-frame basis if there are many bits indicating the reverse power offset to be transmitted. In FIG. 21, the HS-DSCH indicator is transmitted only through the first slot (slot # 0) in the TTI, and the reverse power offset is the remaining (N
-1) The second slot (slot # 1) of the slots and N
It is transmitted through the HS-DSCH indicator part of the th slot (slot # N-1). The other forward channels, that is, the SHCCH and the HS-DSCH have the same structure as described in FIG. Meanwhile, the reverse power offset is the HS-DPCC for HSDPA.
Since it is a value for controlling the reverse transmission power of H, the UE
Is a value required only when receiving the HSDPA service. Therefore, the reverse power offset is equal to the HS
Only when DPA service data exists, that is, H
By transmitting only when the S-DSCH indicator is present, the Node B should always monitor the channel condition to determine the reverse transmission power offset. Alternatively, the UE may be prevented from reading the reverse power offset. In addition, as described with reference to FIG. 20, the Node B performs DTX processing when the reverse power offset is 0 dB,
The reverse power offset is transmitted only when required by the channel conditions. The bit indicating the reverse power offset determined by FIG. 20 is K, and
If the number of bits that can be transmitted through the (N-1) slot is n, as shown in 1, a reverse power offset can be transmitted using an error correction code such as a (n, K) block code. .

FIG. 22 shows H according to another embodiment of the present invention.
Forward DPCH of communication system using SDPA method
The structure is shown. Referring to FIG. 22, the DPCH includes a forward DPCH structure defined in a CDMA communication system that does not support an existing HSDPA service, for example, Release-99, and has the following fields. The Data1 and Data2 fields carry data for supporting the operation of an upper layer or data for supporting a voice-only service. The TPC field is a forward TPC for controlling reverse transmit power.
The command is transmitted and the TFCI field is set to the Data1.
And TFC information of the Data2 field is transmitted. P
The ilot field is a field that carries a pilot symbol stream predefined by the system and is used by the UE to estimate the forward channel condition. HS for the HSDPA service
-DSCH indicator and reverse power offset are
As shown in FIG. 9, it is transmitted to the UE through a field newly defined in an existing Release-99 forward DPCH. FIG. 22 illustrates a case where the HS-DSCH indicator and the reverse power offset are transmitted through a newly defined field in an existing forward DPCH. Meanwhile, referring to FIG. 23, the HS-DSCH indicator and the reverse power offset are not transmitted through a specific field in the existing forward DPCH, but a new forward DPCH.
The case of being transmitted through will be described.

FIG. 23 illustrates a forward direction DP of a communication system using the HSDPA method according to another embodiment of the present invention.
A CH structure is shown. Referring to FIG. 23, the HS-DS
The CH indicator or reverse power offset is not transmitted through a specific field in the existing forward DPCH, but through a new forward DPCH assigned a separate channelization code. Two forward DPCHs, namely P-DPCH and S-DPC
Assign H. S-DP for transmitting the HS-DSCH indicator or the reverse power offset
Since CH has a different amount of data to be transmitted from the P-DPCH, N is assigned as SF to the P-DPCH,
M is assigned as SF to the S-DPCH. If the amount of data of the transmitted HS-DSCH indicator and reverse power offset is small, the S-DPCH
The SF value of M is a relatively large value, for example, M = 5
Setting to 12 increases the efficiency of use of the forward channelization code.

FIG. 24 shows an HSD according to an embodiment of the present invention.
It is a block diagram which shows the internal structure of the Node B receiver in a PA system. Referring to FIG. 24, the signal received from the UE through the antenna 2401 is input to the RF processor 2402. The RF processor 2402
Converts the signal received from the antenna 2401 into a baseband signal and provides it to the demodulator 2403. The demodulator 2403 demodulates the signal output from the RF processor 2402 according to a preset demodulation method and provides the demodulated signal to the multiplier 2404. The multiplier 2404 descrambles the signal output from the demodulator 2403 by multiplying it by a scrambling code C _SCRAMBLE . Here, the scrambling code is the N
A code specified between the Node B and the UE, which enables the Node B to identify a specific UE among a plurality of UEs. The signals output from the multiplier 2404 are despreaders 2405, 2406, 240.
7 is commonly input. The despreader 2405 performs despreading on the reverse DPDCH signal, the despreader 2406 performs despreading on the reverse DPCCH signal, and the despreader 2407 performs despreading on the HS-DPCCH. Carry out. Here, "performing despreading" means multiplying an input signal by a preset channelization code. Of course, the channelization code is reciprocal between the Node B and the UE.

DP output from the despreader 2406
The CCH signal is input to the multiplier 2411, multiplied by -j, and restored to a real number signal. Here, the reason for multiplying the input signal by the -j is that the UE uses the DPCCH.
This is because the signal is multiplied by j and transmitted as an imaginary signal.
The signal output from the multiplier 2411 is input to the demultiplexer 2419 and the multiplier 2412, respectively. The demultiplexer 2419 extracts only the pilot 2414 from the DPCCH signal to obtain a channel estimator 2418.
And channel condition determiner 2425. The channel condition determiner 2425 calculates the reverse power offset by U.
In order to determine whether to transmit to E, a difference between SIR _est and SIR _target is calculated, and the difference is compared with a preset critical value, and the comparison result is a reverse power offset determination. 2426. Then,
The reverse power offset determiner 2426 determines the reverse power offset 242 according to the comparison result output from the channel condition determiner 2425 as described with reference to FIG.
Determine 7. In the above process, as described with reference to FIG. 21, if the Node B does not have an HSDPA data packet to transmit, that is, if the HS-DSCH indicator is off, the reverse power offset determiner 2426 may perform the reverse operation. Do not transmit directional power offset.

On the other hand, the channel estimator 2418 uses the pilot 2414 to transmit the UE and the Node.
Estimate the channel environment with B. The channel estimator 2418 estimates a channel based on the pilot 2414 and then multiplies the channel estimation value for the estimated channel environment by multipliers 2412, 208, and 2421.
To provide. The multiplier 2412 is the multiplier 241.
1 is multiplied by the signal output from the channel estimator 2418, and then provided to the demultiplexer 2413. The demultiplexer 2413 includes the multiplier 241.
2 except the pilot 2414
PC2415, TFCI2416, feedback information
(Feed Back Information: Hereinafter referred to as FBI) 24
Demultiplex to 17. The TPC 2415 is used for controlling the forward transmission power, and the TFCI 2416 is used.
Is used for the analysis of the reverse DPDCH, and the F
BI 2417 is used for gain adjustment of the closed loop transmit antenna. Further, the multiplier 2408 multiplies the signal output from the despreader 2405 and the signal output from the channel estimator 2418 to obtain a decoder 240.
9 to provide. The decoder 2409 includes the multiplier 24
08, the coding method used by the UE, for example, convolutional coding or turbo coding.
By decoding with a decoding method corresponding to a coding method such as (turbo coding), user data (user da
ta) or the upper layer signaling signal 2428, and provides the generated user data or the upper layer signaling signal 2428 to the upper layer. Further, the multiplier 2421 multiplies the signal output from the despreader 2407 and the signal output from the channel estimator 2418 and provides the result to the demultiplexer 2422. The demultiplexer 2422 outputs the signal output from the multiplier 2421 to ACK / NACK 2423 and other control information (oth).
er information) 2424.

The receiver of the Node B in the HSDPA system has been described with reference to FIG. Next, with reference to FIG. 25, the transmission apparatus of the Node B will be described.

FIG. 25 shows an HSD according to an embodiment of the present invention.
It is a block diagram which shows the internal structure of the transmission apparatus of Node B in a PA system. In FIG. 25, Node
The transmission device of B is a communication system that does not use the HSDPA method, for example, Data1, TPC, TFCI, Data2, defined in Release-99.
Pilot, and in the case where the Node B supports the HSDPA service, the HS-DSCH indicator or the reverse power offset is added to one forward DPC.
Transmit through H.

Referring to FIG. 25, user data 2501 transmitted through the DPCH is input to the encoder 2502. The encoder 2502 channel-codes the user data 2501 and provides the user data 2501 to a rate matching unit 2503. The rate matching device 2
503 performs rate matching on the signal output from the encoder 2502 so that the number of output bits matches the number of bits actually transmitted through the physical channel, and outputs the rate-matched signal. It is provided to the multiplexer 2510. The HS-DSCH indicator 2505 occurs when there is data to be transmitted through the HSDPA service to the UE, and the reverse power offset 2506 should be transmitted according to the channel conditions in the interval where the HS-DSCH indicator is not transmitted. Occurs at times. The generated HS-DS
CH indicator 2505 and reverse power offset 2
506 is provided to switch 2504. The switch 2504 includes the HS-DSCH indicator 250.
5 and the reverse transmission power offset 2506 are switched and provided to the multiplexer 2510. further,
The TFCI 2507, pilot 2508, and TPC 2509 generated in the system are also input to the multiplexer 2510.

The multiplexer 2510 outputs the signal output from the rate matching unit 2503, the switch 2
504 output signal, TFCI 2507, Pilot
1 by multiplexing 2508 and TPC2509
One bitstream is generated, and the generated bitstream is provided to the serial / parallel converter 2511. The serial / parallel converter 2511 includes the multiplexer 251.
The signal output from 0 is converted into two bit streams, that is, a bit stream I and a bit stream Q in parallel and provided to the spreader 2512. The diffuser 251
2 is composed of two multipliers, and the two bit streams output from the serial / parallel converter 2511 are provided to the two multipliers, respectively, and orthogonal to signals using other channelization codes. The spread bit stream I and the spread bit stream Q are generated by being multiplied with the channelization code C _OVSF to ensure the property. Here, the diffuser 2512 is
The spread bit stream Q is provided to the multiplier 2513, and the spread bit stream I is added to the adder 2
514. The multiplier 2513 multiplies the bit stream Q output from the spreader 2512 by j and provides the result to the adder 2514. The adder 2514
Is the bitstream I signal and the multiplier 2513
One complex number bit stream is generated by adding the signals output from, and provided to the multiplier 2515. The multiplier 2515 multiplies the complex bit stream output from the adder 2514 by a scrambling code C _{SCRAMB LE} on a chip-by-chip basis to scramble, and provides the output to the multiplier 2516. here,
The multiplier 2515 operates as a scrambler. The multiplier 2516 multiplies the signal output from the multiplier 2515 by a channel gain to provide a summer 2524. Where the channel gain is
A parameter for determining the transmission power of the DPCH,
Generally, when the spreading factor is small, the channel gain is large, and it varies depending on the type of user data transmitted. So far, the process of generating the DPCH has been described. Next, a process of generating SHCCH will be described.

The HS-DSCH control information 2517 is input to the serial / parallel converter 2518. The serial / parallel converter 2518 uses the HS-DSCH control information 251.
7 is converted into two bit streams, that is, a bit stream I and a bit stream Q, and provided to the spreader 2519. The spreader 2519 is composed of two multipliers, and the two bit streams are input to the two multipliers and multiplied by the channelization code C _OVSF to spread the bit stream I and the spread bit stream I and spread, respectively. And generates a bitstream Q that has been processed. Here, the spreader 2519 is used by the spread bit stream Q.
To the multiplier 2520 and the spread bit stream I to the adder 2521. The multiplier 25
20 multiplies the bit stream Q output from the spreader 2519 by j and provides the result to the adder 2521.
The adder 2521 generates one complex bit stream by adding the bit stream I and the signal output from the multiplier 2520, and the multiplier 2521
22. The multiplier 2522 uses the adder 2
The complex number bit stream output from 521 is scrambling code C _{SCRAMBLE in} chip units.
It is multiplied by and scrambled, and its output is provided to the multiplier 2523. Here, the multiplier 2522 operates as a scrambler. The multiplier 2523 multiplies the signal output from the multiplier 2522 by a channel gain and provides the signal to the summer 2524. The totalizer 2524
Is the generated DPCH signal (that is, the signal output from the multiplier 2516) and the generated SHC
The CH signals (that is, the signals output from the multiplier 2523) are summed and provided to the modulator 2525. The modulator 2525 modulates the signal output from the summer 2524 and provides it to the RF processor 2526. The RF processor 2526 converts the signal output from the modulator 2525 into an RF band signal and transmits the RF band signal on the air through an antenna 2527.

FIG. 26 shows an HSD according to an embodiment of the present invention.
It is a block diagram which shows the internal structure of the transmission / reception apparatus of UE in a PA system. Referring to FIG. 26, user data and higher layer signaling information 2601 are input to an encoder 2602. The encoder 2602 encodes the user data and higher layer signaling information 2601 using a preset coding scheme, for example, convolutional coding or turbo coding scheme, and provides the encoded data to the rate matching unit 2603.
The rate matching unit 2603 is the encoder 260.
The signal output from the signal 2 is rate-matched through a symbol repetition or puncturing process and provided to the spreader 2604. The spreader 2604 uses the rate matching unit 2
The signal output from 603 is multiplied by a channelization code, spread, and provided to a multiplier 2605. The multiplier 2605
Is multiplied by the signal output from the spreader 2604 and the channel gain and provided to the summer 2606. Furthermore, TP
C2607, Pilot2608, TFCI2609,
And the FBI 2610 are input to the multiplexer 2611. The multiplexer 2611 includes the TPCs 2607, P
ilot2608, TFCI2609, and FBI26
DPCCH is generated by multiplexing 10 and spreader 2
612 will be provided. The spreader 2612 applies the DPCCH signal output from the multiplexer 2611 to the DPCC.
H is multiplied by a preset channelization code and spread, and provided to the multiplier 2613. The multiplier 2613
Multiplies the signal output from the spreader 2612 by the channel gain and provides it to the multiplier 2614. The multiplier 2
614 represents the signal output from the multiplier 2613 and-
It is multiplied by j and provided to the summer 2606. Where −
The reason for multiplying j is to distinguish the DPCCH signal and the DPDCH signal into the imaginary number side and the real number side, and
In (Constellation), the frequency of zero crossing is reduced, and the peak-to-average ratio (P
This is because it is possible to reduce the "eak to Average ratio:" (hereinafter referred to as PAR). Generally, when a zero crossing occurs in a constellation on a radio frequency, PAR increases, and the increased PAR adversely affects the transmitter of the UE.

The ACK / NACK 2615 and other control information 2616 are input to the multiplexer 2617.
The multiplexer 2617 uses the ACK / NACK 261.
5 and other control information 2616 are multiplexed and spreader 261
Provide to 8. The spreader 2618 is used by the multiplexer 2
The signal output from 617 is multiplied by the channelization code set in advance on HS-DPCCH and spread, and the output is provided to multiplier 2623. Meanwhile, the UE receives the signal received through the receiving antenna 2619 from the receiving stage 2
620. The receiving stage 2620 demodulates the received signal to detect a reverse power offset 2621, and detects the detected reverse power offset by the controller 2.
622. Here, the receiving unit 2620
Performs demodulation through a process opposite to the process of transmitting the reverse power offset in the Node B transmitter shown in FIGS. 21 and 25. The controller 2622
Is a reverse transmission power determined by increasing the reverse transmission power of the current HS-DPCCH transmitted with a constant power ratio with the DPCCH by the detected reverse power offset. Adjusting the channel gain and transmitting the adjusted channel gain to the multiplier 2623 for transmitting the DPCCH signal. The multiplier 2623 multiplies the signal output from the spreader 2618 by the adjusted channel gain and adds the multiplier 2
606 is provided. In short, the UE is the DPDCH
The existing power control method is applied to the channel gains for the DPCCH and DPCCH, but the channel gain for the HS-DPCCH is adjusted using the reverse power offset. The summer 2606 sums the DPDCH signal output from the multiplier 2605, the DPCCH signal output from the multiplier 2614, and the HS-DPCCH signal output from the multiplier 2623 to add a multiplier 262.
4 to provide. Here, as described above, since the DPCCH signal is an imaginary number generated by being multiplied by j, the characteristic of each DPCCH does not disappear even if it is summed with the HS-DPCCH. In addition, the DPDCH and HS
-The DPCCHs are spread with different channelization codes, so they do not affect each other when spread at the receiver. Unlike the DPCCH, the HS-DPCCH is added to the DPDCH and transmitted through the I channel,
The DPCCH is transmitted through the Q channel because the HS-DPCCH is not transmitted when there is no user data or higher layer signaling on the DPDCH transmitted through the real channel (or I channel). If the DPDCH is not transmitted and two DPCCHs are transmitted through the imaginary channel (or the Q channel), the frequency of zero crossings increases and the PAR of the UE transmitter increases.
Therefore, the HS-DPCCH is the PA of the UE transmitter.
In order to minimize R, it is transmitted in real numbers.

The multiplier 2624 is connected to the adder 260.
The signal output from the signal _{No. 6} is multiplied by a scrambling code C _SCRAMBLE set in advance, scrambled, and provided to the modulator 2625. Here, the scrambling code is a code used to distinguish each UE in UMTS, and is, for example, a complex code generated from a gold code.
e). The modulator 2625 is the multiplier 2624.
The output signal from the modulator is provided to the RF processor 2626. The RF processor 2626 converts the signal output from the modulator 2625 into an RF band signal, and transmits the RF band signal through the antenna 2627 over the air.

FIG. 27 shows H according to another embodiment of the present invention.
It is a figure which shows the operation process of NodeB in a SDPA system. Referring to FIG. 27, in step 2702, the N
The Node B checks whether there is HSDPA packet data to be transmitted to the corresponding UE, and determines an HS-DSCH indicator indicating the presence or absence of HSDPA packet data to be transmitted to the UE according to the result of the check. Then, proceed to step 2703. Here, "HS-D
"Determining the SCH indicator" means the above H
It means determining whether to transmit the S-DSCH indicator, and as described in FIG.
The reverse power offset required only when receiving SDPA service is generated only when the HS-DSCH indicator is present. In Step 2703, the No.
de B checks whether the determined HS-DSCH indicator is on. As a result of the inspection, if the HS-DSCH indicator is not on, that is, if the HS-DSCH is off, the Nod.
e B proceeds to step 2704. In Step 2704, the Node B waits until the next TTI because the HS-DSCH indicator is off, and then in Step 2702.
Return to.

If it is determined in step 2703 that the HS-DSCH indicator is on, the Node
B proceeds to step 2705. In step 2705, the Node B determines SIR _est and S for the UE.
Check if the difference between the IR _target and the IR _target exceeds the first critical value among the preset critical values. If the difference between the SIR _est and the SIR _target exceeds the first critical value as a result of the inspection, the Node is detected.
B proceeds to step 2706. However, if the difference between the SIR _est and the SIR _target is less than or equal to the first critical value as a result of the inspection, the Node is detected.
B proceeds to step 2704. In step 2706, the Node B determines a reverse power offset that causes heavy rain on the UE, and then proceeds to step 2707. here,
The reverse power offset is determined using the difference between the SIR _est and the SIR _target and a preset threshold value as described with reference to FIG. 24, and a detailed description thereof will be omitted. In step 2707, the Node B
DPCH the determined reverse power offset value
Alternatively, after determining through the S-DPCH, the process ends. Here, the reverse power offset is transmitted in another slot in which the HS-DSCH indicator is not transmitted when one DPCH is used, and two reverse power offsets are transmitted.
When PCH is used, that is, P-DPCH and S-
When the DPCH is used, it is transmitted through the S-DPCH.

So far, the process for transmitting the reverse power offset by the Node B according to the embodiment of the present invention has been described with reference to FIG. Next, an operation process of the UE that receives the reverse power offset and actually adjusts the reverse power of the HS-DPCCH will be described with reference to FIG. 28.

FIG. 28 shows H according to another embodiment of the present invention.
FIG. 6 is a diagram illustrating an operation process of a UE in the SDPA system. Referring to FIG. 28, in step 2802, the UE
H from the received DPCH signal or S-DPCH signal
After detecting the S-DSCH indicator, step 2803
Proceed to. Here, when the Node B transmits one DPCH, the UE detects an HS-DSCH indicator from the DPCH signal. However, the UE has a DPCH with two Node Bs,
That is, when transmitting the P-DPCH and S-DPCH, the HS-DSCH indicator is detected from the S-DPCH signal. In step 2803, the UE checks whether the detected HS-DSCH indicator is on. If the result of the check is that the HS-DSCH indicator is not on, the UE proceeds to step 2804. In step 2804, the UE waits for the next TTI and returns to step 2802.

In step 2803, as a result of the inspection, the H
If the S-DSCH indicator is on, the UE
Proceeds to step 2805. In step 2805, the U
E determines that there is a reverse transmission power offset in a slot other than the HS-DSCH indicator slot, and again reads the DPCH or S-DPCH to detect the reverse power offset. Of course, since the channel environment of the system is good, H
If it is not necessary to control the reverse transmission power of the S-DPCCH, the reverse power offset is not transmitted. In step 2805, if the UE is located in a soft handover area or the channel condition is bad, the Node B may control a reverse power offset to control a reverse transmit power for the HS-DPCCH. Suppose you want to transmit. In step 2806, the UE adjusts the reverse transmission power of the HS-DPCCH using the detected reverse transmission power offset, and then ends the process.

Here, as described with reference to FIG.
B determines the HS-DSCH power level and the reverse power offset as described in FIG.
A method and apparatus for constructing a forward DPCCH for forward transmission of S-DSCH power level information and the reverse power offset information will be described. As described with reference to FIGS. 5A to 5C, the QAM modulation method is a method used when the channel environment is good for comparison, and the QPSK modulation method is a method used when the channel environment is bad. . Here, the HS-DSCH power level information and the reverse power offset information will be described. The HS-DSCH power level is information required by the UE for QAM demodulation when the HS-DSCH is QAM-modulated because the forward channel environment is good. On the other hand, the reverse power offset is information for compensating the reverse transmission power of the HS-DPCCH used when the reverse channel is defective. That the reverse channel environment is bad means that the environment of the forward channel is also bad to some extent. Therefore, the two types of control information are information required by the UE in different channel environments. That is, when the forward channel environment is good, the HS-DSCH is QAM
Since the UE is HS-DS modulated,
Requires CH power level. However, if the forward channel environment is bad, the Node B may
-Since the DSCH is modulated by the QPSK or 8PSK scheme, the UE does not need the HS-DSCH power level, but instead needs the reverse transmit power offset to compensate the transmit power of the HS-DPCCH. . In conclusion, the Node B selects one of the HS-DSCH power level and the reverse transmission power offset according to the channel environment, and transmits the selected control information to the UE. Here, the criterion for classifying the channel environment is the MCS level. That is, if the channel environment is good, the Node B uses the QAM modulation scheme and transmits the HS-DSCH power level to the UE, and if the channel environment is bad, the Nod is used.
The eB transmits the reverse transmission power to the UE without using the QAM modulation method.

In an embodiment of the present invention, the HS-D
A method of transmitting the SCH power level and the reverse power offset through the forward DPCH will be described with reference to FIG. FIG. 29 is an HSD according to another embodiment of the present invention.
HS-DSC in a communication system using the PA method
7 shows a channel structure for transmitting H power level and reverse power offset. The channel structure of FIG. 9 in which the Node B transmits only the HS-DSCH power level and the Nod
Unlike the channel structure of FIG. 21 in which e B carries only the reverse power offset, the channel structure of FIG.
The HS-DSCH power level and the reverse power offset are alternately transmitted according to channel conditions in a period in which the HS-DSCH indicator is not transmitted. Also,
Even if the HS-DSCH indicator is transmitted through another channel using a channelization code different from that of the DPCH, as shown in FIGS. -DSCH power level and the reverse power offset can be transmitted.

No for determining the reverse power offset
Since the receiving device of de B has the same structure as the receiving device of FIG. 24, detailed description thereof will be omitted, and hereinafter, FIG.
The structure of the Node B transmitter will be described with reference to FIG.

FIG. 31 is a diagram showing the structure of a Node B transmitter corresponding to the forward channel structure of FIG. Referring to FIG. 31, the forward HS-DSCH data packet 3101 is input to the encoder 3102. The encoder 3102 may generate a coded symbol by coding the forward HS-DSCH data packet 3101 according to a preset coding scheme, for example, a turbo coding scheme, and rate the generated coded symbol. It is provided to the matching unit 3103.
The rate matching unit 3103 includes the encoder 310.
In order to actually transmit the signal output from the signal 2 from the TTI on the physical channel, the signal is subjected to rate matching through symbol repetition and puncturing, and then output to the interleaver 3104. The interleaver 31
04 interleaves the signal output from the rate matching unit 3103 and provides it to the modulator 3105. The modulator 3105 includes the interleaver 310.
The signal output from 4 is a preset modulation method,
For example, QPSK system, 8PSK system, or M-ar
The signal is modulated according to the y QAM method, and the modulated signal is provided to the serial / parallel converter 3106. The serial / parallel converter 3106 parallelizes the signal output from the modulator 3105 into two bit streams, that is, a bit stream I and a bit stream Q, and a spreader 310.
Provide to 7. The spreader 3107 uses the same channelization code C as the two bitstreams so as to have orthogonality with other signals using other channelization codes.
After spreading using _OVSF , the spread bit stream I is provided to the adder 3109 and the spread bit stream Q is provided to the multiplier 3108. The multiplier 3108 outputs the bit stream Q
And j, and then provides them to the adder 3109. The adder 3109 adds the signal output from the multiplier 3108 and the signal output from the spreader 3107, and provides the result to the multiplier 3110. The multiplier 3110 is
The signal output from the adder 3109 is multiplied by a preset scrambling code C _SCRAMBLE to scramble, and the output is provided to the multiplier 3111. Here, the multiplier 3110 operates as a scrambler. The multiplier 3111 uses the multiplier 31.
The signal output from 10 is multiplied by the channel gain 3112 and provided to the summer 3143. Generally, the channel gain 3112 is a parameter for determining the transmission power of the HS-DSCH, has a large value when the SF is small, and is variable depending on the type of user data transmitted. When the HS-DSCH data packet is modulated by the modulator 3105 according to the QAM scheme, the transmitter of the Node B uses one channelization code so that the UE can perform the QAM demodulation on the received signal. Inform the UE of the HS-DSCH power level for. To this end, in the Node B transmitter, the HS-DSCH power level determiner 311 is used.
5 uses the maximum and minimum levels of HS-DSCH power and HS-DSCH power for one channelization code to channel gain 3112 to HS-DS.
CH power level is determined and said determined HS-DSC
The bit 3121 corresponding to the H power level is generated, and the bit 3121 is provided to the switch 3123.

User data 3116 transmitted through the DPCH is input to the encoder 3117. The encoder 3117 encodes the user data 3116 according to a preset coding scheme, and provides the encoded symbols to the rate matching unit 3118. The rate matcher 3118 performs rate matching on the signal output from the encoder 3117 through symbol repetition and puncturing so as to match the number of bits actually transmitted through the physical channel, and then the interleaver 3119 receives the rate matching. provide. The interleaver 3119 interleaves the signal output from the rate matching unit 3118 according to a preset interleaving method and provides the interleaved signal to the modulator 3120.
The modulator 3120 modulates the signal output from the interleaver 3119 according to a preset modulation method and provides the signal to the multiplexer 3217. The switch 3123 may change the HS-DS according to a corresponding transmission time point.
It controls its concatenation to provide a CH power level 3121, an HS-DSCH indicator 3122, and a reverse power offset 3147 to the multiplexer 3127.
Here, the switch 3123 controls the HS-DSCH.
Is modulated by the QAM method, the HS-DSCH
Providing a power level 3121 to the multiplexer 3127,
The reverse power offset 3147 is provided to the multiplexer 3127 when the HS-DSCH is not modulated by the QAM scheme. The multiplexer 3127 outputs the information output from the switch 3123 corresponding to the transmission time, TPC3126, Pilot3125, TFCI3.
The signals output from the modulator 124 and the modulator 3120 are multiplexed and provided to the serial / parallel converter 3128.

The serial / parallel converter 3218 converts the signal output from the multiplexer 3127 into two bit streams, that is, a bit stream I and a bit stream Q, and provides the signals to a spreader 3129. The spreader 3129 multiplies the bitstream I and the bitstream Q output from the serial / parallel converter 3218 by a preset channelization code C _OVSF and spreads them to use another channelization code. Have orthogonality with other signals. The diffuser 3129
Provides the spread bit stream Q to the multiplier 3130 and the spread bit stream I to the adder 3130.
Providing to 131. The multiplier 3130 multiplies the spread bitstream Q output from the spreader 3129 by j and provides the multiplied bitstream Q to the adder 3131.
The adder 3131 adds the signal output from the multiplier 3130 to the signal output from the spreader 3129 and provides the added signal to the multiplier 3132. The multiplier 3132
Supplies the signal output from the adder 3131 to the multiplier 3133 by multiplying the signal output from the adder 3131 with a scrambling code C _SCRAMBLE on a chip basis. Here, the multiplier 3132 operates as a scrambler. The multiplier 3133 multiplies the signal output from the multiplier 3132 by a channel gain 3134 and provides the signal to the summer 3143.

On the other hand, the transmitter of Node B shown in FIG. 31 further includes a transmitter for SHCCH. HS-
The DSCH control information 3135 is the serial / parallel converter 313.
6 is input. The serial / parallel converter 3136 converts the HS-DSCH control information 3135 into two bitstreams, that is, a bitstream I and a bitstream Q, and provides them to the spreader 3137. The spreader 3137 multiplies the signal output from the serial / parallel converter 3136 by a channelization code C _OVSF , spreads the spread signal, provides a spread bit stream I to an adder 3139, and spreads the bit stream Q. To the multiplier 313
Provide to 8. The multiplier 3138 is the spreader 31.
The spread bit stream Q output from 37
And j are multiplied and provided to the adder 3139. The adder 3139 adds the signal output from the multiplier 3138 to the spread bit stream I output from the spreader 3137 and provides the added signal to the multiplier 3140. The multiplier 3140 multiplies the signal output from the adder 3139 by a preset scrambling code C _SCRAMBLE , scrambles the scrambled code, and provides the scrambled signal to the multiplier 3141. Here, the multiplier 3140
Acts as a scrambler. The multiplier 314
1 multiplies the signal output from the multiplier 3140 with the channel gain 3142 and provides the signal to the summer 3143. The summer 3143 is configured to generate the DPCH signal (that is, the signal output from the multiplier 3133),
The generated SHCCH signal (that is, the multiplier 3
141), and the generated HS
-DSCH signal (that is, the signal output from the multiplier 3111) is added and provided to the filter 3144.
The filter 3144 filters the signal output from the summer 3143 and provides it to the RF processor 3145. The RF processor 3145 includes the filter 3
The signal output from 144 is converted into an RF band signal, and the RF band signal is transmitted over the air through an antenna 3146.

On the other hand, as explained in FIG. 29, HS-D
When the SCH indicator is transmitted through a separate channel using a channelization code different from that of the DPCH, the HS-DSCH power level is transmitted through the HS-DSCH indicator channel. Can be applied. However, the transmitter of the Node B should be changed so that the HS-DSCH indicator channel and the DPCH channel are separated by separate channelization codes.

Further, referring to FIGS. 30 and 32, H
The SHCCH slot format and the Node B transmitter for transmitting the S-DSCH power level and the reverse power offset in the forward direction will be described respectively. Figure 30
FIG. 6 illustrates a forward channel structure for transmitting HS-DSCH power level and reverse power offset over SHCCH in an HSDPA communication system according to another embodiment of the present invention. Referring to FIG. 30, as shown in FIG.
SHCCH for controlling S-DSCH is HS-D
SCH channelization code, MCS level indicating the modulation method and channel coding method used in the HS-DSCH, and HARQ information, eg, HA.
The RQ processor number and HARQ packet number are transmitted. Of course, the SHCCH can transmit not only the control information described above but also other control information. In the embodiment of the present invention, as shown in FIG.
The HS-DSCH power level and the reverse power offset are transmitted along with the control information described above through specific fields of the CCH. If the MCS level indicates that the HS-DSCH is modulated by the QAM scheme, the S
The HS-DSCH power level is transmitted over the HCCH. On the contrary, the MCS level is HS-DSCH is QA.
If it indicates that the signal is not modulated by the M method, the HS
The reverse power offset is transmitted through the field in which the DSCH power level is transmitted. FIG. 30 has a slot format in which an HS-DSCH indicator field is present in the forward DPCH.
The SCH indicator may be transmitted through a separate channel using a different channelization code than the DPCH.

Next, with reference to FIG. 32, a NodeB transmitter corresponding to the forward channel structure of FIG. 30 will be described. FIG. 32 shows the internal structure of the Node B transmitter corresponding to the forward channel structure of FIG.

Referring to FIG. 32, forward HS-DSC
The H data packet 3201 is input to the encoder 3202. The encoder 3202 encodes the forward HS-DSCH data packet 3201 according to a preset coding method, for example, a turbo coding method to generate a coded symbol, and the generated coded symbol is a rate matching unit. 3203.
The rate matching unit 3203 includes the encoder 320.
In order to transmit the signal output from the signal 2 during the TTI on the physical channel, the signal is subjected to rate matching through symbol repetition and puncturing and provided to the interleaver 3204. The interleaver 3
204 interleaves the signal output from the rate matching unit 3203 according to a preset method and provides it to the modulator 3205. The modulator 320
Reference numeral 5 modulates the signal output from the interleaver 3204 by a preset modulation method, for example, a QPSK method, an 8PSK method, or an M-ary QAM method, and provides the signal to the serial / parallel converter 3206. The serial / parallel converter 3206 parallel-converts the signal output from the modulator 3205 into two bit streams, that is, a bit stream I and a bit stream Q, and provides the signals to the spreader 3207. The diffuser 3207 is
The two bitstreams are spread using the same channelization code C _OVSF to be orthogonal with other signals using other channelization codes,
The spread bit stream I is provided to the adder 3209 and the spread bit stream Q is provided to the multiplier 3
208. The multiplier 3208 multiplies the spread bitstream Q output from the spreader 3207 by j and provides the result to the adder 3209. The adder 3209 adds the signal output from the multiplier 3208 and the signal output from the spreader 3207 and provides the result to the multiplier 3210. The multiplier 3210 is
The signal output from the adder 3209 is multiplied by the scrambling code C _SCRAMBLE to scramble in chip units, and the output is provided to the multiplier 3211.
Here, the multiplier 3210 operates as a scrambler. The multiplier 3211 is the multiplier 3210.
The signal output from the signal is multiplied by the channel gain 3212 and provided to the summer 3245.

On the other hand, the modulator 3205 causes the HS-D
When SCH data is modulated by the QAM method, the Node B transmitter may use HS- for one code so that the UE can perform QAM demodulation on the received signal.
Inform the UE of DSCH power. To this end, in the Node B transmitter, as described in FIG. 8, the HS-DSCH power level determiner 3215 determines the HS-DSCH power from the channel gain 3212 and the HS-DSCH power for one code. The bit 3218 corresponding to the HS-DSCH power level is determined using the maximum level and the minimum level, and the determined HS
-Provide the DSCH power level to the switch 3250.
When the HS-DSCH modulation method is not the QAM method,
The HS-DSCH power level determiner 3215 is
Do not generate DSCH power level 3218, but generate reverse power offset 3249 as described in FIG. The switch 3250 provides the HS-DSCH power level 3218 to the multiplexer 3220 when the HS-DSCH modulation scheme is QAM, and the HS
-If the DSCH modulation method is not the QAM method, the reverse power offset 3249 is provided to the multiplexer 3220. The multiplexer 3220 includes the HS-DSCH power level 3218, reverse transmission power offset 324.
9, HS-DSCH channelization code and other control information 3216, MCS level 3217, and HARQ information 3
219 is multiplexed and provided to the serial / parallel converter 3221. The serial / parallel converter 3221 is connected to the multiplexer 3
The signal output from 220 is two bit streams,
That is, the bit stream I and the bit stream Q are converted and provided to the spreader 3222. The diffuser 322
2 multiplies the signal output from the serial / parallel converter 3221 by the corresponding channelization code C _OVSF and spreads the spread bit stream I by the adder 322.
4 and the spread bit stream Q is provided to the multiplier 3223. The multiplier 3223 multiplies the spread bitstream Q output from the spreader 3222 by j and provides the result to the adder 3224.
The adder 3224 adds the multiplier 3 to the spread bit stream I output from the spreader 3222.
The signals output from the H.223 are added and provided to the multiplier 3225. The multiplier 3225 is connected to the adder 3224.
The signal output from the above is multiplied by a preset scrambling code C _SCRAMBLE and scrambled, and the output is provided to the multiplier 3226. Here, the multiplier 3225 operates as a scrambler.
The multiplier 3226 multiplies the signal output from the multiplier 3225 by a channel gain 3227 to add the sum 3
245 to provide.

User data 3228 transmitted through the DPCH is input to the encoder 3229. The encoder 3229 encodes the user data 3228 according to a preset coding scheme and provides the encoded symbols to the rate matching unit 3230. The rate matching unit 3230 includes the encoder 3229.
The rate-matched signal is output by performing rate matching through symbol repetition and puncturing so that the number of output bits matches the number of bits actually transmitted through the physical channel. Provide to Reaver 3231. The interleaver 3231 interleaves the signal output from the rate matching unit 3230 according to a preset interleaving method and provides the interleaver 3232 to the modulator 3232. The modulator 3232 modulates the signal output from the interleaver 3231 according to a preset modulation method and provides it to the multiplexer 3237. The multiplexer 3
237 is HS-DSCH indicator 3233, TF
CI3234, Pilot3235, and TPC323
6 are multiplexed and provided to the serial / parallel converter 3238.
The serial / parallel converter 3238 is connected to the multiplexer 323.
The signal output from 7 is converted into two bit streams, that is, a bit stream I and a bit stream Q and provided to the spreader 3239. The diffuser 3239
Spreads the signal output from the serial / parallel converter 3238 with a preset channelization code C _OVSF so as to have orthogonality with other signals using another channelization code. The diffuser 3239
Adds the spread bitstream I to an adder 324
1 and provides the spread bit stream Q to the multiplier 3240. The multiplier 3240 multiplies the spread bit stream Q output from the spreader 3239 by j and provides the result to the adder 3241.
The adder 3241 adds the signal output from the multiplier 3240 to the signal output from the spreader 3239 and provides the added signal to the multiplier 3242. The multiplier 3242
Is a scrambling code C _{S CRAMBLE} with a preset signal output from the adder 3241.
Multiply and scramble, and provide the output to the multiplier 3243. Here, the multiplier 3242 operates as a scrambler. The multiplier 3243 receives the signal output from the multiplier 3242 as a channel gain 3244.
And provides it to the summing device 3245. The adder 3
245 is the generated DPCH signal (that is, the signal output from the multiplier 3243), the generated SHCCH signal (that is, the signal output from the multiplier 3226), and the generated HS- DSCH signal
(That is, the signal output from the multiplier 3211) is added and provided to the filter 3246. The filter 32
46 filters the signal output from the adder 3245 and provides it to the RF processor 3247. R
The F processor 3247 converts the signal output from the filter 3246 into an RF band signal and transmits the RF band signal through the antenna 3248 over the air. Of course, as explained in FIG. 29, HS is transmitted through SHCCH.
The Node B transmitter that transmits the DSCH power level may also be applied to a channel structure in which the HS-DSCH indicator is transmitted through a separate channel using a channelization code different from that of the DPCH.

Next, referring to FIG. 33, Nod of FIG.
A UE receiver corresponding to the eB transmitter will be described. FIG. 33 is a block diagram showing a receiver structure of a UE corresponding to the Node B transmitter shown in FIG. FIG. 33
R, received through antenna 3301
The F band signal is input to the RF processor 3302. The RF processor 3302 converts the received RF band signal into a base band signal and provides the base band signal to the filter 3303.
The filter 3303 filters the signal output from the RF processor 3302 to obtain a multiplier 3304,
3316 and 3327. Here, the multiplier 3
304, 3316, and 3327 each operate as a descrambler, and input their respective input signals to the Node.
Multiply with the channelization code C _SCRAMBLE for the channel transmitted by the B transmitter. As a result, the multiplier 3304 outputs an HS-DSCH signal, which is a forward data channel, and the multiplier 3316 outputs the HS-DSCH signal.
Outputs a forward DPCH signal, the multiplier 3327
Outputs the SHCCH signal. The complex number signal output from the multiplier 3304 is complex to I and Q strea
It is input to the ms unit 3305. Said complex to I and Q s
The treams unit 3305 separates the signal output from the multiplier 3304 into a real number signal I and an imaginary number signal Q, and despreads the same.
Provide to 306. The despreader 3306 is the compass.
The real number signal I and the imaginary number signal Q output from the lex to I and Q streams section 3305 are multiplied by the channelization code C _OVSF used in the transmission device of Node B and despread, and the output is provided to the channel compensator 3310. To do.
Similarly, the complex number signal output from the multiplier 3316 is input to complex to I and Q streams 3317. The complex to I and Q streams 3317 separate the signal output from the multiplier 3316 into a real number signal I and an imaginary number signal Q, and provide the despreader 3318 with the separated signals. The despreader 3318 is used for the complex to I and Q streams3.
The real number signal I and the imaginary number signal Q output from 317 are multiplied by the channelization code C _OVSF used in the transmission device of the NodeB and despread, and the output is provided to the channel compensator 3319 and the demultiplexer 3307. . Also, the complex signal output from the multiplier 3327 is
Input to complex to I and Q streams 3328. In the complex to I and Q streams 3328, the signal output from the multiplier 3327 is a real number signal I and an imaginary number signal Q.
And provides the despreader 3329. The despreader 3329 is the complex to I and Q streams 3328.
The real number signal I and the imaginary number signal Q output from
It multiplies and despreads with the channelization code C _OVSF even used in the e B transmitter and provides its output to the channel compensator 3330. The signals I and Q output from the despreader 3318 are provided to the demultiplexer 3307. The demultiplexer 3307 is the despreader 3318.
And outputs the pilot 3308 by demultiplexing the signals I and Q output from The output pilot is input to the channel estimator 3309. The channel estimator 3309 detects a channel estimation value through distortion estimation by a radio channel and the channel compensator 331.
0, 3319, 3330.

The channel compensators 3310, 3319,
3329 compensates for distortion caused by the wireless channel using the channel estimate. That is, the channel compensator 3310 performs channel compensation on the signal output from the despreader 3306 to perform parallel / serial converter 3311.
To provide. The channel compensator 3319 channel-compensates the signal output from the despreader 3318 and provides the signal to the parallel / serial converter 3320. The channel compensator 3330 channel-compensates the signal output from the despreader 3329 and provides the signal to the parallel / serial converter 3331.

The parallel / serial converters 3311 and 332
0 and 3331 are the channel compensators 331, respectively.
The signals output from 0, 3319 and 3330 are serially converted into one bit stream. The signal output from the parallel / serial converter 3331 is finally the HS-DS.
The signal output as the CH control information 3332 and output from the parallel / serial converter 3320 is the demultiplexer 33.
21, TPC 3322, TFCI 3323, and HS-DSCH indicator 3324 partitioned by switch 3325, HS-DSCH power level 332.
6 and the reverse transmit power offset.
The demultiplexer 3321 also outputs a forward data signal, and the forward data signal is channel-decoded by a demodulator 3333, a deinterleaver 3334, and a decoder 3335 to obtain forward user data 3336. Finally output. In addition, the parallel / serial converter 3
The signal output from 311 is channel-decoded by the demodulator 3312, the deinterleaver 3313, and the decoder 3314, and finally output as a forward data packet 3315. Here, the decoder 3314 is
If the forward data packet 3315 is modulated by the QAM scheme, the forward data packet 3 using the received HS-DSCH power level 3326.
315 is QAM demodulated.

Next, referring to FIG. 34, Nod in FIG.
A UE receiver corresponding to the eB transmitter will be described. FIG. 34 is a UE corresponding to the Node B transmitter of FIG. 32.
It is a block diagram which shows the internal structure of a receiver. Referring to FIG. 34, the RF received through the antenna 3401
The band signal is input to the RF processor 3402. R
The F processor 3402 converts the received RF band signal into a base band signal and provides the base band signal to the filter 3403. The filter 3403 filters the signal output from the RF processor 3402 to multiply the multipliers 3404 and 3404.
416 and 3425, respectively. Here, the multipliers 3404, 3416, and 3425 each operate as a descrambler, and input their respective input signals to the N signals.
Multiply with the channelization code for the channel transmitted by the transmitter of node B. As a result, the multiplier 3404 outputs the forward data channel HS-DSC.
H signal is output, and the multiplier 3316 outputs the forward DPC.
The H signal is output, and the multiplier 3325 outputs the SHCCH signal. The complex number signal output from the multiplier 3404 is input to complex to I and Q streams 3405. The complex to I and Q streams 3405 is
The signal output from the multiplier 3404 is separated into a real number signal I and an imaginary number signal Q and provided to the despreader 3406. The despreader 3406 includes the complex to I and Q streaks.
The real number signal I and the imaginary number signal Q output from ms3405 are multiplied by a preset channelization code C _OVSF and despread, and the output is provided to the channel compensator 3410. Similarly, the signal output from the multiplier 3416 is input to complex to I and Q streams 3417. The complex to I and Q streams 3417 separates the signal output from the multiplier 3416 into a real number signal I and an imaginary number signal Q, and provides the despreader 3418 with the separated signal. The despreader 3418 is used for the complex to I and Q streams3.
The real number signal I and the imaginary number signal Q output from 417 are multiplied by a preset channelization code C _OVSF and despread, and the output is provided to the channel compensator 3419 and the demultiplexer 3407. Also, the signal output from the multiplier 3425 is complex to I and Q streams34.
26 is input. Said complex to I and Q streams3
426 separates the signal output from the multiplier 3425 into a real number signal I and an imaginary number signal Q, and supplies the real number signal I and the imaginary number signal Q to the despreader 3427. The despreader 3427 is connected to the complex to I a
nd Q streams 3426 output real number signal I and imaginary number signal Q are preset channelization code C
_It is multiplied by _OVSF and despread, and its output is provided to channel compensator 3428.

The demultiplexer 3407 demultiplexes the signal output from the despreader 3418 and outputs a pilot 3408. The pilot output is input to the channel estimator 3409. The channel estimator 34
09 uses the pilot 3408 to detect a channel estimation value through distortion estimation by a radio channel, and detects the detected channel estimation value from the channel compensator 34.
10, 3419, 3428. The channel compensators 3410, 3419 and 3428 compensate for the distortion of the signals output from the despreaders 3406, 3418 and 3427, respectively, using the channel estimation values output from the channel estimator 3409. That is, the channel compensator 3410 performs channel compensation on the signal output from the despreader 3406 to perform parallel / serial converter 3411.
To provide. The channel compensator 3419 channel-compensates the signal output from the despreader 3418 and provides the signal to the parallel / serial converter 3420. The channel compensator 3428 channel-compensates the signal output from the despreader 3427 and provides the signal to the parallel / serial converter 3429.

The parallel / serial converters 3411 and 342.
0 and 3429 are channel compensators 3410 and 3 respectively.
419 and 3428 output signals are serially converted to demodulator 3412, demultiplexer 3421, and demultiplexer 3
430. The demodulator 3412 is connected to the parallel /
The signal output from the serial converter 3411 is output to the Node B
The data is demodulated by the method corresponding to the modulation method used in the transmitting device and provided to the deinterleaver 3413.
The deinterleaver 3413 includes the demodulator 3412.
The signal output from is deinterleaved by the deinterleaving method corresponding to the interleaving method used in the Node B transmitter and provided to the decoder 3414. The decoder 3414 outputs the signal output from the deinterleaver 3413 to the No.
HS-decoding is performed by a decoding method corresponding to the coding method used in the de B transmitter.
The DSCH data 3415 is output. Here, when the forward data is QAM-modulated, the demodulator 3412
Demodulation is performed using the received HS-DSCH power level 3433.

The demultiplexer 3421 outputs the signal output from the parallel / serial converter 3420 to the TPC 342.
2, demultiplexing into TFCI 3423 and HS-DSCH indicator 3424. The demultiplexer 3421
Further outputs a forward data signal, which is forwarded by the demodulator 3435 and the deinterleaver 343.
6, and channel decoded by decoder 3437,
It is finally output as the forward data 3438. Also, the demultiplexer 3430 includes the parallel / serial converter 34.
The signal output from 29 is demultiplexed into HS-DSCH channelization code and other information 3431, MCS level 3432, input to switch 3439, and HARQ information 3434. When the MCS level indicates that the modulation method is the QAM method, the switch 3439 is set to H level.
Output S-DSCH power level 3433. The MC
If the S level indicates that the modulation scheme is not the QAM scheme, the switch 3439 outputs a reverse power offset 3440.

FIG. 35 shows an N according to another embodiment of the present invention.
The operation process of the node B is shown. Referring to FIG. 35, the step
At floor 3502, the Node B is the HSDPA data.
HS-DSCH indicator that indicates the presence or absence of packets
, And proceed to step 3502. 9 and 21
As explained, the H required during the HSDPA service.
S-DSCH power level and reverse transmit power offset
Is live only when the HS-DSCH indicator is present.
Is made. In step 3503, the Node B determines that the Node B is
Check if HS-DSCH indicator is on
To do. As a result of the inspection, the HS-DSCH indicator
Node B is off, the Node B determines 350.
Go to 4. In step 3504, the Node B
After waiting for the next TTI, return to step 3502. However
Meanwhile, in step 3503, as a result of the inspection, the HS-DS
If the CH indicator is on, the Node B
Proceeds to step 3505. In step 3505,
The Node B transmits data over the HS-DSCH.
Data packet modulation method and channel coding method
After determining the MCS level, go to step 3506.
proceed. In operation 3506, the Node B determines that the Node B
It is checked whether the HS-DSCH modulation method is QAM method.
Inspect. Here, the HS-DSCH modulation method is QAM.
The reason for checking whether or not the system is the HS-DSC
HS-DSCH when the H modulation method is the QAM method
The power level should be transmitted, said HS-DSC
Reverse power off when H modulation is not QAM
This is because the set should be transmitted. Step 350
As a result of the inspection of No. 6, the HS-DSCH modulation method is QAM.
If not, the Node B proceeds to step 3508.
To go. In step 3508, the Node B is
Maximum level of HS-DSCH power that can be assigned to a code
After determining the level and minimum level, proceed to step 3510.
It In step 3510, the Node B determines that the HS-DS.
After determining the CH power level, proceed to step 3511.
It Meanwhile, as a result of the inspection in step 3506, the HS-DS
When the CH modulation method is not the QAM method, the Node
B proceeds to step 3507. In step 3507, the
Node B is SIR_estAnd SIR_targetWhen
Check if the difference between the two exceeds a first critical value. Previous
As a result of the inspection, the SIR_estAnd SIR_target
N does not exceed the first critical value, the N
Node B returns to step 3504. On the other hand, the SIR
_estAnd SIR_{target t}Is the first critical
If the value is exceeded, the Node B determines in step 3509.
Proceed to. In step 3509, the Node B determines that S
IR_estAnd SIR _targetIs the first critical
Between the Node B and the UE because the value is exceeded.
It is determined that the channel status of the
Reverse power offset is determined as described above. Step 35
At 11, the Node B is connected to the Node B and the U
Inverse corresponding to the forward channel set between E and
Through directional channel, ie DPCH, S-DPC
Through H or SHCCH, the HS-DSCH power
After transmitting the power level or reverse power offset
The process is finished.

FIG. 36 shows a U according to another embodiment of the present invention.
The operation process of E is shown. Referring to FIG. 36, step 360.
At 2, the UE is HS-based on the received DPCH signal.
After detecting the DSCH indicator, proceed to step 3603. In step 3603, the UE sends the HS-DS.
Check if CH indicator is on. If the result of the check is that the HS-DSCH indicator is not on, that is, the HS-DSCH indicator is off, the UE proceeds to step 3604. In step 3604, the UE waits until the next TTI and then returns to step 362. If the result of the check in step 3603 is that the HS-DSCH indicator is on, the UE proceeds to step 3605. Stage 3
At 605, the UE receives a SHCCH signal and detects an MCS level from the received SHCCH signal. In step 3606, the UE checks whether the HS-DSCH modulation scheme is QAM scheme. If the result of the check is that the HS-DSCH modulation scheme is not the QAM scheme, the UE proceeds to step 3608. Stage 3
At 608, the UE proceeds to step 3610 after detecting a reverse power offset. In step 3610, the UE determines transmission power of the HS-DPCCH using the detected reverse power offset, and then ends the process. As a result of the inspection in step 3606, the HS-D
When the SCH modulation method is the QAM method, the UE is
Proceed to step 3607. In step 3607, the UE
After detecting the HS-DSCH power level, step 36
Go to 09. Here, the Node B and the UE
If the UE has a forward channel structure as described with reference to FIG. 29, the UE receives a DPCH signal and detects the HS-DSCH power level from the received DPCH. On the other hand, if the UE has a forward channel structure as described with reference to FIG. 30, the UE receives an SHCCH signal, and the HS- is received from the received SHCCH signal.
Detect DSCH power level. In step 3609, the UE performs HS-DSCH demodulation using the detected HS-DSCH power level, and then ends the process.

As described above, the detailed description of the present invention has been made with reference to specific embodiments, but the scope of the present invention should not be limited to the above embodiments.
It will be apparent to those of ordinary skill in the art that various modifications are possible within the scope of the invention.

[0122]

As described above, the present invention provides HSDPA.
In the communication system using the method, the HSDPA
HS- that carries the information necessary to service the scheme
Enables reverse transmit power control for DPCCH signals. Therefore, in the communication system using the HSDPA method, the HS-D may be changed according to the channel state of the UE.
Enables control of reverse transmission power of PCCH
Improve the quality of PA services. Also, when the HSDPA data is modulated by the QAM method, the HSDPA
Set the power level of HS-DSCH for transmitting PA data to U
Informing E, the UE can demodulate the HSDPA data reliably.

[Brief description of drawings]

FIG. 1 is a schematic diagram illustrating a forward channel structure of a communication system using a general HSDPA scheme.

FIG. 2 is a diagram illustrating a forward DPCH structure of a communication system using a general HSDPA scheme.

FIG. 3 is a diagram illustrating another structure of a forward DPCH of a communication system using a general HSDPA scheme.

FIG. 4 is a diagram illustrating a reverse DPCH structure of a communication system using a general HSDPA scheme.

FIG. 5A is a diagram showing an AMC system of HS-DSCH in a communication system using a general HSDPA system.

FIG. 5B is a diagram showing an AMC system of HS-DSCH in a communication system using a general HSDPA system.

FIG. 5C is a diagram showing an AMC system of HS-DSCH in a communication system using a general HSDPA system.

FIG. 6 is a diagram showing a method for determining an HS-DSCH power level in a communication system using a general HSDPA method.

FIG. 7 is a schematic diagram showing a channel allocation structure when a UE exists in a soft handover area in a communication system using a general HSDPA method.

FIG. 8 is a diagram showing a method for determining an HS-DSCH in a communication system using the HSDPA method according to the embodiment of the present invention.

FIG. 9 is a diagram illustrating a forward channel structure of a communication system using an HSDPA scheme according to an exemplary embodiment of the present invention.

FIG. 10 is a diagram illustrating a forward DPCH structure of a communication system using an HSDPA scheme according to another embodiment of the present invention.

FIG. 11 is a diagram illustrating a forward DPCH structure of a communication system using an HSDPA scheme according to another embodiment of the present invention.

FIG. 12 is a diagram showing an SHCCH structure of a communication system using the HSDPA method according to another embodiment of the present invention.

13 is a No corresponding to the forward channel structure of FIG.
It is a block diagram which shows the transmitter apparatus structure of de B.

14 is an N corresponding to the forward channel structure of FIG.
It is a block diagram which shows the transmitter structure of node B.

FIG. 15 is a block diagram showing a receiver structure of a UE corresponding to the Node B transmitter of FIG.

16 is a block diagram showing a receiver structure of a UE corresponding to the transmitter of the Node B of FIG.

FIG. 17 is a flowchart showing an operation process of a Node B in the HSDPA system according to the embodiment of the present invention.

FIG. 18 is a flowchart showing an operation process of a UE in the HSDPA system according to the embodiment of the present invention.

FIG. 19 illustrates a scheme for determining a reverse power offset according to an embodiment of the present invention.

FIG. 20 illustrates a table showing bit values for transmitting a reverse power offset according to an embodiment of the present invention.

FIG. 21 is a schematic diagram illustrating a forward channel structure of a communication system using an HSDPA scheme according to another embodiment of the present invention.

FIG. 22 is a diagram illustrating a forward DPCH structure of a communication system using an HSDPA scheme according to another embodiment of the present invention.

FIG. 23 is a diagram illustrating a forward DPCH structure of a communication system using an HSDPA scheme according to another embodiment of the present invention.

FIG. 24 is an N corresponding to the forward channel structure of FIG. 21.
It is a block diagram which shows the receiver structure of node B.

FIG. 25 shows N corresponding to the forward channel structure of FIG.
It is a block diagram which shows the transmitter structure of node B.

FIG. 26 is a block diagram showing a transmitter / receiver structure of a UE corresponding to the transmitter structure of the Node B of FIG. 25.

FIG. 27 is a diagram showing an operation process of a Node B in the HSDPA system according to another embodiment of the present invention.

FIG. 28 is a diagram illustrating an operation process of a UE in an HSDPA system according to another embodiment of the present invention.

FIG. 29 is a diagram illustrating a forward channel structure for transmitting an HS-DSCH power level and a reverse power offset through a DSCH in a communication system using an HSDPA scheme according to another embodiment of the present invention.

FIG. 30 is a diagram illustrating a forward channel structure for transmitting an HS-DSCH power level and a reverse power offset through a SHCCH in a communication system using the HSDPA scheme according to another embodiment of the present invention.

FIG. 31 shows N corresponding to the forward channel structure of FIG.
It is a figure which shows the transmitter structure of node B.

32 is an N corresponding to the forward channel structure of FIG.
It is a figure which shows the transmitter structure of node B.

FIG. 33 is a block diagram illustrating a receiver structure of a UE corresponding to the Node B transmitter of FIG. 31.

FIG. 34 is a block diagram illustrating a UE receiver structure corresponding to the Node B transmitter of FIG. 32.

FIG. 35 is a Node B according to another embodiment of the present invention.
FIG. 6 is a diagram showing an operation process of FIG.

FIG. 36 is a diagram illustrating a process of performing a UE according to an exemplary embodiment of the present invention.

   ─────────────────────────────────────────────────── ─── Continued front page    (72) Inventor Choi             Republic of Korea Gyeonggi-do Seongnam-si             None) Nutimaul 306, No. 302 (72) Inventor Lee Zhou Ho             Republic of Korea, Gyeonggi-do Suwon-si, Batada-dong             None) 730 modern apartments in Sargugor 803             號 F term (reference) 5K067 CC08 DD42 DD48 EE10 GG08                       GG09 HH22

Claims (37)

[Claims] 1. In a base station apparatus (Node B) transmitting a reverse transmission power offset and a forward data channel power level in a high speed packet data communication system, a first reverse received from a user equipment (UE). Measure the signal-to-interference ratio (SIR) of the directional channel signal,
The difference between the measured signal-to-interference ratio and the preset target signal-to-interference ratio is compared with a preset critical value, and control information for the packet data received by the terminal is transmitted according to the comparison result. A reverse power offset determiner for determining a reverse power offset applied to a second reverse dedicated channel, and a modulation applied to a forward data channel for transmitting the packet data according to a channel state set with the UE. A forward data channel power level determiner for determining a scheme and determining a forward data channel power level that is channel gain related control information of the forward data channel when the determined modulation scheme is a higher order modulation scheme. And the UE through the reverse power offset or the forward data channel power level in the forward direction. Apparatus characterized by including: a transmitter for transmitting. 2. The reverse transmission power offset determiner measures a signal to interference ratio using the first reverse dedicated channel signal, and measures the measured signal to interference ratio and a preset target signal. A channel condition determiner for calculating a difference between an interference ratio and a reverse power offset applied to the second reverse dedicated channel according to the comparison result of comparing the difference with a preset threshold value. And a transmit power determiner for determining. 3. The reverse power offset is the UE
2. The apparatus according to claim 1, wherein the transmission power is added to the transmission power of the second reverse dedicated channel currently transmitted by. 4. The apparatus of claim 1, wherein the transmitter does not transmit the reverse power offset when the difference is less than a certain critical value among the preset critical values. . 5. The forward data channel power level determiner determines the forward data channel power level in consideration of a maximum power and a minimum power that can be assigned to the forward data channel. 1. The device according to 1. 6. The apparatus of claim 1, wherein the forward data channel power level determiner does not generate the forward data power level if the modulation scheme is not a high order modulation scheme. 7. In a device for transmitting and receiving a reverse power offset and a forward data channel power level in a high speed packet data communication system, a signal to interference ratio of a first reverse dedicated channel signal received from a terminal (UE) is calculated. The difference between the measured signal-to-interference ratio and the preset target signal-to-interference ratio is measured and compared with a preset critical value, and the U
Forward data for determining a reverse power offset applied to a second reverse dedicated channel for transmitting control information for packet data received by E, and transmitting the packet data according to a channel state set with the UE. Determining a modulation scheme to be applied to a channel, and determining a forward data channel power level that is channel gain related control information of the forward data channel when the determined modulation scheme is a higher order modulation scheme, A base station (Node B) for transmitting the reverse power offset and the forward data channel power level to the UE through the forward direction.
And receiving a reverse power offset transmitted through the forward direction, adjusting the transmission power of the second reverse dedicated channel currently being transmitted by the reverse power offset, and transmitting the forward data offset through the forward direction. UE receiving a channel power level and demodulating the packet data according to the received forward data channel power level
And a device including. 8. The Node B measures a signal-to-interference ratio of a first reverse dedicated channel signal received from the UE, and calculates a difference between the measured signal-to-interference ratio and the target signal-to-interference ratio. And a reverse transmission power offset determiner for determining a reverse transmission power offset applied to the second reverse dedicated channel, the forward data according to a channel state set with the UE. A forward data channel power level determiner that determines a modulation scheme to be applied to a channel, and determines the forward data channel power level when the determined modulation scheme is a higher order modulation scheme; and the reverse power. 8. A transmitter for transmitting an offset or the forward data channel power level to the terminal through the forward direction. . 9. The apparatus of claim 7, wherein the forward data channel power level is determined in consideration of a maximum power and a minimum power that can be assigned to the forward data channel. 10. The reverse power offset is the U
8. The apparatus according to claim 7, wherein the transmission power is added to the transmission power of the second reverse dedicated channel currently transmitted by E. 11. A method of controlling a base station apparatus (Node B) transmitting a reverse power offset and a forward data channel power level in a high speed packet data communication system, the first reverse direction received from a terminal unit (UE). The signal-to-interference ratio of the dedicated channel signal is measured, and the difference between the measured signal-to-interference ratio and the preset target signal-to-interference ratio is compared with a preset critical value, and the result of the comparison, Determining a reverse power offset applied to a second reverse dedicated channel for transmitting control information for the packet data received by the UE terminal, and transmitting the packet data according to a channel state set with the UE Determining a modulation scheme to be applied to the forward data channel, and if the determined modulation scheme is a higher-order modulation scheme, the forward direction Determining a forward data channel power level that is channel gain related control information of a data channel, and transmitting the reverse power offset or the forward data channel power level to the UE through the forward direction. How to characterize. 12. The reverse power offset is the U
12. The method of claim 11, wherein the transmission power is added to the transmission power of the second reverse dedicated channel currently transmitted by E. 13. The method of claim 11, wherein the reverse power offset is not transmitted if the difference is less than a particular critical value of the preset critical values. 14. The method of claim 11, wherein the fast forward data channel power level is determined considering the maximum power and the minimum power that can be assigned to the forward data channel. 15. The method of claim 11, further comprising: not generating the forward data power level if the modulation scheme is not a higher order modulation scheme. 16. A method for transmitting and receiving a reverse power offset and a forward data channel power level in a high speed packet data communication system, wherein a first reverse direction received by a base station (Node B) from a base station (UE) is used. Measuring the signal-to-interference ratio of the channel signal, comparing the difference between the measured signal-to-interference ratio and a preset target signal-to-interference ratio with a preset critical value, and by the result of the comparison, the Determining a reverse power offset applied to a second reverse dedicated channel carrying control information for the packet data received by the UE;
If a modulation scheme applied to a forward data channel for transmitting the packet data is determined according to a channel state set with the UE, and the determined modulation scheme is a higher-order modulation scheme, the forward data channel Determining a forward data channel power level, which is channel gain related control information, and transmitting the reverse power offset or the forward data channel power level to the UE through the forward direction; A reverse power offset transmitted through the forward data channel power level, adjusting the transmit power of the second reverse dedicated channel currently transmitted in consideration of the reverse power offset, and the forward data channel power level through the forward direction. And the packet according to the received forward data channel power level. And a step of demodulating the received data. 17. The reverse power offset is the U
17. The method of claim 16, wherein the transmission power is added to the transmission power of the second reverse dedicated channel currently transmitted by E. 18. The method of claim 16, wherein the forward data channel power level is determined considering a maximum power and a minimum power that can be assigned to the forward data channel. 19. A method of controlling reverse transmission power in a high speed packet data communication system, the method comprising: measuring a signal-to-interference ratio of a first reverse dedicated channel signal received from a terminal (UE); Calculating a difference between a preset signal-to-interference ratio and a preset target signal-to-interference ratio, comparing the difference with a preset critical value, and receiving the UE terminal according to a result of the comparison. Determining a reverse power offset to be applied to a second reverse dedicated channel transmitting control information for the packet data, and transmitting the determined reverse power offset to the UE through a forward direction. A method comprising. 20. The reverse power offset is the U
20. The method of claim 19, wherein the transmission power is added to the transmission power of the second reverse dedicated channel currently transmitted by E. 21. The method of claim 19, further comprising: not transmitting the reverse power offset to the UE when the difference is less than a predetermined critical value among the preset critical values. the method of. 22. A device for controlling reverse transmission power in a high speed packet data communication system, wherein a signal to interference ratio is measured using a first reverse dedicated channel signal received from a terminal (UE), and A channel condition determiner for calculating a difference between a measured signal-to-interference ratio and a preset target signal-to-interference ratio, and comparing the difference with a preset critical value, and by the result of the comparison, the UE A transmission power determiner for determining a reverse power offset applied to a second reverse dedicated channel for transmitting control information for received packet data, and transmitting the determined reverse power offset to the UE through a forward direction. And a transmitter, the device comprising: 23. The reverse power offset is equal to the U
23. The apparatus of claim 22, wherein the transmission power is added to the transmission power of the second reverse dedicated channel currently transmitted by E. 24. A method for controlling reverse transmission power in a high speed packet data communication system, comprising: a signal to interference ratio of a first reverse dedicated channel signal received from a terminal (UE) by a base station (Node B). (S
IR) and calculating the difference between the measured signal-to-interference ratio and the preset target signal-to-interference ratio by the Node B,
Comparing the difference with a preset threshold value, the result of the comparison determines a reverse power offset applied to a second reverse dedicated channel for transmitting control information for packet data received by the UE, Transmitting the determined reverse power offset to the UE in the forward direction, and receiving the reverse power offset in the forward direction, the UE receives the currently transmitted second reverse dedicated channel. Adjusting the transmit power by the reverse power offset. 25. The reverse power offset is the U
25. The method of claim 24, wherein the transmission power is added to the transmission power of the second reverse dedicated channel currently transmitted by E. 26. The method further comprising transmitting the reverse power offset to the UE when the difference is less than a predetermined threshold among the preset thresholds. The method described. 27. In a device for controlling reverse transmission power in a high speed packet data communication system, a signal to interference ratio of a first reverse dedicated channel signal received from a terminal (UE) is measured, and the measured Calculate the difference between the signal-to-interference ratio and the preset target signal-to-interference ratio, compare the difference with a preset critical value, and depending on the result of the comparison, for the packet data received by the UE A base station (Node B) for determining a reverse power offset applied to a second reverse dedicated channel for transmitting control information, and transmitting the determined reverse power offset to the UE through a forward direction; UE that receives the reverse power offset through a direction and adjusts the transmission power of the currently transmitted second reverse dedicated channel by the reverse power offset.
And a device including. 28. The Node B measures a signal-to-interference ratio of a first reverse dedicated channel signal received from the UE, and measures the measured signal-to-interference ratio and a preset target signal-to-interference ratio. A channel condition determiner for calculating a difference between the UE and the UE comparing the difference with the preset threshold value;
A transmission power determiner for determining a reverse power offset applied to a second reverse dedicated channel for transmitting control information for received packet data, and transmitting the determined reverse power offset to the UE through a forward direction. 28. The apparatus of claim 27, comprising: 29. The reverse power offset is the U
28. The apparatus of claim 27, wherein the transmission power is added to the transmission power of the second reverse dedicated channel currently transmitted by E. 30. In a method of transmitting a forward data channel power level in a high speed packet data communication system, estimating a channel condition set with a terminal (UE),
Determining a modulation scheme applied to a forward data channel for transmitting packet data according to the estimated channel state; and, if the determined modulation scheme is a higher-order modulation scheme, a channel of the forward data channel. Determining a forward data channel power level that is gain-related control information, transmitting the determined forward data channel power level to the UE through the forward direction, and the UE transmits the forward data channel power level. Using the packet data to demodulate the packet data. 31. The method of claim 30, wherein the forward data channel power level is determined considering a maximum power and a minimum power that can be assigned to the forward data channel. 32. A device for transmitting a forward data channel power level in a high speed packet data communication system, wherein a modulation applied to a forward data channel for transmitting packet data according to a channel state set with a terminal (UE). A modulation scheme determiner for determining a scheme, and, if the determined modulation scheme is a higher-order modulation scheme, forward data for determining a forward data channel power level that is channel gain related control information of the forward data channel. A channel power level determiner, transmitting the determined forward data channel power level to the UE in the forward direction, and the UE demodulating the packet data using the forward data channel power level. And a transmitter, the device comprising: 33. The apparatus of claim 32, wherein the forward data channel power level determiner considers a maximum power and a minimum power that can be assigned to the forward data channel. 34. A method of transmitting and receiving a forward data channel power level in a high speed packet data communication system, comprising: estimating a channel state set with a terminal (UE) by a base station (Node B); Determining a modulation scheme to be applied to a forward data channel for transmitting packet data according to the channel state, and, if the determined modulation scheme is a high-order modulation scheme, the Node B controls the forward data channel. Determining a forward data channel power level, which is channel gain related control information, and transmitting the forward data channel power level to the UE through the forward direction, and receiving the forward data channel power level through the forward direction. Then, the UE receives the power according to the forward data channel power level. And demodulating the packet data. 35. The method of claim 34, wherein the forward data channel power level is determined considering a maximum power and a minimum power that can be assigned to the forward data channel. 36. An apparatus for transmitting and receiving a forward data channel power level in a high speed packet data communication system, estimating a channel state set with a terminal (UE),
A modulation scheme applied to a forward data channel for transmitting packet data is determined according to the estimated channel state, and when the determined modulation scheme is a higher order modulation scheme, a channel gain related to the forward data channel. A base station (Node B) for determining a forward data channel power level that is control information and transmitting the forward data channel power level to the UE through the forward direction, and a forward data channel power level through the forward direction. A UE that receives and demodulates the packet data according to the received forward data channel power level. 37. The Node B is a modulation scheme determiner that determines a modulation scheme applied to the forward data channel according to a channel state set with the UE, and the determined modulation scheme is a high-order modulation. And a forward data channel power level determiner for determining the forward data channel power level, and transmitting the determined forward data channel power level to the UE through the forward direction to obtain the forward data. 37. An apparatus as claimed in claim 36, comprising a transmitter adapted to demodulate the packet data using a channel power level.