JP2003133683A - Stack mounting structure of electronic parts and method for stack mounting electronic parts - Google Patents
Stack mounting structure of electronic parts and method for stack mounting electronic partsInfo
- Publication number
- JP2003133683A JP2003133683A JP2001326852A JP2001326852A JP2003133683A JP 2003133683 A JP2003133683 A JP 2003133683A JP 2001326852 A JP2001326852 A JP 2001326852A JP 2001326852 A JP2001326852 A JP 2001326852A JP 2003133683 A JP2003133683 A JP 2003133683A
- Authority
- JP
- Japan
- Prior art keywords
- electronic component
- insulating layer
- opening
- photosensitive resin
- electronic
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L25/0657—Stacked arrangements of devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/16237—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bonding area disposed in a recess of the surface of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/0651—Wire or wire-like electrical connections from device to substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06555—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
- H01L2225/06565—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking the devices having the same size and there being no auxiliary carrier between the devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06555—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
- H01L2225/06568—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking the devices decreasing in size, e.g. pyramidical stack
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01078—Platinum [Pt]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、電子機器等に用い
られる電子部品を配線板に対して高密度で実装すること
ができる電子部品の積層実装構造および積層実装方法に
関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a laminated mounting structure and a laminated mounting method for electronic components, which are capable of mounting electronic components used in electronic equipment or the like on a wiring board at high density.
【０００２】[0002]
【従来の技術】電子機器等に使用される電子部品は、通
常、印刷配線板上に実装されている。図５は、電子部品
の実装構造の一例を示す断面図である。図５に示す電子
部品の実装構造では、印刷配線板５１に電子部品５３が
実装されている。印刷配線板５１上には、導電体をエッ
チング等によってパターニングして形成された複数の電
子部品実装用ランド５２が形成されており、各電子部品
実装用ランド５２に、電子部品５３の接続端子となる接
続リード５４が、半田５５によって、それぞれ電気的に
接続されている。2. Description of the Related Art Electronic components used in electronic equipment and the like are usually mounted on a printed wiring board. FIG. 5 is a sectional view showing an example of a mounting structure of an electronic component. In the electronic component mounting structure shown in FIG. 5, the electronic component 53 is mounted on the printed wiring board 51. A plurality of electronic component mounting lands 52 formed by patterning a conductor by etching or the like are formed on the printed wiring board 51. Each electronic component mounting land 52 has a connection terminal for an electronic component 53. The connecting leads 54 are electrically connected by solder 55.
【０００３】通常、１枚の印刷配線板５１に、複数の電
子部品５３が、同様の実装構造によって実装されてい
る。Usually, a plurality of electronic components 53 are mounted on one printed wiring board 51 by the same mounting structure.
【０００４】また、特開２０００−２００９７２号公報
には、ＢＧＡパッケージ等の電子部品を配線板に搭載す
る際に、電子部品と配線層との電気的接続および絶縁層
の絶縁性を良好にするために、配線板表面に設けられた
絶縁層に、電子部品の半田バンプ部に対応して開口部を
形成して、その開口部内に設けられた導電体層によっ
て、電子部品と配線層とを電気的に接続する構成が開示
されている。Further, in Japanese Patent Laid-Open No. 2000-200972, when an electronic component such as a BGA package is mounted on a wiring board, electrical connection between the electronic component and the wiring layer and insulation of the insulating layer are improved. Therefore, an opening is formed in the insulating layer provided on the surface of the wiring board so as to correspond to the solder bump portion of the electronic component, and the electronic component and the wiring layer are separated by the conductor layer provided in the opening. A configuration for electrically connecting is disclosed.
【０００５】この公報に開示された構成は、配線板表面
の平滑性を確保し、ガス抜きを行うために、絶縁層に開
口部を形成して、配線板に対して電子部品を実装するよ
うになっており、配線板に対して複数の電子部品がそれ
ぞれ個別に実装されるようになっており、複数の電子部
品を高密度に実装することができるものではない。In the structure disclosed in this publication, in order to ensure the smoothness of the surface of the wiring board and perform degassing, an opening is formed in the insulating layer to mount electronic parts on the wiring board. Since a plurality of electronic components are individually mounted on the wiring board, the plurality of electronic components cannot be mounted at high density.
【０００６】さらに、特開平６−２７５９５９号公報に
は、感光性樹脂からなる絶縁層に導通部となる穴を設け
て、絶縁層を挟んで上層および下層に設けられた配線層
をメッキによって電気的に接続させる、所謂フォトビア
方式のビルドアップ配線板の構成が開示されている。Further, in Japanese Unexamined Patent Publication No. 6-275959, a hole serving as a conductive portion is provided in an insulating layer made of a photosensitive resin, and wiring layers provided in an upper layer and a lower layer sandwiching the insulating layer are electrically plated. The structure of a so-called photo-via type build-up wiring board that is electrically connected is disclosed.
【０００７】この公報に開示された構成も、配線板全面
に１つの層として構成された絶縁層にフォトビアが設け
られて、このフォトビアを介して、各配線層の導電体パ
ターン同士を接続するものであり、複数の電子部品を高
密度に実装することができないという問題がある。Also in the structure disclosed in this publication, a photo via is provided in the insulating layer formed as one layer on the entire surface of the wiring board, and the conductor patterns of the respective wiring layers are connected via the photo via. Therefore, there is a problem that a plurality of electronic components cannot be mounted at high density.
【０００８】いずれの場合も、１枚の印刷配線板に対し
て、複数の電子部品を、印刷配線板に対して直接実装す
るようになっている。従って、このような構成におい
て、全体を小型化するためには、通常、次の４つの方法
が実施される。In either case, a plurality of electronic components are directly mounted on one printed wiring board. Therefore, in such a configuration, the following four methods are usually performed in order to reduce the size of the entire device.
【０００９】１．印刷配線板に実装される電子部品自体
を小型化する。1. The electronic component itself mounted on the printed wiring board is miniaturized.
【００１０】２．複数の電子部品をワンチップ化して印
刷配線板に実装される部品点数を削減する。2. Reduce the number of components mounted on a printed wiring board by integrating multiple electronic components into a single chip.
【００１１】３．印刷配線板に設けられる配線パターン
（電子部品実装ランド）を微細化して、配線密度を大き
くする。3. The wiring pattern (electronic component mounting land) provided on the printed wiring board is miniaturized to increase the wiring density.
【００１２】４．配線パターンが設けられる配線層を多
層化して、電子部品が占める面積（フットプリント）と
印刷配線板の面積との比を、できるだけ１に近似した値
とする。4. The wiring layer on which the wiring pattern is provided is multilayered, and the ratio of the area (footprint) occupied by the electronic component to the area of the printed wiring board is set to a value as close to 1 as possible.
【００１３】これら４つの方法のいずれかを実施するこ
とによって、印刷配線板に対して複数の電子部品を実装
する場合にも、全体を小型化することができる。By implementing any one of these four methods, it is possible to reduce the size of the whole even when a plurality of electronic components are mounted on the printed wiring board.
【００１４】これに対して、印刷配線板に対して複数の
電子部品を積層状態で実装することによって、全体を小
型化することが提案されている。図６および図７は、一
対の電子部品を積層状態で実装する構造の一例をそれぞ
れ示している。On the other hand, it has been proposed to reduce the size of the printed wiring board by mounting a plurality of electronic components in a stacked state. 6 and 7 each show an example of a structure for mounting a pair of electronic components in a stacked state.
【００１５】図６に示す電子部品の実装構造では、印刷
配線板６１上に、集積回路チップである第１のベアチッ
プ部品６２がダイレクトボンディングされており、この
第１のベアチップ部品６２上に、第２のベアチップ部品
６３がダイレクトボンディングされている。上下方向に
積層された第１のベアチップ部品６２および第２のベア
チップ部品６３は、印刷配線板６１上に設けられた各電
子部品実装用ランド６４と、それぞれ、金ワイヤー６５
によって電気的に接続されている。In the electronic component mounting structure shown in FIG. 6, the first bare chip component 62, which is an integrated circuit chip, is directly bonded onto the printed wiring board 61. The two bare chip parts 63 are directly bonded. The first bare chip component 62 and the second bare chip component 63, which are vertically stacked, each have an electronic component mounting land 64 provided on the printed wiring board 61, and a gold wire 65, respectively.
Are electrically connected by.
【００１６】図７に示す実装構造では、通常、ピギーバ
ックと称される第１の電子部品７２上に、第２の電子部
品７３が実装されている。第１の電子部品７２は、ＩＣ
パッケージの背面に、第２の電子部品７３を搭載するた
めのソケット７２ａが設けられている。このソケット７
２ａと、第２の電子部品７３の接続端子７３ａとが電気
的に接続される。In the mounting structure shown in FIG. 7, a second electronic component 73 is mounted on a first electronic component 72 which is usually called a piggyback. The first electronic component 72 is an IC
A socket 72a for mounting the second electronic component 73 is provided on the back surface of the package. This socket 7
2a and the connection terminal 73a of the second electronic component 73 are electrically connected.
【００１７】[0017]
【発明が解決しようとする課題】図６に示す実装構造で
は、第１および第２のベアチップ部品６２および６３同
士が、相互にダイレクトボンディングされるように、そ
れぞれのベアチップ部品６２および６３として、特殊な
形態のパッケージを使用する必要があるという問題があ
る。In the mounting structure shown in FIG. 6, the first and second bare chip components 62 and 63 are specially bonded to each other so that they are directly bonded to each other. There is a problem that it is necessary to use various types of packages.
【００１８】また、図７に示す電子部品の実装構造は、
各電子部品７２および７３の実装面積を削減する目的よ
りも、ＣＰＵとマスクＲＯＭ等のように、積層状態で実
装される一対の電子部品７２および７３それぞれの機能
等の相関に基づいて、各電子部品７２および７３を積層
状態で実装している。従って、この場合も、各電子部品
７２および７３は、特別な機能を有するとともに、相互
に接続されるような特殊な形態になっていることが必要
になる。Further, the mounting structure of the electronic component shown in FIG.
Rather than the purpose of reducing the mounting area of each electronic component 72 and 73, each electronic component 72 and 73 is mounted based on the correlation of the functions of each of the pair of electronic components 72 and 73 mounted in a stacked state, such as a CPU and a mask ROM. The components 72 and 73 are mounted in a stacked state. Therefore, also in this case, it is necessary that each electronic component 72 and 73 has a special function and has a special form that is connected to each other.
【００１９】このように、図６および図７に示す実装構
造は、通常の電子部品には適用されないために、一般的
な電子部品の配線密度を向上させるためには、通常、上
述した１〜４の方法が用いられている。しかし、上記１
〜４の方法でも、電子部品の小型化あるいは複数の電子
部品をワンチップ化することによって新たな電子部品を
開発する必要があり、また、配線パターンを微細化ある
いは多層化する必要があるために、容易に実現すること
ができず、しかも、費用および時間がかかるという問題
がある。As described above, since the mounting structure shown in FIGS. 6 and 7 is not applied to ordinary electronic parts, in order to improve the wiring density of general electronic parts, the above-mentioned 1 to 3 are usually used. 4 method is used. However, the above 1
Even in the methods of 4 to 4, it is necessary to develop a new electronic component by downsizing the electronic component or integrating a plurality of electronic components into one chip, and further, it is necessary to miniaturize or multi-layer the wiring pattern. However, there is a problem that it cannot be easily realized, and that it is expensive and time consuming.
【００２０】本発明は、このよう問題を解決するもので
あり、その目的は、配線板に複数の電子部品を容易に高
密度に実装することができ、しかも、電子部品を容易に
位置合わせすることができる電子部品の積層実装構造お
よびその電子部品の積層実装方法を提供することを目的
とする。The present invention solves such a problem, and an object thereof is to easily mount a plurality of electronic components on a wiring board at a high density and to align the electronic components easily. It is an object of the present invention to provide a laminated mounting structure of an electronic component and a laminated mounting method of the electronic component.
【００２１】[0021]
【課題を解決するための手段】本発明の電子部品の積層
実装構造は、それぞれが接続端子を有する一対の電子部
品が絶縁層を介して相互に積層されており、一方の電子
部品の接続端子に対応した絶縁層部分が選択的に除去さ
れて開口部が形成されるとともに、該開口部を介して、
各電子部品の接続端子同士が相互に電気的に接続されて
いることを特徴とするものであり、そのことにより上記
目的が達成される。According to the laminated mounting structure of an electronic component of the present invention, a pair of electronic components each having a connection terminal are laminated on each other via an insulating layer, and the connection terminal of one electronic component is connected. The insulating layer portion corresponding to is selectively removed to form an opening, and through the opening,
It is characterized in that the connection terminals of the electronic components are electrically connected to each other, whereby the above object is achieved.
【００２２】前記絶縁層は、前記各電子部品それぞれと
接している。The insulating layer is formed on each of the electronic components.
Touching .
【００２３】前記絶縁層に積層される一方の電子部品
は、接続端子に半田バンプが設けられている。One of the electronic components laminated on the insulating layer has solder bumps on the connection terminals.
【００２４】前記電子部品同士が、前記絶縁層の開口部
によって、相互に位置合わせされている。The electronic components are aligned with each other by the opening of the insulating layer.
【００２５】前記絶縁層が感光性樹脂によって構成され
ており、該感光性樹脂に対して光を照射して現像するこ
とによって前記開口部が形成されている。The insulating layer is made of a photosensitive resin, and the opening is formed by irradiating the photosensitive resin with light to develop it.
【００２６】前記絶縁層の開口部内および該開口部の周
縁部に、前記一方の電子部品の接続端子に電気的に接続
された導電体層が設けられている。A conductor layer electrically connected to the connection terminal of the one electronic component is provided in the opening of the insulating layer and in the peripheral portion of the opening.
【００２７】前記導電体層が、金属をメッキまたはスパ
ッタリングすることによって形成されている。The conductor layer is formed by plating or sputtering a metal.
【００２８】本発明の電子部品の積層実装方法は、接続
端子を有する電子部品を覆って絶縁層を形成する工程
と、該絶縁層にて覆われた電子部品の接続端子に対応す
る絶縁層部分を選択的に除去して該接続端子が露出する
開口部を形成する工程と、該絶縁層の上に、接続端子を
有する他の電子部品を積層して、該絶縁層の開口部に露
出する一方の電子部品の接続端子と該他の電子部品の接
続端子とを電気的に接続する工程と、を包含し、そのこ
とにより上記目的が達成される。The method of stacking and mounting electronic components according to the present invention comprises a step of forming an insulating layer covering an electronic component having a connecting terminal, and an insulating layer portion corresponding to the connecting terminal of the electronic component covered with the insulating layer. Selectively removing the opening to form an opening exposing the connection terminal, and stacking another electronic component having a connection terminal on the insulating layer to expose the opening in the insulating layer. The step of electrically connecting the connection terminal of one electronic component and the connection terminal of the other electronic component is included, whereby the above object is achieved.
【００２９】前記絶縁層に積層される一方の電子部品
は、接続端子に半田バンプが設けられており、該半田バ
ンプが前記絶縁層の開口部内に挿入されて該電子部品が
位置決めされる。The one electronic component laminated on the insulating layer has solder bumps provided on the connection terminals, and the electronic component is positioned by inserting the solder bump into the opening of the insulating layer.
【００３０】前記絶縁層および開口部は、感光性樹脂に
対して光を選択的に照射して現像することにより形成さ
れる。The insulating layer and the opening are formed by selectively irradiating the photosensitive resin with light and developing it.
【００３１】前記絶縁層の開口部内および該開口部の周
縁部に、前記一方の電子部品の接続端子に電気的に接続
された導電体層を形成する工程をさらに含む。The method further includes the step of forming a conductor layer electrically connected to the connection terminal of the one electronic component in the opening of the insulating layer and in the peripheral portion of the opening.
【００３２】以下に、本発明の作用について説明する。The operation of the present invention will be described below.
【００３３】本発明にあっては、複数の電子部品を積み
重ねて配線板に実装する際に、電子部品間に絶縁層を設
けて、電子部品の接続端子上の絶縁層を選択的に除去し
て開口部を形成して、絶縁層の開口部において電子部品
同士を電気的に接続することができる。従って、通常の
電子部品であっても、積層状態で実装することができる
ために、配線板上に複数の電子部品を高密度に実装する
ことができる。According to the present invention, when a plurality of electronic components are stacked and mounted on a wiring board, an insulating layer is provided between the electronic components to selectively remove the insulating layer on the connection terminals of the electronic components. The electronic parts can be electrically connected to each other in the opening of the insulating layer by forming the opening. Therefore, even ordinary electronic components can be mounted in a laminated state, so that a plurality of electronic components can be mounted on the wiring board at high density.
【００３４】絶縁層は、電子部品同士を接続するための
接続層としても用いることができる。また、絶縁層の開
口部によって、上側の電子部品を配置する際の位置決め
を行うこともできる。The insulating layer can also be used as a connection layer for connecting electronic components to each other. In addition, the opening of the insulating layer can be used to position the upper electronic component.
【００３５】絶縁層として感光性樹脂を用いることによ
り、光照射および現像によって容易に開口部を形成する
ことができる。また、メッキまたはスパッタリング等の
メタライズ処理によって、絶縁層が開口部内および開口
部の周縁部に、電子部品の接続端子に電気的に接続され
た導電体層を形成することにより、他の電子部品との電
気的な接続を、さらに容易にできる。By using a photosensitive resin as the insulating layer, the opening can be easily formed by light irradiation and development. In addition, by forming a conductor layer electrically connected to the connection terminal of the electronic component in the insulating layer in the opening and in the peripheral portion of the opening by a metallizing treatment such as plating or sputtering, it is possible to form another electronic component. The electrical connection can be made easier.
【００３６】[0036]
【発明の実施の形態】以下に、本発明の実施の形態につ
いて、図面に基づいて説明する。BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings.
【００３７】（実施形態１）図１は、本発明の一実施形
態である電子部品の積層実装構造の一例を示す断面図で
ある。この積層構造では、表面に部品実装用ランド１１
ａがエッチング等によってパターニングされた印刷配線
板１１が実装用支持板として使用されており、この印刷
配線板１１の部品実装用ランド１１ａ上に、ＢＧＡ（Ｂ
ａｌｌ Ｇｒｉｄ Ａｒｒａｙ）パッケージの集積回路
である第１電子部品１３が実装される。このＢＧＡパッ
ケージの集積回路である第１電子部品は、その下面に設
けられた複数の接続端子（図示せず）に半田バンプ１４
がそれぞれ設けられており、各半田バンプ１４が、印刷
配線板１１に設けられた各部品実装用ランド１１ａに、
それぞれ、電気的に接続されている。(Embodiment 1) FIG. 1 is a sectional view showing an example of a stacked mounting structure of an electronic component according to an embodiment of the present invention. In this laminated structure, the component mounting land 11 is formed on the surface.
The printed wiring board 11 in which a is patterned by etching or the like is used as a mounting support plate, and the BGA (B
The first electronic component 13, which is an integrated circuit of an all grid array) package, is mounted. The first electronic component, which is an integrated circuit of this BGA package, has solder bumps 14 on a plurality of connection terminals (not shown) provided on the lower surface thereof.
And the solder bumps 14 are provided on the component mounting lands 11a provided on the printed wiring board 11, respectively.
Each is electrically connected.
【００３８】第１電子部品１３上には、絶縁層としての
感光性樹脂１２が積層されている。感光性樹脂１２に
は、第１電子部品１３の表面から露出する接続端子１３
ａに対応する部分がそれぞれ選択的に除去されて開口部
１２ａがそれぞれ形成されている。感光性樹脂１２に形
成された各開口部１２ａからは、第１電子部品１３の各
接続端子１３ａがそれぞれ露出している。A photosensitive resin 12 as an insulating layer is laminated on the first electronic component 13. The photosensitive resin 12 has a connection terminal 13 exposed from the surface of the first electronic component 13.
Portions corresponding to a are selectively removed to form openings 12a. Each connection terminal 13a of the first electronic component 13 is exposed from each opening 12a formed in the photosensitive resin 12.
【００３９】感光性樹脂１２上には、ＢＧＡパッケージ
の集積回路である第２電子部品１５が積層されている。
この第２電子部品１５も、その下面に設けられた複数の
接続端子（図示せず）に半田バンプ１６がそれぞれ設け
られており、第２電子部品１５の各半田バンプ１６が、
感光性樹脂１２の各開口部１２ａ内にそれぞれ挿入され
て、第１電子部品１３と位置決めされた状態で、第１電
子部品の各接続ランド１３ａにそれぞれ電気的に接続さ
れている。A second electronic component 15 which is an integrated circuit of a BGA package is laminated on the photosensitive resin 12.
This second electronic component 15 is also provided with solder bumps 16 on a plurality of connection terminals (not shown) provided on the lower surface thereof, and each solder bump 16 of the second electronic component 15 is
The photosensitive resin 12 is inserted into the openings 12a of the photosensitive resin 12, respectively, and is electrically connected to the connection lands 13a of the first electronic component 13 while being positioned with respect to the first electronic component 13.
【００４０】この場合、第１電子部品１３および第２電
子部品１５は、感光性樹脂１２にそれぞれ接した状態に
なっている。In this case, the first electronic component 13 and the second electronic component 15 are in contact with the photosensitive resin 12, respectively.
【００４１】なお、本実施形態では、印刷配線板１１と
して、多層配線板を使用しているが、図１では、上面に
設けられる配線パターンである部品接続用ランド１１ａ
のみを示しており、内部に設けられる多数の内層配線パ
ターン、裏面に設けられる配線パターン等については、
特に図示していない。また、印刷配線板１１としては、
このような多層配線板に限らず、表面にのみ配線パター
ンである部品接続用ランド１１ａが設けられたものであ
ってもよく、さらに、印刷配線板１１に代えて、樹脂
板、コア金属板等も実装用支持板として使用することが
できる。In this embodiment, a multilayer wiring board is used as the printed wiring board 11, but in FIG. 1, a component connecting land 11a which is a wiring pattern provided on the upper surface.
Only a large number of inner layer wiring patterns provided inside, wiring patterns provided on the back side, etc.
Not specifically shown. Further, as the printed wiring board 11,
Not limited to such a multilayer wiring board, a component connection land 11a that is a wiring pattern may be provided only on the surface, and instead of the printed wiring board 11, a resin plate, a core metal plate, or the like. Can also be used as a mounting support plate.
【００４２】第１電子部品１３は、上面に接続端子１３
ａが設けられるとともに下面に半田バンプ１４が設けら
れたＢＧＡパッケージの集積回路に限らず、他の電子部
品であってもよい。第２電子部品１５も、同様に、ＢＧ
Ａパッケージの集積回路に限らず、他の電子部品であっ
てもよい。The first electronic component 13 has a connection terminal 13 on the upper surface.
The electronic circuit is not limited to the integrated circuit of the BGA package in which a is provided and the solder bumps 14 are provided on the lower surface, and other electronic components may be used. Similarly, the second electronic component 15 also has a BG
The electronic circuit is not limited to the integrated circuit of the A package and may be other electronic components.
【００４３】このような電子部品の実装構造を得るため
の本発明の実装方法について、図２（ａ）〜（ｃ）に基
づいて説明する。なお、図２（ａ）〜（ｃ）でも、説明
を簡単にするために、多層配線板である印刷配線板１１
の内層配線パターン、裏面の配線パターン等は、図示を
省略している。A mounting method of the present invention for obtaining such a mounting structure for electronic parts will be described with reference to FIGS. 2 (a) to 2 (c). 2A to 2C as well, the printed wiring board 11 which is a multilayer wiring board is used to simplify the description.
The inner layer wiring pattern, the wiring pattern on the back surface, etc. are not shown.
【００４４】図２（ａ）に示すように、表面に部品実装
用ランド１１ａが設けられた印刷配線板１１を準備し
て、その印刷配線板１１の各部品実装用ランド１１ａ上
に、ＢＧＡパッケージの集積回路である第１電子部品１
３を搭載する。この場合、第１電子部品１３の下面に設
けられた各半田バンプ１４が、印刷配線板１１の各部品
実装用ランド１１ａと、それぞれ電気的に接続される。As shown in FIG. 2A, a printed wiring board 11 having component mounting lands 11a on its surface is prepared, and a BGA package is mounted on each component mounting land 11a of the printed wiring board 11. First electronic component 1 which is an integrated circuit of
It is equipped with 3. In this case, the solder bumps 14 provided on the lower surface of the first electronic component 13 are electrically connected to the component mounting lands 11a of the printed wiring board 11, respectively.
【００４５】第１電子部品１３を印刷配線板１１に搭載
した後に、この第１電子部品１３の上面に、絶縁層とな
る感光性樹脂１２を塗布する。この感光性樹脂１２は、
電気的絶縁性能を有しており、本実施形態では、ポジ型
の感光性エポキシ樹脂を用いている。このポジ型感光性
エポキシ樹脂は、最初は液体状であるが、光の照射によ
って光重合を起こして硬化する。感光性樹脂１２として
は、このようなポジ型に限らず、ネガ型の感光性樹脂、
感光性ポリイミド等を用いることができ、一対の電子部
品間に設けられる際に必要とされる機械強度、電気特性
等に応じて、最適なものが、適宜選択される。After mounting the first electronic component 13 on the printed wiring board 11, a photosensitive resin 12 serving as an insulating layer is applied to the upper surface of the first electronic component 13. This photosensitive resin 12 is
It has electrical insulation performance, and in this embodiment, a positive photosensitive epoxy resin is used. Although this positive photosensitive epoxy resin is initially in a liquid state, it undergoes photopolymerization upon irradiation with light to be cured. The photosensitive resin 12 is not limited to such a positive type, but a negative type photosensitive resin,
A photosensitive polyimide or the like can be used, and the most suitable one is appropriately selected according to the mechanical strength, electrical characteristics, etc. required when it is provided between a pair of electronic components.
【００４６】感光性樹脂１２は、第１電子部品１３の表
面に露出する各接続端子１３ａを覆うように、第１電子
部品１３の上面全体にわたって設けられる。The photosensitive resin 12 is provided over the entire upper surface of the first electronic component 13 so as to cover the connection terminals 13a exposed on the surface of the first electronic component 13.
【００４７】次に、図２（ｂ）に示すように、感光性樹
脂１２を覆うように、フォトマスク１７を配置して、光
重合プロセスにより、第１電子部品１３上に塗布した感
光性樹脂１２を硬化させる。フォトマスク１７は、通常
の写真フィルムと同様のものが使用され、光が透過する
透明部分１７ａと、光を遮光する遮光部分１７ｂとがそ
れぞれ所定の位置に設けられている。Next, as shown in FIG. 2B, a photomask 17 is arranged so as to cover the photosensitive resin 12, and the photosensitive resin applied on the first electronic component 13 by a photopolymerization process. Cure 12 As the photomask 17, the same one as a normal photographic film is used, and a transparent portion 17a that transmits light and a light shielding portion 17b that shields light are provided at predetermined positions.
【００４８】この場合、フォトマスク１７は、第１電子
部品１３の表面に露出した各接続端子１３ａが設けられ
ている部分１３ａに対応して、光を遮光する遮光部分１
７ａがそれぞれ設けられており、各透明部分１７ｂが、
第１電子部品１３の表面における各接続端子１３ａが設
けられていない部分１３ｂに対応して、それぞれ位置す
るように、フォトマスク１７を感光性樹脂１２上に配置
する。そして、フォトマスク１７の全体にわたって光を
照射する。これにより、フォトマスク１７の透明部分１
７ｂでは、光が透過して、各透明部分１７ｂの下方の感
光性樹脂部分１２ｂがそれぞれ硬化し、絶縁層が形成さ
れる。これに対して、フォトマスク１７の遮光部分１７
ａでは、光が透過しないために、各遮光部分１７ａの下
方の感光性樹脂部分１２ｃは硬化しない。In this case, the photomask 17 corresponds to the portion 13a where the connection terminals 13a exposed on the surface of the first electronic component 13 are provided, and the light shielding portion 1 for shielding light.
7a are provided, and each transparent portion 17b is
The photomask 17 is arranged on the photosensitive resin 12 so as to be located corresponding to the portions 13b on the surface of the first electronic component 13 where the connection terminals 13a are not provided. Then, the entire photomask 17 is irradiated with light. As a result, the transparent portion 1 of the photomask 17
In 7b, the light is transmitted, and the photosensitive resin portions 12b below the respective transparent portions 17b are cured respectively to form an insulating layer. On the other hand, the light-shielding portion 17 of the photomask 17
In a, since light does not pass therethrough, the photosensitive resin portion 12c below each light shielding portion 17a is not cured.
【００４９】このようにして、フォトマスク１７を介し
て感光性樹脂１２に十分な光量を与えて、感光性樹脂１
２を硬化させた後、適切な溶剤を用いて感光性樹脂１２
を現像すると、図２（ｃ）に示すように、露光時に使用
したフォトマスク１７の透明部１７ａと遮光部１７ｂの
パターンによって、第１電子部品１３の表面に設けられ
た接続端子１３ａ上に位置する感光性樹脂部分１２ｃの
みが選択的に除去される。これにより、感光性樹脂１２
には、第１電子部品１３の各接続端子１３ａに対応した
開口部１２ａが形成され、各開口部１２ａから各接続端
子１３ａが露出した状態になる。In this way, a sufficient amount of light is applied to the photosensitive resin 12 through the photomask 17, and the photosensitive resin 1
After curing 2, the photosensitive resin 12 using a suitable solvent
2C, it is positioned on the connection terminal 13a provided on the surface of the first electronic component 13 by the pattern of the transparent portion 17a and the light shielding portion 17b of the photomask 17 used at the time of exposure, as shown in FIG. 2C. Only the photosensitive resin portion 12c that is to be removed is selectively removed. Thereby, the photosensitive resin 12
The openings 12a corresponding to the respective connection terminals 13a of the first electronic component 13 are formed in the opening, and the respective connection terminals 13a are exposed from the respective openings 12a.
【００５０】なお、本実施形態では、絶縁層として感光
性樹脂１２を使用して、感光性樹脂を選択的に除去する
ために、光重合プロセスを利用する構成であったが、こ
のような構成に限定されるものではなく、例えば、絶縁
層として通常の絶縁性樹脂を用いて、レーザー光の照
射、物理的なドリル加工等によって、接続端子１３ａ上
の絶縁性樹脂部分を選択的に除去するようにしてもよ
い。In this embodiment, the photosensitive resin 12 is used as the insulating layer, and the photopolymerization process is used to selectively remove the photosensitive resin. However, the insulating resin portion on the connection terminal 13a is selectively removed by irradiation with laser light, physical drilling, or the like, using an ordinary insulating resin as the insulating layer. You may do it.
【００５１】絶縁層である感光性樹脂１２に開口部１２
ａが形成されると、図１に示すように、下面に設けられ
た複数の接続ランド（図示せず）に対応して半田バンプ
１６がそれぞれ設けられたＢＧＡパッケージの集積回路
である第２電子部品１５が、絶縁層である感光性樹脂１
２上に搭載される。この場合、第２電子部品１５の各半
田バンプ１６が、感光性樹脂１２の各開口部１２ａ内に
それぞれ挿入されることによって、第２電子部品１５
は、第１電子部品１３に対して位置決めされる。そし
て、位置決めされた第２電子部品１５に対して、熱また
は圧力を加えて、第１電子部品１３の接続端子１３ａに
第２電子部品１５の各半田バンプ１６を、それぞれ電気
的に接続させる。これにより、第２電子部品１５は、絶
縁層である感光性樹脂１２を介して第１分子部品１３上
に実装される。The opening 12 is formed in the photosensitive resin 12 which is an insulating layer.
When a is formed, as shown in FIG. 1, a second electron which is an integrated circuit of a BGA package in which solder bumps 16 are respectively provided corresponding to a plurality of connection lands (not shown) provided on the lower surface. The photosensitive resin 1 in which the component 15 is an insulating layer
It is mounted on 2. In this case, the solder bumps 16 of the second electronic component 15 are inserted into the openings 12 a of the photosensitive resin 12, respectively, so that the second electronic component 15 is
Are positioned with respect to the first electronic component 13. Then, heat or pressure is applied to the positioned second electronic component 15 to electrically connect the solder bumps 16 of the second electronic component 15 to the connection terminals 13 a of the first electronic component 13. As a result, the second electronic component 15 is mounted on the first molecular component 13 via the photosensitive resin 12 that is an insulating layer.
【００５２】このように、感光性樹脂１２に形成された
開口部１２ａ内に、実装される第２電子部品１５の凸形
状の各半田バンプ１６をそれぞれ挿入して、第２電子部
品１５を第１電子部品１３に対して位置決めすることが
でき、第２電子部品１５をセルフアライメントによって
感光性樹脂１２上に実装することができる。As described above, the convex solder bumps 16 of the second electronic component 15 to be mounted are respectively inserted into the openings 12a formed in the photosensitive resin 12 to form the second electronic component 15 into the first electronic component 15. It can be positioned with respect to the first electronic component 13, and the second electronic component 15 can be mounted on the photosensitive resin 12 by self-alignment.
【００５３】図３（ａ）〜（ｄ）は、それぞれ、本発明
の電子部品の実装方法における他の例の各工程をそれぞ
れ示す断面図である。図１に示す電子部品の実装構造で
は、絶縁層である感光性樹脂１２を、第１電子部品１３
上にのみ形成したが、本実施形態では、第１電子部品１
３全体を覆うように、印刷配線板１１上に設けるように
なっている。その他の基本的な構成は、図１に示す電子
部品と実装構造と同様になっている。FIGS. 3A to 3D are cross-sectional views showing respective steps of another example of the electronic component mounting method of the present invention. In the mounting structure of the electronic component shown in FIG. 1, the photosensitive resin 12, which is an insulating layer, is replaced by the first electronic component 13
Although formed only on the top, in the present embodiment, the first electronic component 1
It is provided on the printed wiring board 11 so as to cover the whole 3. Other basic configurations are similar to those of the electronic component and mounting structure shown in FIG.
【００５４】すなわち、図３（ａ）に示すように、表面
に部品実装用ランド１１ａが設けられた印刷配線板１１
を準備して、その印刷配線板１１の各部品実装用ランド
１１ａ上に、ＢＧＡパッケージの集積回路である第１電
子部品１３を搭載する。第１電子部品１３の下面に設け
られた各半田バンプ１４は、印刷配線板１１の各部品実
装用ランド１１ａと、それぞれ電気的に接続される。そ
の後、第１電子部品１３が搭載された印刷配線板１１上
に、この第１電子部品１３全体を覆うように、印刷配線
板１１の上面に、絶縁層となる感光性樹脂１２を塗布す
る。That is, as shown in FIG. 3A, the printed wiring board 11 having the component mounting lands 11a on its surface is provided.
Is prepared, and the first electronic component 13, which is an integrated circuit of the BGA package, is mounted on each component mounting land 11a of the printed wiring board 11. The solder bumps 14 provided on the lower surface of the first electronic component 13 are electrically connected to the component mounting lands 11a of the printed wiring board 11, respectively. Then, on the printed wiring board 11 on which the first electronic component 13 is mounted, the photosensitive resin 12 serving as an insulating layer is applied to the upper surface of the printed wiring board 11 so as to cover the entire first electronic component 13.
【００５５】次に、第１電子部品１３に対応した感光性
樹脂１２上に、フォトマスク１７を配置して、光重合プ
ロセスにより、第１電子部品１３の表面に露出した接続
端子１３ａ上に位置する感光性樹脂部分１２ｃのみを選
択的に除去して、感光性樹脂１２に、第１電子部品１３
の各接続端子１３ａに対応した開口部１２ａを形成す
る。Next, a photomask 17 is arranged on the photosensitive resin 12 corresponding to the first electronic component 13 and is positioned on the connection terminal 13a exposed on the surface of the first electronic component 13 by a photopolymerization process. Selectively removing only the photosensitive resin portion 12c, the photosensitive resin 12 is covered with the first electronic component 13c.
The opening 12a corresponding to each connection terminal 13a is formed.
【００５６】このような状態になると、図３（ｂ）に示
すように、絶縁層である感光性樹脂１２の上面全体およ
び感光性樹脂１２の各開口部１２ａ内に、メッキ、スパ
ッタリング等によって、金属層１８を形成する。金属層
１８は、各開口部１２ａ内に露出した第１電子部品１３
の各接続端子１３ａとはそれぞれ電気的に接続される。In such a state, as shown in FIG. 3B, the entire upper surface of the photosensitive resin 12 which is an insulating layer and each opening 12a of the photosensitive resin 12 are plated, sputtered or the like. The metal layer 18 is formed. The metal layer 18 has the first electronic component 13 exposed in each opening 12a.
Are electrically connected to the respective connection terminals 13a.
【００５７】次に、通常のエッチングレジスト形成およ
びエッチング工程により、図３（ｃ）に示すように、第
１電子部品１３の各接続端子１３ａ上、感光性樹脂１２
の開口部１２ａの内周面およびそれに連なる開口部１２
ａの周縁部における感光性樹脂１２の表面に、金属層１
８が残るようにメタライズして、接続部１８ａをそれぞ
れ形成する。Next, as shown in FIG. 3C, the photosensitive resin 12 is formed on each connection terminal 13a of the first electronic component 13 by the usual etching resist forming and etching steps.
Inner peripheral surface of the opening 12a of the base plate and the opening 12 continuous with the inner peripheral surface
On the surface of the photosensitive resin 12 in the peripheral portion of a, the metal layer 1
Metallization is performed so that 8 remains, and the connection portions 18a are formed.
【００５８】なお、接続部１８ａは、感光性樹脂１２の
開口部１２ａにおける内周面のみならず、感光性樹脂１
２の表面における開口部１２ａの周縁部にも、ビアラン
ドとして設けられており、開口部１２ａの欠損等が防止
されているが、このような構成に限らず、配線密度を向
上させるために、感光性樹脂１２の表面における開口部
１２ａの周縁部には、金属層１８を残すことなく、接続
部１８ａを、開口部１２ａの内周面および底面を覆うよ
うに設けるようにしてもよい。The connecting portion 18a is not limited to the inner peripheral surface of the opening 12a of the photosensitive resin 12 but also the photosensitive resin 1
The peripheral portion of the opening 12a on the surface of 2 is also provided as a via land to prevent the opening 12a from being damaged. However, the structure is not limited to such a configuration, and the wiring density is increased to improve the wiring density. At the peripheral edge of the opening 12a on the surface of the resin 12, the connecting portion 18a may be provided so as to cover the inner peripheral surface and the bottom surface of the opening 12a without leaving the metal layer 18.
【００５９】その後、図３（ｄ）に示すように、第２電
子部品１５を絶縁層である感光性樹脂１２上に搭載す
る。この場合、第２電子部品１５に設けられた各半田バ
ンプ１６が、感光性樹脂１２に設けられた各接続部１８
ａにそれぞれ接するように、第２電子部品１５が配置さ
れて、第２電子部品に熱および圧力を加えることによっ
て、各半田バンプ１６を、各接続部１８ａに対して、そ
れぞれ電気的に接続する。After that, as shown in FIG. 3D, the second electronic component 15 is mounted on the photosensitive resin 12 which is an insulating layer. In this case, the solder bumps 16 provided on the second electronic component 15 are connected to the connection portions 18 provided on the photosensitive resin 12.
The second electronic component 15 is arranged so as to be in contact with each a, and each solder bump 16 is electrically connected to each connection portion 18a by applying heat and pressure to the second electronic component. .
【００６０】このように、絶縁層である感光性樹脂１２
の各開口部１２ａの内周面から感光性樹脂１２の表面に
わたって、第１電子部品１３の各接続端子１３ａに接続
された接続部１８ａがそれぞれ形成されていることによ
り、第２電子部品１５の半田バンプ１６を各接続部１８
ａに対して容易に接続することができ、しかも、第２電
子部品１５の各半田バンプ１６と第１電子部品１３の各
接続端子との電気的な接続の信頼性も向上する。As described above, the photosensitive resin 12 as the insulating layer
Since the connection portions 18a connected to the connection terminals 13a of the first electronic component 13 are formed from the inner peripheral surface of each opening 12a to the surface of the photosensitive resin 12, the second electronic component 15 of Connect the solder bumps 16 to the connection parts 18
It can be easily connected to a, and the reliability of electrical connection between each solder bump 16 of the second electronic component 15 and each connection terminal of the first electronic component 13 is also improved.
【００６１】さらには、各接続部１８ａは、第１電子部
品１３にそれぞれ直接接した状態になっているために、
第１電子部品１３を効果的に放熱することができる。Further, since each connecting portion 18a is in direct contact with the first electronic component 13,
The first electronic component 13 can be effectively dissipated.
【００６２】なお、各接続部１８ａを設ける際に、同様
の手順によって、第１電子部品１３に広い面積にわたっ
て接する金属層を設けるようにしてもよい。これによ
り、放熱板、ヒートスプレッダー等を別に設けることな
く、第１電子部品１３を金属層によって放熱することが
できる。しかも、この場合の金属層は、放熱板、ヒート
スプレッダー等を設ける場合に比べて、放熱効果に優れ
ている。Incidentally, when the respective connecting portions 18a are provided, a metal layer which is in contact with the first electronic component 13 over a wide area may be provided by the same procedure. Accordingly, the first electronic component 13 can be radiated by the metal layer without separately providing a heat radiating plate, a heat spreader, or the like. In addition, the metal layer in this case is superior in heat dissipation effect as compared with the case where a heat dissipation plate, a heat spreader, etc. are provided.
【００６３】図４は、本発明の電子部品の積層実装構造
のさらに他の例を示す断面図である。この電子部品の積
層実装構造では、両面に接続端子が設けられたＢＧＡパ
ッケージの集積回路である第１電子部品２３が、印刷配
線板２１上に実装されるとともに、両側部に接続端子３
２ａがそれぞれ設けられた通常のチップ部品である第２
電子部品３２が印刷配線板２１上に実装されている。FIG. 4 is a sectional view showing still another example of the laminated mounting structure of the electronic component of the present invention. In this laminated mounting structure of electronic components, the first electronic component 23, which is an integrated circuit of a BGA package having connection terminals provided on both surfaces, is mounted on the printed wiring board 21 and the connection terminals 3 are provided on both sides.
2a which is a normal chip component provided with 2a respectively
The electronic component 32 is mounted on the printed wiring board 21.
【００６４】第１電子部品２３は、実施形態１と同様
に、印刷配線板２１の部品実装用ランド２１ａ上に、第
１電子部品２３に設けられた各半田バンプ２４が電気的
に接続されて、印刷配線板２１上に実装されている。ま
た、第２電子部品３２は、印刷配線板２１上の他の部品
実装用ランド２１ａ上に、各側部の接続端子３２ａが位
置するように配置されて、部品実装用ランド２１ａと各
接続端子３２ａとがそれぞれ半田３１によって、電気的
に接続されている。In the first electronic component 23, as in the first embodiment, the solder bumps 24 provided in the first electronic component 23 are electrically connected to the component mounting lands 21a of the printed wiring board 21. , Mounted on the printed wiring board 21. The second electronic component 32 is arranged so that the connection terminals 32a on each side are located on the other component mounting lands 21a on the printed wiring board 21, and the component mounting lands 21a and each connection terminal are arranged. 32a are electrically connected to each other by solder 31.
【００６５】印刷配線板２１上には、第１電子部品２３
および第２電子部品３２を覆うように、絶縁層２２が設
けられている。絶縁層２２には、第１電子部品２３の上
面に設けられた接続端子（図示せず）、第２電子部品３
２の接続端子３２ａ、および、印刷配線板２１の上面に
設けられたバイアホールランド２１ｂにそれぞれ対応す
る部分がそれぞれ選択的に除去されて開口部２２ａがそ
れぞれ形成されている。The first electronic component 23 is provided on the printed wiring board 21.
The insulating layer 22 is provided so as to cover the second electronic component 32. The insulating layer 22 has a connection terminal (not shown) provided on the upper surface of the first electronic component 23 and a second electronic component 3
Portions corresponding to the two connection terminals 32a and the via hole lands 21b provided on the upper surface of the printed wiring board 21 are selectively removed to form openings 22a.
【００６６】絶縁層２２の各開口部２２ａの内部には、
第１電子部品２３の接続端子、第２電子部品３２の各接
続端子３２ａ、バイアホールランド２１ｂにそれぞれ電
気的に接続された導電性の接続部３５が、それぞれ設け
られており、絶縁層２２の表面には、各接続部３５にそ
れぞれ連続する積層実装用ランド３６およびバイアホー
ルランド３７がそれぞ形成されている。そして、第１電
子部品２３の接続端子に接続された積層実装用ランド３
６の上面と、第２電子部品３２の一方の接続端子３２ａ
接続された積層実装用ランド３６の上面との間にわたっ
て、第３電子部品３３が実装されており、また、第２電
子部品３２の一方の接続端子３２ａ接続された積層実装
用ランド３６の上面と、バイアホールランド２１ｂに接
続されたバイアホールランド３７の上面との間にわたっ
て、第４電子部品３４が実装されている。Inside each opening 22a of the insulating layer 22,
Conductive connection portions 35 electrically connected to the connection terminals of the first electronic component 23, the connection terminals 32a of the second electronic component 32, and the via hole lands 21b are respectively provided, and the insulating layers 22 of the insulating layer 22 are provided. Stacked mounting lands 36 and via hole lands 37 that are continuous with the respective connection portions 35 are formed on the surface. The stacked mounting land 3 connected to the connection terminal of the first electronic component 23
6 and one connection terminal 32a of the second electronic component 32
The third electronic component 33 is mounted between the upper surface of the connected laminated mounting land 36 and the upper surface of the laminated mounting land 36 connected to one of the connection terminals 32a of the second electronic component 32. The fourth electronic component 34 is mounted over the upper surface of the via hole land 37 connected to the via hole land 21b.
【００６７】第３電子部品３３は、各側部に接続端子３
３ａがそれぞれ設けられており、各接続端子３３ａと、
各積層実装用ランド３６の上面とが、それぞれ半田３８
によって電気的に接続されている。同様に、第４電子部
品３４も、各側部に接続端子３４ａがそれぞれ設けられ
ており、各接続端子３４ａと、各積層実装用ランド３６
の上面とが、それぞれ半田３８によって電気的に接続さ
れている。The third electronic component 33 has a connecting terminal 3 on each side.
3a are provided respectively, and each connection terminal 33a,
The upper surface of each laminated mounting land 36 is connected to the solder 38.
Are electrically connected by. Similarly, the fourth electronic component 34 is also provided with the connection terminals 34 a on each side, and each connection terminal 34 a and each stacked mounting land 36.
Are electrically connected to the upper surface of each of them by solder 38.
【００６８】また、絶縁層２２上に設けられた一対の積
層実装用ランド３６の上面間にわたって設けられた第３
電子部品３３と、絶縁層２２との間には、適当な空間が
形成されており、その空間内における絶縁層２２の表面
に、配線パターン３９が設けられている。Further, the third layer provided between the upper surfaces of the pair of stacked mounting lands 36 provided on the insulating layer 22.
An appropriate space is formed between the electronic component 33 and the insulating layer 22, and the wiring pattern 39 is provided on the surface of the insulating layer 22 in the space.
【００６９】図４に示す電子部品の実装構造では、表面
に接続端子が設けられたＢＧＡパーケージの集積回路で
ある第１電子部品２３とともに、通常の半導体チップで
ある第２〜第４電子部品３２〜３４を用いており、ＢＧ
Ａパーケージの集積回路である第１電子部品２３に対し
て、通常の半導体チップである第３電子部品が積層状態
で実装されるとともに、それぞれが通常の半導体チップ
である第２電子部品３２および第４電子部品３４同士が
積層状態で実装されている。In the mounting structure of the electronic component shown in FIG. 4, together with the first electronic component 23 which is an integrated circuit of the BGA package having the connection terminals provided on the surface, the second to fourth electronic components 32 which are ordinary semiconductor chips are provided. ~ 34 is used, BG
The third electronic component, which is a normal semiconductor chip, is mounted in a stacked state on the first electronic component 23, which is an integrated circuit of A package, and the second electronic component 32 and the second electronic component 32, which are normal semiconductor chips, respectively. The four electronic components 34 are mounted in a stacked state.
【００７０】また、印刷配線板２１上に設けられた絶縁
層２２上における第３電子部品３３の実装位置に形成さ
れる空間を利用して配線パターン３９を設けることがで
きるために、さらに配線密度を向上させることができ
る。Further, since the wiring pattern 39 can be provided by utilizing the space formed at the mounting position of the third electronic component 33 on the insulating layer 22 provided on the printed wiring board 21, the wiring density is further increased. Can be improved.
【００７１】[0071]
【発明の効果】本発明の電子部品の積層実装構造および
実装方法は、このように、特殊な形態のパッケージを用
いることなく、通常の電子部品を用いて、複数の電子部
品を積層実装することができるために、実装構造を小型
化することができる。また、電子部品を積層実装する際
に、絶縁層が選択的に除去されて形成された開口部を利
用して、電子部品同士の位置決めが可能となり、実装に
際しての作業効率を向上させることができるとともに、
電子部品同士の電気的な接続の安定性を向上させること
ができる。As described above, according to the laminated mounting structure and mounting method of the electronic component of the present invention, a plurality of electronic components are laminated and mounted by using the ordinary electronic component without using the package of the special form. Therefore, the mounting structure can be downsized. In addition, when the electronic components are stacked and mounted, the openings formed by selectively removing the insulating layer can be used to position the electronic components with each other, and the work efficiency in mounting can be improved. With
The stability of electrical connection between electronic components can be improved.
【図１】本発明の電子部品の積層実装構造の一例を示す
断面図である。FIG. 1 is a cross-sectional view showing an example of a stacked mounting structure of an electronic component of the present invention.
【図２】（ａ）〜（ｃ）は、それぞれ、その電子部品の
積層実装構造を得るための本発明の積層実装方法におけ
る各工程を示す断面図である。FIGS. 2A to 2C are cross-sectional views showing respective steps in a stacked mounting method of the present invention for obtaining a stacked mounting structure of the electronic component.
【図３】（ａ）〜（ｄ）は、それぞれ、本発明の積層実
装方法の他の例における各工程を示す断面図である。3A to 3D are cross-sectional views showing respective steps in another example of the stacked mounting method of the present invention.
【図４】本発明の電子部品の積層実装構造のさらに他の
例を示す断面図である。FIG. 4 is a sectional view showing still another example of the stacked mounting structure of the electronic component of the present invention.
【図５】従来の電子部品の積層実装構造の一例を示す断
面図である。FIG. 5 is a cross-sectional view showing an example of a conventional stacked mounting structure of electronic components.
【図６】従来の電子部品の積層実装構造の他の例を示す
断面図である。FIG. 6 is a cross-sectional view showing another example of a conventional stacked mounting structure of electronic components.
【図７】従来の電子部品の積層実装構造のさらに他の例
を示す断面図である。FIG. 7 is a cross-sectional view showing still another example of a conventional stacked mounting structure of electronic components.
１１ 印刷配線板 １１ ａ部品実装用ランド １２ 感光性樹脂 １２ａ 開口部 １３ 第１電子部品 １３ａ 接続端子 １４ 半田バンプ １６ 半田バンプ １７ フォトマスク １７ａ 透明部 １７ｂ 遮光部 １８ 金属層 １８ａ 接続部 ２１ 印刷配線板 ２１ ａ部品実装用ランド ２１ｂ バイアホールランド ２２ 絶縁層 ２２ａ 開口部 ２３ 第１電子部品 ２４ 半田バンプ ３２ 第２電子部品 ３３ 第３電子部品 ３４ 第４電子部品 ３５ 接続部 ３６ 積層実装用ランド ３７ バイアホールランド ３８ 半田 ３９ 配線パターン 11 Printed wiring board 11a Parts mounting land 12 Photosensitive resin 12a opening 13 First electronic components 13a connection terminal 14 Solder bump 16 Solder bump 17 Photomask 17a transparent part 17b Light-shielding part 18 metal layers 18a connection part 21 Printed wiring board 21 a Land for component mounting 21b Bahia Holeland 22 Insulation layer 22a opening 23 First electronic component 24 Solder bump 32 Second electronic component 33 Third electronic component 34 Fourth Electronic Component 35 Connection 36 Stacking land 37 Bahia Holeland 38 Solder 39 Wiring pattern
Claims (11)
部品が絶縁層を介して相互に積層されており、一方の電
子部品の接続端子に対応した絶縁層部分が選択的に除去
されて開口部が形成されるとともに、該開口部を介し
て、各電子部品の接続端子同士が相互に電気的に接続さ
れていることを特徴とする電子部品の積層実装構造。1. A pair of electronic components each having a connection terminal are laminated on each other with an insulating layer interposed therebetween, and an insulating layer portion corresponding to the connection terminal of one electronic component is selectively removed to form an opening. And the connection terminals of the electronic components are electrically connected to each other through the opening.
と接している請求項１に記載の電子部品の積層実装構
造。2. The stacked mounting structure for electronic components according to claim 1, wherein the insulating layer is in contact with each of the electronic components.
は、接続端子に半田バンプが設けられている請求項１に
記載の電子部品の積層実装構造。3. The stacked mounting structure for an electronic component according to claim 1, wherein one of the electronic components stacked on the insulating layer has a solder bump on a connection terminal.
部によって、相互に位置合わせされている請求項１に記
載の電子部品の積層実装構造。4. The stacked mounting structure for electronic components according to claim 1, wherein the electronic components are aligned with each other by the openings of the insulating layer.
れており、該感光性樹脂に対して光を照射して現像する
ことによって前記開口部が形成されている請求項１に記
載の電子部品の積層実装構造。5. The electronic component according to claim 1, wherein the insulating layer is made of a photosensitive resin, and the opening is formed by irradiating the photosensitive resin with light to develop it. Stacked mounting structure.
周縁部に、前記一方の電子部品の接続端子に電気的に接
続された導電体層が設けられている請求項１に記載の電
子部品の積層実装構造。6. The electron according to claim 1, wherein a conductor layer electrically connected to a connection terminal of the one electronic component is provided in the opening of the insulating layer and in a peripheral portion of the opening. Stacked mounting structure of parts.
パッタリングすることによって形成されている請求項５
に記載の電子部品の積層実装構造。7. The conductor layer is formed by plating or sputtering a metal.
The laminated mounting structure of the electronic component described in.
層を形成する工程と、 該絶縁層にて覆われた電子部品の接続端子に対応する絶
縁層部分を選択的に除去して該接続端子が露出する開口
部を形成する工程と、 該絶縁層の上に、接続端子を有する他の電子部品を積層
して、該絶縁層の開口部に露出する一方の電子部品の接
続端子と該他の電子部品の接続端子とを電気的に接続す
る工程と、を包含する電子部品の積層実装方法。8. A step of forming an insulating layer covering an electronic component having a connection terminal, and an insulating layer portion corresponding to the connection terminal of the electronic component covered with the insulating layer is selectively removed to form the connection. A step of forming an opening through which the terminal is exposed; another electronic component having a connecting terminal is laminated on the insulating layer, and the connecting terminal of one electronic component exposed in the opening of the insulating layer and the connecting terminal And a step of electrically connecting to a connection terminal of another electronic component.
は、接続端子に半田バンプが設けられており、該半田バ
ンプが前記絶縁層の開口部内に挿入されて該電子部品が
位置決めされる請求項８に記載の電子部品の積層実装方
法。9. The electronic component on one side of the insulating layer is provided with a solder bump on a connection terminal, and the solder bump is inserted into the opening of the insulating layer to position the electronic component. The stacked mounting method for an electronic component according to claim 8.
脂に対して光を選択的に照射して現像することにより形
成される請求項８に記載の電子部品の積層実装方法。10. The method of stacking electronic components according to claim 8, wherein the insulating layer and the opening are formed by selectively irradiating a photosensitive resin with light and developing the photosensitive resin.
の周縁部に、前記一方の電子部品の接続端子に電気的に
接続された導電体層を形成する工程をさらに含む請求項
８に記載の電子部品の積層実装方法。11. The method according to claim 8, further comprising forming a conductor layer electrically connected to a connection terminal of the one electronic component in the opening of the insulating layer and in a peripheral portion of the opening. Stacked mounting method for electronic components.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2001326852A JP2003133683A (en) | 2001-10-24 | 2001-10-24 | Stack mounting structure of electronic parts and method for stack mounting electronic parts |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2001326852A JP2003133683A (en) | 2001-10-24 | 2001-10-24 | Stack mounting structure of electronic parts and method for stack mounting electronic parts |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JP2003133683A true JP2003133683A (en) | 2003-05-09 |
Family
ID=19143163
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2001326852A Pending JP2003133683A (en) | 2001-10-24 | 2001-10-24 | Stack mounting structure of electronic parts and method for stack mounting electronic parts |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2003133683A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2005294724A (en) * | 2004-04-05 | 2005-10-20 | Sony Corp | Semiconductor device and method for manufacturing the same |
| KR100609334B1 (en) | 2005-06-13 | 2006-08-08 | 삼성전자주식회사 | Stack circuit member gap-filled photo sensitive polymer and method for manufacturing thereof |
-
2001
- 2001-10-24 JP JP2001326852A patent/JP2003133683A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2005294724A (en) * | 2004-04-05 | 2005-10-20 | Sony Corp | Semiconductor device and method for manufacturing the same |
| JP4496825B2 (en) * | 2004-04-05 | 2010-07-07 | ソニー株式会社 | Semiconductor device and manufacturing method thereof |
| KR100609334B1 (en) | 2005-06-13 | 2006-08-08 | 삼성전자주식회사 | Stack circuit member gap-filled photo sensitive polymer and method for manufacturing thereof |
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