JP2003131895A - Built-in memory device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve the reliability of a device by suppressing the garbling of data due to soft error generated in volatile memory while maintaining the high speed of memory access and without increasing the processing load on a microcomputer. SOLUTION: In the device, a program transferring circuit 4 is provided, operation is started in the program transferring circuit 4 by starting of a timer 3 or a device load measuring circuit 42, and an actually moving program in an involatile memory 5 is transferred to volatile memory by periodically breaking up an area.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention incorporates a microcomputer, a non-volatile memory, and a volatile memory, and a program for operating the microcomputer is stored in the non-volatile memory.
The present invention relates to a built-in memory device in which a microcomputer reads a program in a volatile memory and operates after the program stored in the nonvolatile memory is copied to the volatile memory.

[0002]

2. Description of the Related Art In a device such as a communication control device which has a built-in microcomputer and which is required to have high performance, a circuit which operates on a volatile memory capable of accessing the memory at high speed is often incorporated. However, in the volatile memory, data conversion due to a soft error may occur. Therefore, there is a method in which a device that actually operates on a volatile memory incorporates a 1-bit correction circuit for memory data by ECC to suppress malfunction of the device and improve reliability.

Further, in Japanese Patent Laid-Open No. 2000-132461, a program copy routine is executed in every cycle so that even if a garbled bit occurs in the normal processing routine, a correct value is overwritten again to prevent a memory error. is there.

[0004]

In the 1-bit correction of memory data by ECC, since it is necessary to finish the detection / correction of the memory within one access, it is possible to detect the garbled bit even if the garbled bit has not occurred. Therefore, there is a problem that one access time to the memory becomes long and the performance of the device for accessing the memory is deteriorated. Also,
There is a problem in that the cost of the device is increased by incorporating the ECC circuit into actual hardware.

Further, the technique for preventing the memory error by the above program copy routine does not consider the size of the program or the capability of the MPU.

The present invention is a circuit for maintaining the high speed of memory access, suppressing the data corruption due to the soft error generated in the volatile memory and increasing the reliability of the device without increasing the processing load of the microcomputer. To provide.

[0007]

[Means for Solving the Problems] The above-described object is to copy a program stored in a non-volatile memory for operating a microcomputer to a volatile memory, and transfer the program to the volatile memory so that the microcomputer executes the program. After the operation is started, a means for periodically copying the program in the non-volatile memory to the same area in the volatile memory and a program for periodically copying the program in the non-volatile memory to the volatile memory are provided. This is achieved by having means for dividing the amount and copying the entire program within a fixed period, and means for recognizing the load of the apparatus and copying the program in the non-volatile memory to the volatile memory when the load is low.

[0008]

BEST MODE FOR CARRYING OUT THE INVENTION An embodiment of the present invention will be described below with reference to the drawings.

The block diagram shown in FIG. 4 shows the configuration of one communication control unit 26. The communication control device 26 comprises an MPU 2, a non-volatile memory 5, a volatile memory 6, and an internal bus 7. The nonvolatile memory 5 is a program PRG-A8, PRG-B9, PRG- for operating the MPU shown in FIG.
C10, PRG-D11, PRG-E12, PRG-F
13 in which PRG-A8 and PRG-B9 are in area A14, and PRG-C10 and PR are respectively.
G-D11 is in area B15, PRG-E12 and PRG
-It is assumed that F13 is assigned to the area C16. FIG. 3 shows a memory layout diagram for copying a program for operating the microprocessor in the non-volatile memory to a volatile memory, and PRG-A'17 has PRG-A'17.
A8 and PRG-B'18 have PRG-B9 and PRG-
PRG-C10 for C'19 and P for PRG-D'20
For RG-D11 and PRG-E'21, PRG-E12,
PRG-F13 is copied to PRG-F'22.
First, as shown in the time chart shown in FIG. 5, the communication control apparatus operates in the area A1 of the actual operation program in the nonvolatile memory 5 in response to an instruction from the MPU 2 when the power is turned on.
4, area B15 and area C16 are copied to the areas A'23, B'24 and C'25 on the volatile memory 6 shown in FIG. 3, and the MPU copies the program on the volatile memory 6. Read and execute the program. After that, the actual operation is PR as shown in the time chart of FIG.
G-A'17, PRG-C'19, PRG-B'18 to P
It will be continued with RG-D'20. Here, it is assumed that garbled data occurs due to a soft error in the PRG-B'18 area at the timing shown in FIG. After that, MPU
When PRG-B'18 is read by 2 and actually operates, the communication control device 26 malfunctions due to garbled data due to a soft error and becomes abnormal.

FIG. 1 is a block diagram of a memory built-in device 1 according to an embodiment of the present invention.

The device 1 with a built-in memory comprises an MPU 2, a timer 3, a program transfer circuit 4, a non-volatile memory 5, a volatile memory 6 and an internal bus 7. The non-volatile memory 5 is a program PR for operating the MPU shown in FIG.
G-A8, PRG-B9, PRG-C10, PRG-D
It consists of 11, PRG-E12, PRG-F13,
FIG. 3 is a memory layout diagram for copying a program for operating the microprocessor in the non-volatile memory to a volatile memory. PRG-A'17 has a PRG-A'17.
-A8 and PRG-B'18 have PRG-B9 and PRG-
PRG-C10 for C'19 and P for PRG-D'20
For RG-D11 and PRG-E'21, PRG-E12,
PRG-F13 is copied to PRG-F'22.
First, as shown in the time chart of FIG. 6, the memory-incorporated device 1 displays the area A14, the area B15, and the area C16 of the actual operation program in the nonvolatile memory 5 in FIG. 3 according to an instruction from the MPU 2 when the power is turned on. The data is transferred to the areas A'23, B'24, and C'25 on the volatile memory 6 shown, and the actual operation is started on the volatile memory 6. Thereafter, the actual operation is performed at the time shown in FIG. As shown in the chart, PRG-A'17, PRG-C'19, PRG
-B'18 to PRG-D'20 will continue.
Next, the MPU 2 activates the timer 3. The program transfer circuit 4 starts its operation when the timer 3 is activated when the time is up. The operation of the program transfer circuit 4 will be described below with reference to the flow chart of the program transfer circuit of FIG. In the program transfer circuit 4, in the management table 34 shown in FIG. 8, the program start address 35 in the non-volatile memory, the program end address 36 in the non-volatile memory, the program start address 37 in the volatile memory, the transfer source address 38, the transfer destination address 39, The transfer size 40 is managed. In the management table 34, when the power is turned on, the MPU 2 sets the memory addresses A, B, C and the memory size S shown in FIG. In step 27, first, the data in the area indicated by the transfer source address 38 is transferred to the area indicated by the transfer destination address 39, then in step 28 the transfer source address 38 and the transfer destination address 39 are updated, and the updated transfer source address In step 29, it is determined whether 39 is greater than or equal to the value indicated by the non-volatile memory end address 36, and step 2
If the judgment of 9 is Yes, the transfer source address is 3 in step 30.
The program start address 35 in the non-volatile memory is set to 8 and the program start address 35 in the volatile memory is set to the transfer destination address 39 in step 31. Whether the transfer for the transfer size S40 area has been completed is step 3
If the determination in step 2 is No, and the determination in step 32 is No, the processing from step 27 is repeated, and the determination in step 32 is Yes.
If s, the timer 3 is started in step 33 and the process is terminated. In the subsequent operation, the timer 3 times out, and the program transfer circuit repeats the processing after activation. Here, at the timing shown in FIG. 6, the PRG-B'18 on the volatile memory 6 is
It is assumed that data is corrupted due to a soft error in the area. Before the MPU 2 reads the PRG-B'18 and starts the actual operation, the timer 3 times up, the program transfer circuit 4 is activated, and the program transfer circuit 4 operates to perform PR.
If the area A'including GB'18 is copied from the area A14 of the non-volatile memory 5 to the area A'of the volatile memory 6, the garbled data due to the soft error is corrected and the malfunction can be suppressed.

Next, another embodiment will be described. Data to be transferred per cycle based on the program start address in the non-volatile memory and the program end address in the non-volatile memory by the MPU 2 when the device with built-in memory 1 is turned on so that the entire program area can be divided and transferred within a fixed time. And the transfer size 40 of the management table 34 shown in FIG. 8 is set. After that, a program for operating the MPU 2 in the non-volatile memory 5 is divided into the volatile memory 6 by performing the operation of the memory-embedded device 1 according to the first embodiment, and copying is performed, thereby causing a soft error. This can be achieved by correcting the area where the data is garbled. The time at which an error occurs and the time for writing can be appropriately determined based on the reliability to be achieved. Also, the settings in the management table 34 are appropriately determined. As an example, the following formula can be established and the calculation can be performed based on it.

E> t1 = (B−A) / S * t2 Equation (1) e: Time when soft error occurs A: Program start address in nonvolatile memory B: Program end address in nonvolatile memory t1: All Time to complete transfer of program area t2: Cycle in which the program transfer circuit can be started without increasing the processing load of the device (time when timer expires) S: Program size to be copied in one transfer processing operation An example will be described.

FIG. 10 is a block diagram of a memory built-in device according to a third embodiment of the present invention. The same components as those in FIG. 1 are designated by the same reference numerals and the description thereof will be omitted. In this device, a device load measuring circuit 42 shown in FIG. 10 is provided in place of the timer 3 provided in the memory built-in device 1 according to the first embodiment.
The device load measurement circuit 42 measures the load of the MPU 2 and
The program transfer circuit 4 is activated when U2 has a low load.
After that, the operation of the program transfer circuit shown in FIG. 7 is carried out, but the timer in step 33 is not started. In this way, the program transfer circuit 4 operates when the device has a low load, and the program for operating the MPU 2 in the non-volatile memory 5 is copied to the volatile memory 6 so that data garbling due to a soft error occurs in the area. Can be achieved by modifying

FIG. 11 is a diagram showing the load on the microprocessor during actual operation. A microprocessor executes a program related to the business processing in order to perform the business processing that the computer originally wants to process. This means that it is actually operating, and is also referred to as online processing because the processing result is output to and controlled by another device for business processing. The bar graphs represented by the slanted lines in the figure represent the programs related to this online processing that are calculated by the microprocessor. When the load factor exceeds 100%, the processing of the microprocessor does not end in that cycle, which affects the actual operation. The writing process to the memory is performed in the margin portion up to the load factor of 100%.

When the online processing of (a) is constant, the margin up to a load factor of 100% is constant. Take the time t1 at which you want to complete the transfer of all program areas as shown in the figure, which is the total of vertical bar graphs representing programs that can be processed with a margin Program size to be transferred BA, the processing cycle of the microprocessor (actual operation Time t that does not affect
2 is set), the size S of the program that can be processed with a margin can be obtained from the equation (1).

(B) shows a case where the online processing is periodically changed. Take the time t1 at which you want to complete the transfer of all program areas as shown in the figure, and do not exceed the program size B-A you want to transfer, which is the total of the bar graph of the vertical line representing the program that can be processed with a margin, and process the device. Allocate so that the program transfer circuit can be started without increasing the load. When the time t1 at which the transfer is desired to be completed is larger than the periodic cycle which is periodically fluctuating, the periodic cycle can be set as one unit and assigned to a plurality of units.

Even when the online processing is not periodic,
Divide by setting the upper limit of the load factor within the range that does not exceed the time t1 that you want to complete the transfer of the program size B-A that you want to transfer, which is the total of the vertical bar graph that represents the programs that can be processed It can be handled by calculating the amount.

[0019]

As described above, according to the present invention, it is possible to suppress data corruption due to a soft error occurring in a volatile memory without increasing the processing load of the microcomputer while maintaining the high speed of memory access. It is possible to improve the reliability of the device.

[Brief description of drawings]

FIG. 1 is a block configuration diagram showing an outline of an internal configuration of a device with a built-in memory according to the present invention.

FIG. 2 is a memory layout diagram of a non-volatile memory included in the device illustrated in FIGS. 1, 4, and 10;

FIG. 3 is a memory layout diagram of a volatile memory included in the device illustrated in FIGS. 1, 4, and 10;

FIG. 4 is a block configuration diagram showing an outline of an internal configuration of a communication control device shown as an example.

FIG. 5 is an operation time chart of the communication control device shown as an example.

FIG. 6 is an operation time chart diagram of the device with a built-in memory according to the present invention.

FIG. 7 is a flowchart of a program transfer circuit included in the device shown in FIGS. 1 and 10.

FIG. 8 is a management table managed by a program transfer circuit included in the apparatus shown in FIGS.

9 is a memory diagram showing values set in the management table shown in FIG.

FIG. 10 is a block diagram showing an outline of an internal configuration of a device with a built-in memory according to the present invention.

FIG. 11 is a diagram showing a load on the microprocessor during actual operation.

[Explanation of symbols]

1 ... Device with built-in memory according to claim 1, 2 ... MPU (microcomputer processing unit), 3 ... Timer, 4 ... Program transfer circuit, 5 ... Non-volatile memory, 6
... Volatile memory, 7 ... Internal bus, 8 ... Actual operation program PRG-A, 9 ... Actual operation program PRG-B, 10 ...
Actual operation program PRG-C, 11 ... Actual operation program PRG-D, 12 ... Actual operation program PRG-E, 13
... actual operation program PRG-F, 14 ... area A, 15
Area B, 16 ... Area C, 17 ... Actual operation program PRG-A ', 18 ... Actual operation program PRG-B',
19 ... Actual operation program PRG-C ', 20 ... Actual operation program PRG-D', 21 ... Actual operation program PRG
-E ', 22 ... Actual operation program PRG-F', 23 ...
Area A ', 24 ... Area B', 25 ... Area C ', 2
6 ... Example of communication control device, 27 ... Step 1 of program transfer circuit, 28 ... Step 2 of program transfer circuit,
29 ... Program transfer circuit step 3, 30 ... Program transfer circuit step 4, 31 ... Program transfer circuit step 5, 32 ... Program transfer circuit step 6, 33 ... Program transfer circuit step 7, 34 ... Program transfer circuit Management table, 35 ... Non-volatile memory program start address, 36 ... Non-volatile memory program end address, 37 ... Volatile memory program start address, 38 ... Transfer source address, 39 ... Transfer destination address, 40 ... Transfer size , 41 ... Device with built-in memory according to claim 3, 42 ... Device load measuring circuit.

   ─────────────────────────────────────────────────── ─── Continued front page    (72) Inventor Hideaki Masuko             5-2-1 Omika-cho, Hitachi City, Ibaraki Prefecture             Information Control Systems Division, Hitachi, Ltd.             Within (72) Inventor Nao Ogawa             5-2-1 Omika-cho, Hitachi City, Ibaraki Prefecture             Information Control Systems Division, Hitachi, Ltd.             Within (72) Inventor Yoshimi Fujimata             5-2-1 Omika-cho, Hitachi City, Ibaraki Prefecture             Inside the Hitachi Information Control System (72) Inventor Junichi Sekimura             5-2-1 Omika-cho, Hitachi City, Ibaraki Prefecture             Inside the Hitachi Information Control System F term (reference) 5B018 GA04 HA40 MA23 NA01 QA04                       RA04                 5B076 BA04

Claims (6)

[Claims] 1. A memory built-in device having a microprocessor, a non-volatile memory, and a volatile memory inside the device, and a program for operating the microprocessor is stored in the non-volatile memory. Has a means for periodically writing the program in the non-volatile memory to the volatile memory after starting an actual operation for executing the program in the volatile memory without affecting the actual operation. A device with a built-in memory. 2. A device with a built-in memory, which has a microprocessor, a non-volatile memory, and a volatile memory inside the device, and stores a program for operating the microprocessor in the non-volatile memory. A device with a built-in memory, comprising means for dividing a program in a memory and writing the divided program in the volatile memory. 3. A device with a built-in memory, which has a microprocessor, a non-volatile memory and a volatile memory inside the device, and a program for operating the microprocessor is stored in the non-volatile memory. Means for dividing the program in the memory and writing the divided program in the volatile memory; means for recognizing the total amount of the program in the non-volatile memory; and the division based on the recognized total amount of the program. And a means for calculating the data amount of the program to be executed. 4. A memory built-in device having a microprocessor, a non-volatile memory, and a volatile memory inside the device, and a program for operating the microprocessor being stored in the non-volatile memory. And a means for recognizing the load of the microprocessor, and a means for copying the program by dividing the program into the volatile memory when the microprocessor has a low load. 5. The program transfer, wherein the microprocessor starts the actual operation of executing the program in the non-volatile memory copied in the volatile memory, and transfers the program in the non-volatile memory to the volatile memory. A method for suppressing an error in a device with a built-in memory, wherein after the start of the actual operation, the circuit periodically writes the program in the non-volatile memory to the volatile memory without affecting the actual operation. 6. The program transfer, wherein the microprocessor starts an actual operation of executing a program in the nonvolatile memory copied in the volatile memory, and transfers the program in the nonvolatile memory to the volatile memory. A circuit divides a program in the non-volatile memory, and writes the divided program in the volatile memory.