JP2003131873A - Microcomputer - Google Patents

Abstract

PROBLEM TO BE SOLVED: To suppress growth in logic size such as an instruction decode circuit in a microcomputer in which a DSP engine is mounted on a single LSI together with a CPU core. SOLUTION: This microcomputer is constituted with a CPU (2), a memory unit which access is trolled by the CPU, a data bus to transfer between the above memory unit and the above CPU, and a DSP (3) connected to the above data bus. The CPU has a CPU instruction of 16 bit fixed length, an instruction register (25) to fetch a DSP instruction of 16 bit or 32 bit length for the DSP, and a decoder (24) to generate the first control signal (247) to identify the CPU instruction or the DSP instruction based on a part of the instruction fetched by the above instruction register and control behavior of the CPU in accordance with an outcome of identification, and the second control signal (20) to control the behavior of the DSP. The DSP includes a decoder (34) to decode the second control signal received from the CPU.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a logic LSI formed into a semiconductor integrated circuit having a central processing unit and a digital signal processing unit, and relates to a technique effective when applied to a microcomputer requiring high-speed arithmetic processing.

[0002]

2. Description of the Related Art Japanese Patent Application No. 4-296778 or U.S. Pat. App. No. 145157 is an example of a microcomputer in which a multiplier and an arithmetic logic unit are mounted on the same chip. According to this, a logic LSI chip such as a microcomputer is provided with a central processing unit, a bus, a memory and a multiplier, and in particular, while reading data from the memory, a command of a multiplication instruction regarding the read data is multiplied from the central processing unit. It has a command signal line for transferring to a container. As a result, while the central processing unit reads the data from the memory, the command of the multiply instruction regarding the read data is transferred from the central processing unit to the multiplier, so that the data can be directly transferred between the memory and the multiplier. become.

[0003]

DISCLOSURE OF THE INVENTION The present inventors have examined how to speed up digital signal processing by mounting a digital signal processing unit together with a central processing unit in one LSI. At this time, the above-mentioned conventional technique realizes high-speed multiplication processing in that data can be directly transferred from the memory to the multiplier. However, when pipeline processing of instruction execution by the central processing unit is assumed, No consideration was given to the situation where the fetch cycle of the instruction to be executed by the processing unit and the memory access cycle for the multiplication process compete with each other. Further, no consideration is given to the fact that a plurality of operands for addition and multiplication are read out from the memory in parallel to speed up the arithmetic processing. Further, in that case, it has been found that the usability of the microcomputer is deteriorated unless the relationship with the external access by the central processing unit is taken into consideration. Further, when the digital signal processing unit is mounted on one LSI together with the central processing unit, the code allocation between the CPU instruction and the DSP instruction and the format of the DSP instruction can be devised to increase the logical scale of the instruction decoding circuit as much as possible. It has been found necessary to suppress it.

An object of the present invention is to mount a digital signal processing unit together with a central processing unit in one LSI to speed up digital signal processing. Another object of the present invention is to suppress an increase in the physical scale of a digital processing unit mounted on one LSI together with a central processing unit as much as possible.

The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0006]

The outline of the representative one of the inventions disclosed in the present application will be briefly described as follows.

That is, the microcomputer includes a central processing unit (2) and first to third address buses (IAB, YAB, X) to which addresses are selectively transmitted from the central processing unit.
AB), the first address bus (IAB) and the second address bus (IAB)
To the first memory (5, 7) connected to the address bus (YAB) of the central processing unit and accessed by the address from the central processing unit, and to the first address bus (IAB) and the third address bus (XAB). A second memory (4, 6) connected and accessed by an address from the central processing unit,
A first data bus (IDB) connected to the first and second memories and the central processing unit for transmitting data, and a second data bus connected to the first memory for transmitting data. Data bus (YDB),
A third connected to the second memory to transfer data
Data bus (XDB), an external interface circuit (12) connected to the first address bus and the first data bus, and first to third data buses, which are synchronously operated by the central processing unit. A semiconductor integrated circuit including a digital signal processing unit (3) for controlling the operation of the digital signal processing unit and a control signal line for transmitting a DSP control signal (20) for controlling the operation of the digital signal processing unit from the central processing unit to the digital signal processing unit in one chip. It is made into a circuit.

According to the above means, the built-in memory has the first memory (5, 7) and the second memory (4) in consideration of the sum of products operation by the digital signal processor (3).
6), the central processing unit (2) connects the first memory and the second memory to the third bus (X
AB, XDB) and the second bus (YAB, YDB) are accessible in parallel. As a result, two pieces of data can be transferred simultaneously from the built-in memory to the digital signal processing unit. Furthermore, the third bus (XAB, XDB) and the second bus (YAB, YD)
B) is a first bus (IA) interfaced to the outside.
(B, IDB) are also individualized, the central processing unit is the second memory (4, 6) and the first memory unit.
External memory access is enabled in parallel with the access to the memory (5, 7). As described above, the first to third types of address buses (IAB, XAB, YA) connected to the central processing unit (2) respectively.
B) and the data buses (IDB, XDB, YDB), it is possible to execute different memory access operations in the same clock cycle using the three types of internal buses. Therefore, even when a program or data exists in the external memory, it is possible to easily cope with the speedup of the arithmetic processing.

In order to improve the usability of the microcomputer, the first memory and the second memory are each read as R.
It is preferable to be composed of AM and ROM.

In order to speed up address generation for repetitive operations such as multiply-add operations in the central processing unit, the central processing unit may include a modulo address output section (200). At this time, it is desirable that the address generated by the modulo address output unit can be selectively output to the second or third address bus.

The digital signal processor includes first to third data buffer means (MDBI, MDBY, MDBX) individually interfaced with the first to third data buses (IDB, YDB, XDB), A plurality of register means (305 to 308) connectable to the respective data buffer means via an internal bus; a multiplier (304) and an arithmetic logic unit (302) connected to the internal bus; A decoder (34) for decoding the DSP control signal to control the operations of the data buffer means, the multiplier, the arithmetic and logic unit, and the register means can be configured.

Focusing on the point of instruction decoding, the microcomputer includes a central processing unit (2), memories (4 to 7) whose access is controlled by the central processing unit, the memory and the central processing unit. Digital signal processing unit (3) in which data is transmitted between the two and synchronized with the central processing unit
And are included in one chip to be a semiconductor integrated circuit. The instruction set that can be executed by this microcomputer is
A CPU instruction to be executed by the central processing unit (2) and a DSP instruction to be executed by the digital signal processing unit (3) by causing the central processing unit to bear a part of processing such as address calculation for data fetching. Including. The central processing unit includes a 16-bit fixed-length CPU instruction and a 16-bit or 32-bit DSP, via the data bus.
An instruction register (25) for fetching an instruction and a CPU instruction and a DSP instruction on the basis of a plurality of bits of a part of the instruction fetched in the instruction register, and the digital signal processing according to the identification result. It may include a DSP control signal (20) for controlling the operation of the unit and a decoder (24) for generating a CPU control signal for controlling the operation of the central processing unit.

For example, the CPU instruction is assigned to a range in which the most significant 4 bits of the instruction code are "0000" to "1110". The DSP instruction is assigned to a range in which the most significant 4 bits of the instruction code are "1111". Furthermore, the most significant 6 bits of the instruction code are "111".
The instruction assigned to the range of "100" and "111101" is a 16-bit instruction code even in the DSP instruction. The most significant 6 bits of the instruction code are "11111".
The instruction of “0” is an instruction code of 32 bit length. The instruction is not assigned to the range where the most significant 6 bits of the instruction code is “111111”, and the range is set as an unused area. , By providing the above rule for code allocation for a maximum of 32 bits, if a part of each instruction code, for example, the 6 most significant bits, is decoded, it is determined whether the instruction is a CPU instruction or a 16-bit length. D
It is possible to determine whether the instruction is an SP instruction or a DSP instruction having a 32-bit length with a small logic scale decoder.
It is not always necessary to decode all 32 bits at once.

The decoder is composed of the upper 16 bits of the instruction register.
Bits are decoded and the CPU decode signal (24
3) and a first to generate a DSP decode signal (244)
When the 32-bit length DSP instruction is identified by the first decode circuit and the decode circuit (240), the signal that codes the lower 16 bits of the instruction register is invalid, and when the other instruction is identified, the output is invalid. And a code conversion circuit (242) for outputting a code meaning that there is an output, and the output of the DSP decode signal and the code conversion circuit is a DSP control signal (20).

Focusing on the instruction format of the DSP instruction, the microcomputer includes a central processing unit (2), a digital signal processing unit (3) operated in synchronization with the central processing unit, the central processing unit, and A semiconductor integrated circuit including an internal bus (IDB) to which the digital signal processing unit is commonly connected,
The central processing unit defines a first code area (bit 9 to bit 0 of the 16-bit DSP instruction illustrated in FIG. 18) that defines a data transfer with the digital signal processing unit for the central processing unit. And a second code area (A field of the 32-bit DSP instruction illustrated in FIGS. 20 and 21) having the same format as the first code area.
Has a third code area (B field of the 32-bit DSP instruction illustrated in FIGS. 20 and 21) that specifies, for the digital signal processing unit, the arithmetic processing using the transfer data defined in the code area of FIG. And an execution control means for executing the second format instruction.

As a result, the execution control means employs a decoding means having a common decoding logic for the first code area and the second code area when executing the respective instructions of the first and second formats. This contributes to the reduction of the logic scale of the microcomputer.

The first format instruction and the second format instruction include a fourth code area (for example, bit 15 to bit 10, 32 in a 16-bit DSP instruction) for indicating whether it is the first format or the second format.
Bit 32 to bit 26) in the DSP instruction.

The execution control means includes an instruction register (25) commonly used for the first format instruction and the second format instruction, and the first code area included in the instruction fetched in the instruction register. And a fourth code area or a decoding means (240) for decoding the second code area and the fourth code area, and an execution means for performing an address operation according to the decoding result and performing the data transfer control. can do.

The instruction register includes an upper area (UIR) shared for holding the first code area and the fourth code area or the second code area and the fourth code area, and the third code area. Lower area (LI
R) and the decoding means outputs a control signal (248) indicating that the instruction register holds an instruction of the second format based on the decoding result of the fourth code area, and A means (24) for supplying code data in the third code area from the lower area to the digital signal processing unit based on a control signal.
2, 242A, 242B).

[0020]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 shows an overall block diagram of a microcomputer 1 according to an embodiment of the present invention. The microcomputer shown in the figure is formed on one semiconductor substrate such as single crystal silicon by a semiconductor integrated circuit manufacturing technique. Microcomputer 1
Is a CPU as a central processing unit
Core (CPU Core) 2, DSP engine (DSP Engine) 3 as a digital signal processing unit, X-ROM 4,
Y-ROM 5, X-RAM 6, Y-RAM 7, interrupt controller (Interrupt Controller) 8, bus state controller (Bus State Controller) 9, built-in peripheral circuits (Peripheral Circuit) 10, 11, external memory interface (External Memory Interface) 12 ,
It is composed of a clock pulse generator (CPG) 13. The X-ROM 4 and the Y-ROM 5 are read-only or electrically rewritable read-only memories for storing instructions or constant data.
-RAM6 and Y-RAM7 are temporary storage of data or C
It is a random access memory used as a work area for the PU core 2 and the DSP engine 3. X-
The ROM 4 and the X-RAM 6 are collectively referred to as an internal instruction / data X memory (Internal Instrument / Data X Mem.),
The Y-ROM 5 and the Y-RAM 7 are collectively referred to as an internal instruction / data Y memory (Internal Instrument / Data Y Mem.).

The microcomputer 1 of this embodiment has, as its bus configuration, an internal address bus IAB and an internal data bus ID coupled to the external memory interface 12.
B, internal address bus XAB and internal data bus XDB not coupled to external memory interface 12, internal address bus YAB and internal data bus YDB not coupled to external memory interface 12, and peripheral address bus PAB for internal peripheral circuits 10 and 11. And a peripheral data bus PDB. Although not shown in the drawing, the control bus is provided corresponding to each pair of the address bus and the data bus.

A data bus IDB connectable to the outside of the chip is connected to the CPU core 2 through an external memory interface 12, and an interrupt signal 80 from an interrupt controller 8 is given to it. The CPU core 2 supplies the DSP engine 3 with a control signal 20 for controlling the DSP engine 3. Further, the CPU core 2 outputs an address signal to the address bus IAB connectable to the outside of the chip through the external memory interface 12 and the address buses XAB and YAB not connected to the external memory interface 12. The CPU core 2 outputs the non-overlap two-phase clock signals Clock1 and Clock2 output from the clock pulse generator (CPG) 13.
Is used as the operation reference clock signal. The CPU core 2 will be described in detail later, but the CPU core 2 in FIG. 1 includes a register file 21 and an arithmetic logic unit (AL).
U) 22, address adder (Add-ALU) 23, decoder 24, and instruction register (IR) 25 are representatively shown. The register file 21 is arbitrarily used as an address register and a data register, and includes a program counter, a control register, and the like. The decoder 24 decodes the instruction fetched in the instruction register 25 and generates an internal control signal (not shown in FIG. 1) and a control signal 20. The instruction register (IR) 25 is
Each consists of a 16-bit upper side area (UIR) and a lower side area (LIR). Although details will be described later, the value of the lower side area (LIR) is selectively set to the upper side area (UI).
R) can be shifted. A sequence control circuit for controlling the instruction execution procedure when an exception such as an interrupt occurs and for controlling the saving / restoring of the internal state in response to the exception by hardware is not shown.

The DSP engine 3 uses the data bus ID
Clock signal Cloc connected to B, XDB, and YDB
It is operated by using k1 and Clock2 as operation reference clock signals. The details of the DSP engine 3 will be described later, but the DSP engine 3 of FIG.
r) 32, multiplier (MAC) 33, and decoder 34 are typically shown. Data register file 31
Is used for multiply-accumulate operations. The decoder 34 decodes the control signal 20 provided from the CPU core 2 and
An internal control signal (not shown in FIG. 1) of the engine 3 is generated.

The X-ROM 4 and the X-RAM 6 are connected to the address buses IAB, XAB and the data buses IDB, XDB. The Y-ROM 5 and the Y-RAM 7 are connected to the address buses IAB, YAB and the data buses IDB, YDB. The built-in memory is divided into X memories 4 and 6 and Y memories 5 and 7 in consideration of multiply-accumulate operation by the DSP engine 3, and is made accessible in parallel by internal buses XAB, XDB and YAB, YDB. ing. Further, since the internal buses XAB, XDB and YAB, YDB are also individualized with the buses IAB, IDB which are interfaced to the outside, the external memory access is also performed in parallel with the access of the X memories 4, 6 and the Y memories 5, 7. Enabled X
The memories 4 and 6 and the Y memories 5 and 7 are used as a data temporary storage area for the product-sum calculation by the DSP engine 3 and a storage area for constant data. In addition, X-RAM, Y
It goes without saying that the RAM can also be used as a temporary data storage area or work area of the CPU core 2.

The interrupt controller 8 receives an interrupt request signal (Interrup) from the internal peripheral circuits 10 and 11, etc.
ts) 81, arbitrates and accepts interrupt requests according to information for prioritizing various interrupt requests and masking the interrupt requests, and sends an interrupt vector (Interrupt Vector) 82 corresponding to the accepted interrupt request to the address bus IAB. Output, and interrupt signal 80
Is output to the CPU core 2.

The bus state controller 9 is connected to the address buses IAB, PAB and the data buses IDB, PDB, and controls the interface between the CPU core 2 and the built-in peripheral circuits 10, 11 connected to the address buses PAB and PDB. To do.

The external memory interface 12 is connected to the address bus IAB and the data bus IDB, is connected to an address bus and a data bus (not shown) outside the chip of the microcomputer 1, and controls the interface with the outside.

FIG. 2 shows an example of the address map of the microcomputer 1. The microcomputer 1 of this embodiment manages an address space defined by 32 bits. The address bus IAB has a bit width of 32 bits. In the address space, an exception processing vector area, an X-ROM space (address space allocated to the X-ROM 4), an X-RAM space (address space allocated to the X-RAM 7), a Y-ROM space ( Y-ROM
5), Y-RAM space (address space allocated to Y-RAM 7), internal peripheral circuit allocation space (address space to which internal peripheral circuits 10 and 11 are allocated), and the like. 2 is X
-ROM4 is 24KB, X-RAM6 is 4KB, Y-RO
24 KB is allocated to M5 and 4 KB is allocated to Y-RAM7.

According to FIG. 2, H'000 in hexadecimal notation
An exception processing vector area is allocated to the 256B area in the space of 0000 to H'000003FF. H '
A normal space usable by the user is allocated to 00000400 to H'01FFFFFF. The normal space is a memory area that can be connected to the outside of the microcomputer 1. H'02000000 ~ H'02005
An X-ROM space is allocated to the FFF. H '
X-RA is available for 0200000-H'02006FFF.
M space is allocated. H'02000700
H'02007FFF is an X-RAM_Mirror space, and when you access it, it is actually H'020060.
The X-RAM space of 00 to H'02006FFF will be accessed. H'020008000 to H'0200F
The FFF is an X-RAM, RAM_Mirror space, and when you access it, it is actually H'0200000.
0-H'02007FFF X-ROM space and X-R
You will be accessing the AM space. H'020100
A Y-ROM space is allocated to 00 to H'02015FFF. H'020160000-H'02016
A Y-RAM space is allocated to the FFF. H '
02017000-H'02017FFF is Y-RAM_
It is a Mirar space, and when you access it, it is actually Y-of H'020160000-H'02016FFF.
RAM space will be accessed. H'02018
000-H'0201FFFF is Y-ROM, RAM_
It is a Mirar space, and when you access it, it is actually Y-of H'0201000-H'02017FFF.
The ROM space and the Y-RAM space will be accessed. A normal space is allocated to H'0202000-H'07FFFFFFF. H'080000
Reserved areas are allocated to 00 to H'1FFFFFFFF. This reserved area is inaccessible in the case of a user chip (real chip), and an evaluation chip (evaluation chip used for emulation etc.)
In the case of, the ASE space (control space for emulation) is allocated. H'20000000
A normal space is allocated to H'27FFFFFFF. H'2800000-H'FFFFFDFF
A reserved area is allocated to. H'FFFFFF
A built-in peripheral circuit allocation area for allocating the register address value of the built-in peripheral circuit is allocated to E00 to H'FFFFFFFF.

FIG. 3 is a block diagram of the CPU core 2 showing the modulo address output unit in detail. In FIG. 3, the part surrounded by the broken line is the modulo address output unit 200.
Is. The modulo address output unit 200 outputs the value output from the modulo address register (for example, A0X) to the address bus (for example, XAB) through the buffer (for example, MABX), and at the same time, adds the value output from the modulo address register (A0X) for adding means ( AL for example
U) and add again modulo address register (A0
X) is a circuit block that performs an address update output operation, etc., and sequentially updates and generates data access addresses for iterative operations such as product-sum operations. A circuit block described as a random logic circuit 201 is a circuit block including the decoder 24 of FIG. 1, the sequence control circuit, a control register, a status register, and the like.

In FIG. 3, C1, C2, DR, A1, B
1, A2, B2 and DW are representatively shown buses inside the CPU core 2. The interface between the CPU core 2 and the data bus IDB is the instruction register (IR).
25 and the data buffer (Data Buffer) 203. The instruction fetched in the instruction register (IR) 25 is a random logic circuit (Random Logic Circuit) 2
01 is supplied to the decoder 24 and the like. CP
The interface between the U core 2 and the address bus IAB is performed by a program counter (PC) 204 and an address buffer (Address Buffer) 205. The interface between the CPU core 2 and the address bus XAB is performed by the memory address buffer (MABX) 206.
The memory address buffer (MABY) 207 interfaces with the address bus YAB. The input path of the address information to the address buffer 205 is the bus C.
1, A1, A2 can be selected, and the input path of the address information to the memory address buffers 206, 207 can be selected from the buses C1, C2, A1, A2. The arithmetic unit (AU) 208 is used to increment the value of the program counter 204. 209 is a general-purpose register (Reg.), 210 is an index register (Ix) used for address index modification, 21
Reference numeral 1 is an index register (Iy) which is also used for index modification, 212 is an adder (PAU) dedicated to address calculation, and 213 is an arithmetic logic unit (ALU).

The control bit MXY designates which address of the address bus XAB or the address bus YAB is to be subjected to the modulo operation. The logical value "1" indicates the address bus XAB and the logical value "0" indicates the address bus Y.
Specify AB. The control bit DM indicates whether to perform a modulo operation, a logical value "1" indicates that the modulo operation is performed, and a logical value "0" indicates that the modulo operation is not performed. The modulo start address register (MS) 214 stores the modulo operation start address, and the modulo end address register (ME) 21
5 stores the modulo operation end address.

Modulo address register (A0x, A1
x) 216 is a current address register for storing the current modulo address, 217 is a comparator (CMP) for comparing the value of the modulo end address register (ME) 215 with the value of the modulo address register (A0x, A1x) 216, and 218 is for An AND gate 219 that takes the logical product of the output of the comparator 217 and the three inputs of the control bits MXY and DM is a selector that selects the value of the bus C1 and the value of the modulo start address register (MS) 214. Used for modulo arithmetic on address bus XAB. The selector 219 registers (MS) with the logical value “1” output from the AND gate 218.
The value of 214 is selected, and the selected value is given to the modulo address register (A0x, A1x) 216. The modulo address register 216 is used by selecting either A0x or A1x.

Modulo address register (A0y, A1
y) 226 is a current address register that stores the current modulo address, 227 is a comparator (CMP) that compares the value of the modulo end address register (ME) 215 with the value of the modulo address register (A0y, A1y) 216, and 228 is 3 of the output of the comparator 227, the inverted bit of the control bit MXY, and the control bit DM
An AND gate that takes the logical product of the inputs, 229 is the value of the bus C2 and the modulo start address register (MS)
Selectors for selecting the value of 214 and they are used for the modulo operation on the address bus YAB. The selector 229 selects the value of the register (MS) 214 by the logical value “1” output of the AND gate 228, and selects the selected value as the modulo address register (A0y, A1y) 2
Give to 26. Modulo address register 226 is A0
Either y or A1y is selected and used.

The OP Code described in the random logic circuit 201 means the instruction code supplied from the instruction register 25, and the CONST means a constant value.

Here, as a modulo arithmetic operation in the CPU core 2, for example, a modulo address register (A
0x) 216 will be used to describe the operation of generating address information to be supplied to the address bus XAB by modulo arithmetic.

First, the modulo operation start address is written in the modulo start address register (MS) 214, and the modulo operation end address is written in the modulo end address register (ME) 215. An address value for starting the modulo operation is written in the modulo address register (A0x). Next, since modulo arithmetic is performed on the address of the address bus XAB, XAB, YAB
A logical value "1" is written to the control bit MXY that determines which address of the control bit MXY is to be operated (when performing a modulo operation to the address bus YAB, a logical value "0" is written to the control bit MXY. Written). Finally, the logical value "1" is written in the control bit DM that determines whether or not to perform the modulo operation.

The modulo arithmetic instruction is, for example, MOVS.W.
@Ax, Dx. In this instruction description, Ax is the modulo address register (A0x) 216 or modulo address register (A1x) 216, and Dx is D
Corresponds to a register in the SP engine 3. In Figure 3, Dx
Are not shown. When the modulo arithmetic instruction is executed, the value is read from the modulo address register (A0x) 216 and the memory address buffer (MABX) is read.
206 and the arithmetic logic unit (ALU) 213. The value input to the memory address buffer (MABX) 206 is output to the address bus XAB as it is,
The address of XROM4 or XRAM6 is designated. On the other hand, the value of the modulo address register (A0x) 216 input to the arithmetic logic unit (ALU) 213 is the value of the index register (Ix) 210 or the constant (Const).
Is added. When performing addition with the index register (Ix) 210, the instruction MOVS.W @ (Ax, I
x), Dx, etc. are executed, and when constant addition is performed, the instruction MOVS.W @Ax, Dx, etc. is executed. The addition result is the arithmetic logic unit (ALU) 213.
Will be output. The value output from the arithmetic logic unit (ALU) 213 enters the selector 219. The other input of the selector 219 is the modulo arithmetic start address stored in the modulo start address register (MS) 214.

Whether the output of the selector 219 becomes the output of the arithmetic logic unit (ALU) 213 or the value of the modulo start address register (MS) 214 is determined as follows. Modulo address register (A0
x) value of 216 and modulo end address register (M
E) The value of 215 is constantly compared by the comparator (CMP) 217, and if they match, the value of the comparator (CMP)
A logical value "1" is output from 217, and a logical value "0" is output if they do not match. Comparator (CMP) 217
The output value is ANDed with the control bits DM and MXY by the AND gate 218 (in this example, D
Since both M and MXY have the logical value "1", the comparator 21
The value of 7 is output from the AND gate 218 as it is. ), And is input to the selector 219. Selector 219
Is the logical value of the value input from the AND gate 218.
In case of 1 ”, modulo start address register (M
S) 214 value is selected, and when the logical value is “0”, the output value from the arithmetic logic unit (ALU) 213 is selected.

While the value input from the AND gate 218 is the logical value "0", the output value from the arithmetic and logic unit (ALU) 213 is continuously selected, so that the value output to the address bus XAB is sequentially. Will be updated. When the value of the modulo end address register (ME) 215 matches the value of the modulo address register (A0x) 216, the value input from the AND gate 218 to the selector 219 becomes the logical value "1", and the modulo start address register ( MS) 214 value. Thereby, the modulo address register (A0x) 216 is initialized by the value of the modulo start address register (MS) 214.

In the above description of the modulo operation, the operation when the modulo address register (A0x) 216 is used has been described. However, the modulo operation instruction MOVS.W@A
x, Ax in Dx is modulo address register (A
It is also possible to specify 1x) 216. If a logical value "0" is designated in the control bit MXY, modulo arithmetic can be performed on the address bus YAB. in this case,
Modulo arithmetic instruction MOVS.W @A in Ax, Dx
x must be changed to the value Ay to specify the modulo address register (A0y) 226 or (A1y) 226. If 0 is specified in the control bit DM,
It is also possible to prohibit the execution of modulo arithmetic.

FIG. 4 shows an example block diagram of the DSP engine 3. Random Logic C
The circuit block described as ircuit) 301 is a circuit block including the decoder 34 and the control circuit of FIG. 1, and a control register and a status register. In addition, the DSP engine 3 is an arithmetic logic unit (ALU)
302, shifter (SFT) 303, multiplier (MAC) 3
04, register (Reg.) 305, register (A0, A
1) 306, register (Y0, Y1) 307, register (X0, X1) 308, memory data buffer (MDB
I) 309, memory data buffer (MDBX) 31
0, a memory data buffer (MDBY) 311 is provided. The memory data buffer (MDBY) 311 connects the data bus YDB and the bus D2. The memory data buffer (MDBX) 310 connects the data bus XDB and the bus D1. A memory data buffer (MDBI) 309 is connected to the data bus IDB and buses C1, D1, A1 and B1. Multiplier (MAC) 304 includes buses A1 and B1
More data is input, and the multiplication result is input to the bus C1.
And D1. Shifter (SFT) 303 is bus A
Data is input from 2 and the shift operation result is output to the bus C2. An arithmetic logic unit (ALU) 302 receives data from the buses A2 and B2 and outputs the operation result to the bus C2.

FIG. 5 shows an example of an instruction format and an instruction code included in the instruction set of the microcomputer 1. The microcomputer 1 supports two types of instructions, a CPU instruction and a DSP instruction. CP
All U instructions and some DSP instructions are 16-bit long instruction codes, and the remaining DSP instructions are 32-bit long instruction codes. The CPU instruction is an instruction executed exclusively by the CPU core 2 without operating the DSP engine 3. The DSP instruction is an instruction executed by the DSP engine 3 by causing the CPU core 2 to bear a part of processing such as address calculation or operand access.

As for the CPU instruction, the instruction is assigned to a space in which the most significant 4 bits of the instruction code are "0000" to "1110". In the DSP instruction, all the 4 most significant bits of the instruction code are assigned to “1111”. In addition, the 6 most significant bits of the instruction code are "111".
The instructions assigned to "100" and "111101" are 16-bit instruction codes even for DSP instructions. The uppermost 6 bits of the instruction code are "11111".
The instruction of “0” has an instruction code of 32 bits in length. The uppermost 6 bits of the instruction code is “11111”.
No instruction is allocated to the 1 "space, which is an unused area (undefined instruction area). The instruction code can be further expanded by using this area in the future. As described above, if the most significant 6 bits of each instruction code are decoded, it is determined whether the instruction is a CPU instruction or a 16-bit DSP instruction.
It is possible to determine whether the instruction is a DSP instruction having a bit length or an undefined instruction with a decoder having a small logic scale. In the CPU command format of FIG. 5, nnnn
Is the specified area of the destination operand, sss
s is a source operand designation area, dddd is a displacement designation area, and iiiiiiiii is an immediate value designation area. In the case of an ADD instruction, nnnn is also the designated area of the source operand, and the operation result is stored in nnnn. Further, the modulo operation instruction described with reference to FIG. 3 is the instruction MOV of FIG.
Although it corresponds to SW @ R2, A0, the instruction description in FIG. 5 is different in the description form of the operand designation from the content described in FIG. This is just a difference in form, and is essentially the same.

FIG. 6 shows the decoder 24 and D of the CPU core 2.
An example of the connection configuration of the SP engine 3 with the decoder 34 is shown. 32 instruction fetches by the microcomputer 1
It is performed in the instruction register (IR) 25 bit by bit. The decoder 24 includes a first decoding circuit 240, a second decoding circuit 241, and a code conversion circuit 242. The first decoding circuit 240 decodes the value of the upper 16-bit area (UIR) of the instruction register (IR) 25 to determine whether the instruction is a CPU instruction, a 16-bit DSP instruction, or a 32-bit DSP instruction. CPU decode signal 243, DSP decode signal 244, code conversion control signal 245, and shift control signal 246 are generated. The second decode circuit 241 uses the CPU decode signal 2
43 is decoded to generate various internal control signals (CPU control signals) 247 for selecting arithmetic units and registers inside the CPU core 2. When the code conversion circuit 242 is activated by the code conversion control signal 245, the code conversion circuit 242 compresses or outputs the number of bits of information held in the lower 16-bit area (LIR) of the instruction register (IR) 25, When it is deactivated by the code conversion control signal 245,
Information (non-operation code) indicating that the output is invalid is output. The code conversion circuit 242 uses the signal 24
When 5 is inactive, the lower 16-bit area (LI
In the sense that a non-operation code is output instead of the value of R), it can be realized by a selector. DSP decode signal 244 and code conversion circuit 2
The output of 42 is supplied to the decoder 34 of the DSP engine 3 as the DSP control signal 20. The first decoding circuit 240 includes the uppermost 6 bits stored in the upper 16-bit area (UIR) of the instruction register (IR) 25.
By decoding the bit, the relevant instruction code becomes C
It is possible to determine whether it is a PU instruction, a 16-bit DSP instruction, or a 32-bit DSP instruction.

When the decoded instruction is a 16-bit instruction, the code conversion control signal 245 is inactivated, so that the code conversion circuit 242 outputs a non-operation code meaning that the output is invalid. Also,
If the decoded instruction is a 16-bit instruction, the shift control signal 246 is activated, and the instruction register (IR) 25 that receives it is in the lower 16-bit area (L).
The value of (IR) is shifted to the upper 16-bit area (LIR), and the shifted instruction is used as all or part of the instruction to be executed next. For example, instruction register IR
16-bit CPU instruction is stored in the upper 16-bit area UIR of the
A case where the upper 16-bit instruction code of the P instruction is stored will be described. First, the upper 16-bit area UIR
The 16-bit CPU instruction stored in is decoded by the first decoding circuit 240, the CPU core 2 executes the instruction according to the result, and the upper 16 bits of the 32-bit DSP instruction stored in the lower 16-bit area LIR. The instruction code data of is transferred to the upper 16-bit area UIR. At this time, the random logic circuit 201 causes the arithmetic operation unit AU208 to execute the address operation of the address to be stored in the program counter PC. The program counter PC stores an address according to the address calculation result calculated by the arithmetic operation unit AU208. According to the address stored in the program counter PC, the lower 16-bit instruction code data of the 32-bit DSP instruction is transferred from the instruction memory storing it to the lower 16-bit area LIR of the instruction register IR. As a result, the 32-bit DSP instruction is stored in the instruction register IR. Then, the 32-bit DSP instruction stored in the instruction register IR is supplied to the decoder 34 of the DSP engine 3 via the decoder 24. As another method, although not shown, a plurality of instruction prefetch buffers are provided in the CPU core 2. The plurality of instruction prefetch buffers prefetch an instruction to be executed several cycles ahead of the currently executed instruction. When such a prefetch buffer is provided, as described above, 32-bit D
When the upper 16-bit instruction code data of the SP instruction is transferred from the lower-side area LIR to the upper-side 16-bit area UIR, the random logic circuit 201 prefetches the lower 16-bit instruction code data of the 32-bit DSP instruction. Selected instruction prefetch buffer. 3 from the selected instruction prefetch buffer
The lower 16-bit instruction code data of the 2-bit DSP instruction is read and stored in the lower 16-bit area LIR of the instruction register IR.

CPU whose decoded instruction is 16 bits
If it is an instruction, the DSP decode signal 244 is a code that means non-operation. CPU if the decoded instruction is a 16-bit DSP instruction
The control signal 247 is generated by the second decode circuit 241 based on the CPU decode signal 243, and the DSP engine 3
The internal control signal is substantially generated by the decoder 34 decoding the DSP decode signal 244. When the decoded instruction is a 32-bit DSP instruction, the CPU control signal 247 is generated by the second decoding circuit 241 based on the CPU decode signal 243, and the control signal inside the DSP engine 3 is the code including the DSP decode signal 244. Conversion circuit 2
Decoder 34 decodes and produces the output of 42.

The instruction set of the microcomputer 1 has an instruction code length of 16 bits and an instruction code length of 32 bits, and the processing is different between the 16-bit length instruction and the 32-bit length instruction as described above. The operation will be described in detail.

First, the case of a 16-bit length instruction will be described. The first decoding circuit 240 includes an instruction register (I
R) The upper 16 bits of the 32-bit instruction code fetched by R) 25 are decoded. In the first decoding circuit 240, when the most significant 6-bit code of the instruction code is other than "111110" and "11111", 16
Since it can be seen that it is a bit length instruction, CP at this time
Along with the output of the U decode signal 243 and the DSP decode signal 244, the instruction code data in the lower 16-bit area LIR of the instruction register (IR) 25 is transferred to the upper 16-bit area U.
The shift control signal 246 for shifting to IR is activated. The instruction register (IR) 25 receiving the activated shift control signal 246 shifts the instruction code stored in the lower 16-bit area LIR to the upper 16-bit area UIR. The shifted instruction code is the first
Will be decoded by the decoding circuit 240. CPU decode signal 243 output from the decoder 24
Is output to the second decode circuit 241, and the DSP decode signal 244 is supplied to the DSP engine 3. When the first decoding circuit 240 finds that the instruction is a 16-bit length instruction, it deactivates the code conversion control signal 245, so that the code conversion circuit 242 causes the lower 16 bits.
The code indicating that the instruction code of the bit is invalid is D
It is generated as a part of the SP control signal 20. On the DSP engine 3 side, D output from the first decoding circuit 240
When the SP decode signal 244 and the code signal output from the code conversion circuit 242 are input as the DSP control signal 20, the decoder 34 decodes the DSP control signal 20. In the case of a 16-bit DSP instruction, the DSP control signal output from the code conversion circuit 242 is a signal indicating invalidity. (MAC) 304, arithmetic logic unit (ALU)
The control signals of 302 and the shifter (SFT) 303 are output. The DSP engine 3 performs arithmetic processing according to those control signals.

Next, the case of a 32-bit length instruction will be described. The first decoding circuit 24 inside the CPU core 2
At 0, a 32-bit instruction code is stored in the instruction register (IR) 25. Then, the upper 16 bits are decoded by the first decoding circuit 240, and the decoded signals 243, 2
44 is output. In the first decoding circuit 240, when the most significant 6-bit code of the instruction code is "111110", it is understood that the instruction is a 32-bit length instruction. Therefore, the code conversion control signal 245 is activated, whereby the code conversion circuit 242 is activated. Is the lower 1 of the instruction register (IR) 25
6-bit instruction code is converted. The code-converted information is supplied to the DSP engine 3 as the DSP control signal 20 together with the DSP decode signal 244. The decoder 34 decodes the DSP control signal 20 to generate a control signal inside the DSP engine 3. Incidentally, the decoder 24,
34 can be realized by a random logic circuit, for example.

FIG. 17 shows another embodiment corresponding to FIG. In the embodiment shown in FIG. 6, the instruction data in the lower area LIR of the instruction register 25 is shifted to the upper area UIR. In the embodiment shown in FIG. 17, between the instruction register 25 and the internal data bus IDB, serial two-stage instruction prefetch buffers 250 and 251 forming an instruction prefetch queue are provided, and the data held in the instruction prefetch buffers 250 and 251 are stored. The selection is made by the selector 252 and is given to the instruction register 25.
Each of the instruction prefetch buffers 250 and 251 and the instruction register 25 holds data in 32-bit units,
The holding operation is controlled by control signals φ1 to φ3 (synchronized with CLK1). Although not particularly shown, the instruction prefetch buffers 250 and 251 and the instruction register 2
Each of 5 has a master-slave configuration, the master stage performs an input latch operation in synchronization with the rising edge of the corresponding control signal, and the slave stage synchronizes with the falling edge of the corresponding control signal. Performs input latch operation. As a result, the serial two-stage instruction prefetch buffers 250, 2
In 51, instruction data before and after prefetching is stored.

The selector 252 has a selection control signal φ4.
According to the above, the 32-bit instruction data supplied to the port Pa or the 32-bit instruction data supplied to the port Pb is selected and given to the instruction register 25. The port Pa
Is supplied with 32-bit instruction data having the upper 16-bit area UPB1 of the instruction prefetch buffer 250 as the lower side and the lower 16-bit area LPB2 of the instruction prefetch buffer 251 as the upper side. 32 stored in the instruction prefetch buffer 251 at the port Pb
Bit instruction data is supplied as it is.

As a result, the instruction prefetch buffer 2
When 51 holds a 32-bit DSP instruction, the selector 252 can set the 32-bit DSP instruction in the instruction register 25 by selecting the output of the port Pb. Instruction prefetch buffer 2
51 is a 16-bit DSP instruction or 16-bit CPU
When the instruction is held in the upper area UPB2, the selector 252 selects the output of the port Pb to output the 16-bit instruction to the upper area UI of the instruction register 25.
Can be set to R. The instruction prefetch buffer 251 has a 16-bit DSP instruction or a 16-bit C instruction.
When the PU instruction is held in the lower area LPB2, the selector 252 can set the 16-bit instruction in the upper area UIR of the instruction register 25 by selecting the output of the port Pa. The instruction prefetch buffer 251 holds the upper 16-bit instruction code of the 32-bit DSP instruction in the lower area LPB2, and the instruction prefetch buffer 250 holds the lower 16-bit instruction code of the 32-bit DSP instruction in the upper area UPB1. If so, the selector 252 can set the 32-bit DSP instruction in the instruction register 25 by selecting the output of the port Pa.

In FIG. 17, reference numeral 253 is a control logic for generating the latch control signals φ1 and φ2 of the instruction prefetch buffer, the latch control signal φ3 of the instruction register 25, and the selection control signal φ4. The control logic 253 has a control signal 248 indicating whether it is a 16-bit instruction or a 32-bit instruction and the instruction prefetch buffers 250 and 25.
The control signals .phi.1 to .phi.4 are generated in accordance with the state of the instruction code that remains unexecuted in each area of 1. This control logic 253 forms part of the control logic for instruction fetch. It should be noted that the control signal 248 indicates that the first decoding circuit 240 has an upper area UI of the instruction register 25.
It is generated by decoding the upper 6 bits of the instruction code data supplied from R, and the details thereof will be described later.

Instruction register 2 by the control logic 253
The instruction code data set to 5 is as follows. For the instruction fetch from the outside, there is room for newly storing 32-bit instruction code data in the instruction prefetch buffer 250 at the instruction fetch timing of the CPU core 2 (for example, the instruction fetch stage IF in a plurality of pipeline stages described later). In some cases. When an instruction is fetched at that timing, the instruction that has not been executed remains in the instruction prefetch buffer 251. In the first state where both of the instruction codes stored in the areas UPB2 and LPB2 of the instruction prefetch buffer 251 have not been executed yet, the 32-bit output of the instruction prefetch buffer 251 is output via the port Pb to the selector 252. Is selected in and set in the instruction register 25. On the other hand, in the second state where only the instruction code stored in the lower area LPB2 of the instruction prefetch buffer 251 is not yet executed, the upper area UPB1 prefetched in the instruction prefetch buffer 250 and the lower area of the instruction prefetch buffer 251 are prefetched. The instruction code data in the area LPB2 is set in the instruction register 25 via the port Pa.

In the first state, the instruction register 2
As a result of the decoding circuit 240 decoding the instruction code data set in the upper area UIR of No. 5, if it constitutes a 32-bit instruction, at that time, 3 prefetched to the instruction prefetch buffer 250 is performed.
The 2-bit instruction code data is transferred to the instruction prefetch buffer 251 as it is. On the other hand, when it is detected from the decoding result that it is a 16-bit instruction,
From the instruction prefetch buffer 250 to the next buffer 2
No data shift to 51 is performed.

In the second state, after the data is set in the instruction register 25 via the port Pa, the 32-bit instruction code data prefetched in the instruction prefetch buffer 250 is directly shifted to the instruction prefetch buffer 251. Set. After this shift setting, if there is no unexecuted instruction code data in the instruction prefetch buffer 250, the instruction code data is prefetched in the instruction prefetch buffer 250 at the next instruction fetch timing.

By such control, the instruction code data which has not been processed yet is set in the instruction register 25 after the instruction fetch timing. At this time, regardless of whether the instruction to be executed is a 16-bit CPU instruction, a 16-bit DSP instruction, or a 32-bit DSP instruction, the upper 16 bits of the instruction are always the first decoding circuit 2
40 will be supplied.

The code conversion circuit 242 described with reference to FIG.
In FIG. 17, the selector 242A and the code conversion logic 24
2B. In addition, the first decoding circuit 2
In the description of FIG. 6, the 40 generates the control signals 245 and 246 whose levels are controlled depending on whether the instruction code decoded by the 40 is a 16-bit instruction.
In the example, whether the instruction code decoded by the instruction is a 16-bit instruction or not, a 32-bit instruction (in the present embodiment, 32
A control signal 248 for identifying whether the bit command is a DSP command) is output. Selector 242A
When the control signal 248 means a 16-bit instruction, the no-operation code NOP is selected and supplied to the code conversion logic 242B.
When it means a bit DSP instruction, the instruction code of the lower area LIR of the instruction register 25 is supplied to the code conversion logic 242B. Code conversion logic 24
2B is not particularly limited, but a part of the instruction code data in the lower region LIR of the instruction register 25, for example, code information for register selection, is used by the decoder 3 of the DSP engine 3.
It is corrected to a form suitable for 4 and output.

In the embodiment shown in FIG. 17, the first decoding circuit 240 decodes the 16-bit instruction code data held in the upper area UIR of the instruction register 25, and the CPU decode signal 243 obtained by this decoding is decoded by the second decoding circuit 240. The signal is supplied to the circuit 243, and the DSP decode signal 244 is supplied to the decoder 34. The CPU decode signal 243 is
It is significant in both the CPU instruction and the DSP instruction and is supplied to the second decoding circuit 241. The second decode circuit 241 decodes the CPU decode signal 243 to generate control information for address calculation and data calculation that the CPU core 2 should perform, and an internal memory X-ROM.
4, Y-ROM 5, X-RAM, Y-RAM and selection control information of an address bus and a data bus for accessing an external memory are output. As mentioned above, DS
For the P instruction, the CPU core 2 performs the necessary address calculation and data path selection.

As described above, the DSP decode signal 244 is a significant decode signal when the instruction code supplied to the first decode circuit 240 is code data for a DSP instruction. The significant DSP decode signal 244 includes, for example, designation information such as a register in the DSP engine 3 that transfers data to and from a memory accessed according to an address calculation performed by the CPU core 2. When the instruction code supplied to the first decode circuit 240 is a CPU instruction, the DSP decode signal 244 is set to a code meaning invalid.

Now, the code of the DSP instruction included in the instruction set of the microcomputer 1 will be described in more detail. 18 and 19 show the instruction code of the 16-bit DSP instruction, and FIGS. 20 and 21 show the instruction code of the 32-bit DSP instruction. As aforementioned,
In the DSP instruction, the 4 most significant bits of the instruction code are "1".
The most significant 6 bits of the instruction code are “111100” and “111101” are 16-bit DSP instructions, and the most significant 6 bits of the instruction code are “111110” instructions are 32-bit DSPs. It is an order.

Column 1 of FIG. 18 (X Side of Data Transfe
The instruction format of the 16-bit DSP instruction shown in r) is X memory (X-ROM4, X-RAM6) and DSP.
The instruction format shown in the second column (Y Side of Data Transfer) is a data transfer instruction with the internal register of the engine 3 and is a Y memory (Y-ROM 5, Y-
This is a data transfer instruction between the RAM 7) and the internal register of the DSP engine 3. In the above instruction format, Ax and Ay designate registers included in the register array 209 (see FIG. 3) included in the CPU core 2, Ax = “0” designates the register R4, and Ax = ”.
1 "designates the register R5, Ay =" 0 "designates the register R6, Ay =" 1 "designates the register R7. Dx, Dy, Da designate the registers included in the DSP engine, and Dx = “0” means register X0, Dx = ”
1 "is register X1, Dy =" 0 "is register Y0, D
y = “1” is register Y1, Da = “0” is register A
0 and Da = “1” respectively designate the register A1. I
x and Iy mean immediate values.

The instruction format of the 16-bit DSP instruction shown in FIG. 19 is a data transfer instruction between a memory (not shown) connected to the outside of the microcomputer 1 and a built-in register of the DSP engine 3. As is a register array 209 built in the CPU core 2 (see FIG.
Register), and Ds is a register X1, X0, Y1, Y0, A built in the DSP engine.
1, A0 and registers included in the register array 305 (see FIG. 4) are designated.

The format of the 32-bit DSP instruction is
Code "111" indicating a 32-bit DSP instruction
It is roughly divided into a 110 "area (bit 31 to bit 26), an A field (bit 25 to bit 16), and a B field (bit 15 to bit 0). A code and its corresponding mnemonic are shown, and FIG. 21 shows the code of the field and its corresponding mnemonic when attention is paid to the B field.

The code of the A field shown in FIG. 20 is bit 9 of the 16-bit DSP instruction shown in FIG.
~ The same as the code of bit 0, and the code of the A field shown in the first column (X Side of Data Transfer) of FIG. 20 is X memory (X-ROM4, X-RAM6) and D
Data transfer to and from the internal register of the SP engine 3 is defined, and the code of the A field shown in the second column (Y Side of Data Transfer) is the Y memory (Y-ROM).
5, Y-RAM 7) and the internal registers of the DSP engine 3 are defined. The contents designated by the bits Ax, Ay, Dx, Dy, Da included in the A field are exactly the same as those in FIG.

The code of the B field shown in FIG. 21 defines processing such as arithmetic operation, logical operation, shift operation, and load / store between registers performed inside the DSP engine 3. For example, multiplication (PMULS), subtraction (PSUB), addition (PADD), rounding (PRND), shift (PSH) performed inside the DSP engine 3.
L), logical product (PAND), exclusive OR (XOR),
Operations such as logical sum (OR), increment (PINC), decrement (PDEC), clear (CLR),
Load (PLDS) performed inside the DSP engine 3
And stores (PSTS), etc. The third column (3 Operand Operation with Condition) in FIG. 21 is a code with a condition, and the condition (if cc) is DC.
A logical value of the (data complete) bit (a bit indicating the completion of data processing) or ignoring can be selected.

The actual 32-bit DSP instruction is described by arbitrarily combining the B field code and the A field code. That is, the 32-bit DSP instruction defines a process of fetching an operand to be operated from inside or outside the microcomputer 1 and operating it in the DSP engine 3. As is clear from the above description, the CPU 2 performs the address calculation and the data path selection for the operand fetch. In the 32-bit DSP instruction, the A field code that defines the operand fetch is a 16-bit DSP
Same as the command. The 16-bit DSP instruction is used for initialization of registers inside the DSP engine 3.

As is apparent from the configuration shown in FIG. 17 and the like, the code data of the A field of the 32-bit DSP instruction is the upper area UIR in the instruction register 25.
Is set to. A 16-bit DSP instruction having the same format as the A field is also set in the upper area UIR. Therefore, in any of them, CP
The U core 2 may similarly perform the necessary address calculation and the selection of the data path necessary for the data fetch (or operand fetch). In other words, 32-bit DS
Decoding circuits 240 and 241 required for data fetch (or operand fetch) for executing the P instruction and data fetch (or operand fetch) for executing the 16-bit DSP instruction are made common, and in this respect, Also contributes to the reduction of the logical scale of the microcomputer 1. The designation information of the internal register of the DSP engine 3 designated by the A field of the 32-bit DSP instruction and the designation information of the internal register of the DSP engine 3 designated by the 16-bit DSP instruction are given to the DSP engine 3 as the DSP decode signal 244. . DS
Whether or not the P decode signal 244 is significant is determined by the first
The decoding circuit 240 of 4 is located on the uppermost side of the upper area UIR.
Determine the bit by decoding it.

Next, the contents of arithmetic control in the microcomputer of this embodiment will be described with reference to the instruction execution timing charts of FIGS. The microcomputer 1 of the present embodiment includes IF, ID, EX, MA, W
The 5-stage pipeline operation of the B / DSP stage is performed. IF is an instruction fetch stage, ID is an instruction decode stage, EX is an operation execution stage, MA is a memory access stage, WB / DSP is a stage for fetching data acquired from a memory into a register of the CPU core 2, or DSP engine 3 is a DSP instruction. This is the stage to execute. In each figure, Instruction / Data Access means memory access via the internal buses IAB and IDB, and the access target can be the internal memory 4 to 7 as well as the external memory of the microcomputer 1. X, Y Mem. Access
Means memory access via the internal buses XAB, XDB and YAB, YDB, and the access target is the internal memory 4 to
Limited to 7. Isnt.Fetch is the instruction register (IR) 25
Fetch.Reg means instruction register (IR) 25, Source Data Out means source data output, Destination In means destination data input timing, and Destination Register means destination register. PointerReg. Is pointer register, Address Calc. Is address operation, D
ata Fetch is data fetch, DSP Control signal Deco
rd Timing means the decoding timing of the DSP control signal 20 by the decoder 34.

FIG. 7 shows an execution time chart of the ALU operation instruction inside the CPU core 2. Here, ADD Rm, Rn is taken as an example of the ALU operation instruction.

Clock signal C immediately before the IF stage
The address in which the instruction (ADD Rm, Rn) to be executed is stored is output to the address bus IAB in synchronization with the rising edge of lock2. Instruct
In ion / Data Mem. Access, memory access operation is performed in the IF stage. Specifically, the clock signal Clo
The address specified by the address bus IAB is decoded in the period from the rising of ck1 to the rising of the clock signal Clock2, and the clock signal C of the IF stage is clocked.
Next clock signal Cloc from the rising edge of lock2
Instruction access is performed during the rising edge of k1. Therefore, an instruction is output to the data bus IDB from the rising edge of the clock signal Clock2 of the IF stage. The instruction output to the data bus IDB is taken into the instruction register (IR) 25 in synchronization with the rising timing of the clock signal Clock1 of the ID stage. At the ID stage, the data taken into the instruction register (IR) 25 is decoded. The register in which the source data is stored is accessed in synchronization with the rising timing of the clock signal Clock1 of the EX stage, and the value of the register is output to the internal buses A1 and B1 of the CPU core 2. In the instructions ADD Rm, Rn, the registers designated by Rm and Rn are source registers. R
m and Rn are arbitrary registers inside the CPU core 2 (see FIG. 3).
Then, any register in the register 209, A0x, A
1x, Ix, A0y, A1y, Iy, Rm and Rn can be specified). The data output to the internal buses A1 and B1 of the CPU core 2 is the arithmetic logic unit (AL
U) 213 performs addition operation, and the result is output to the internal bus C1 of the CPU core 2. The operation result output to the internal bus C1 of the CPU core 2 is a destination register (the destination register is designated as Rn by the ADDRm, Rn instruction) in synchronization with the rising timing of the clock signal Clock2 of the EX stage. Stored). Thus, in the ALU operation instruction inside the CPU core 2, the instruction execution operation is completed in the three pipeline stages of IF, ID, and EX.

FIG. 8 shows a time chart of the data reading operation from the memory to the CPU core 2. From memory to CP
As an example of a data read operation instruction to the U core 2, M
The operation will be described by taking OV.L@Rm, Rn as an example.
The operations up to instruction fetch (IF) and instruction decode (ID) are the same as those in FIG. 7, and detailed description thereof will be omitted.

Clock signal Clock1 of the EX stage
The data of the register that serves as the address pointer is synchronized with the rising timing of the internal bus A of the CPU core 2.
It is output to 1. In this example, the register serving as the address pointer is the register designated by Rm. Registers that can be designated as Rm are arbitrary registers included in the CPU core 2 (in FIG. 3, arbitrary registers included in Reg., A0x, A1x, Ix, A0y, A1y, and Iy are R
It can be specified as m). Internal bus A of CPU core 2
The data output to 1 is stored in the address buffer 205 and output to the address bus IAB in synchronization with the rising timing of the clock signal Clock2 of the EX stage. On the other hand, the data output to the internal bus A1 of the CPU core 2 is operated by the arithmetic logic unit (ALU) 213. In this case, the arithmetic logic unit (ALU) 21
3 performs 0 addition operation. The result is output to the internal bus C1 of the CPU core 2. Internal bus C1 of CPU core 2
The calculation result output to is stored in the pointer register (in this case, the register designated by Rm) in synchronization with the rising timing of the clock signal Clock2 of the EX stage. In Instruction / Data Mem. Access, MA
During the period from the rising of the clock signal Clock1 of the stage to the rising of the clock signal Clock2, the address output to the address bus IAB is decoded in synchronization with the rising timing of the clock signal Clock2 of the EX stage, and the clock signal of the MA stage is clocked. From the rising edge of Clock2, the next clock signal Cl
Data access is performed during the rising edge of ock1. Therefore, the clock signal Clock2 of the MA stage
Data is output to the data bus IDB from the rising edge of. The data output to the data bus IDB is WB / D
Incorporated into the CPU core 2 in synchronization with the rising timing of the clock signal Clock1 of the SP stage, C
Data is output to the internal bus DW of the PU core 2. WB
The internal bus D of the CPU core 2 is synchronized with the rising timing of the clock signal Clock2 of the DSP stage.
The data on W is stored in the destination register and the operation ends. In this example, the destination register is the register designated by Rn. Registers that can be designated as Rn are arbitrary registers included in the CPU core 2 (in FIG. 3, arbitrary registers in Reg.
x, A1x, Ix, A0y, A1y, Iy can be designated as Rn). As described above, in the data read operation instruction from the memory to the CPU core 2, IF, ID, E
The instruction execution operation is completed in the five pipeline stages of X, MA and WB / DSP.

FIG. 9 shows a time chart of a data write operation command from the CPU core 2 to the memory. CPU core 2
As an example of a data write operation instruction from the memory to the memory,
The operation will be described by taking OV.L Rm, @Rn as an example.
The operations of the instruction fetch (IF) and the instruction decode (ID) are the same as those in FIG. 8, and detailed description thereof will be omitted.

Clock signal Clock1 of the EX stage
The data of the register that serves as the address pointer is synchronized with the rising timing of the internal bus A of the CPU core 2.
It is output to 1. In this example, the register serving as the address pointer is the register designated by Rn. Registers that can be designated as Rn are arbitrary registers included in the CPU core 2 (in FIG. 3, arbitrary registers in Reg.
x, A1x, Ix, A0y, A1y, Iy can be designated as Rn). The data output to the internal bus A1 of the CPU core 2 is stored in the address buffer 205,
The signal is output to the address bus IAB in synchronization with the rising timing of the clock signal Clock2 of the EX stage. On the other hand, the data output to the internal bus A1 of the CPU core 2 is operated by the arithmetic logic unit (ALU) 213. In this case, the arithmetic logic unit (ALU) 213 performs 0 addition operation. The calculation result is output to the internal bus C1 of the CPU core 2. The operation result output to the internal bus C1 of the CPU core 2 is the clock signal Cl of the EX stage.
The data is stored in the pointer register (in this case, the register designated by Rn) in synchronization with the rising timing of ock2. In the case of the instruction MOV.L Rm, @Rn, an address operation is performed in the EX stage, and at the same time, the data to be written in the memory is prepared to be output to the data bus IDB. In synchronization with the rising timing of the clock signal Clock1 of the EX stage, a value is output to the internal bus DR of the CPU core 2 from the register that stores the data to be written in the memory. In this example, the register that stores the data to be written to the memory is R
It becomes the register specified by m. Registers that can be designated as Rm are arbitrary registers included in the CPU core 2 (in FIG. 3, arbitrary registers in Reg., A0x, A1x, I
x, A0y, A1y, Iy can be designated as Rm). The value output to the internal bus DR of the CPU core 2 is M
It is output to the data bus IDB in synchronization with the rising timing of the clock signal Clock2 of the A stage.
In the Instruction / Data Mem. Access, the address output to the address bus IAB is decoded in synchronization with the rising timing of the clock signal Clock2 of the EX stage during the rising period of the clock signal Clock1 of the MA stage to the rising edge of the clock signal Clock2. And the clock signal Clock of the MA stage is clocked.
Data bus ID in synchronization with the rising edge of 2
The data output to B is written, and the operation ends.
In the data write operation command from the memory to the CPU core 2, the operation ends as the CPU core 2 outputs the data to the data bus IDB. Therefore, IF, ID, E
The operation is completed in the four pipeline stages of X and MA.

FIG. 10 shows a time chart when the DSP instruction is executed. As an example of the DSP instruction, PADD
The operation will be described by taking C Sx, Sy, Dz NOPX NOPY as an example. This instruction is for DSP engine 3
Add the data stored in the register inside,
DSP engine 3, X-ROM 4, X-RAM 6, and Y
-The instruction is not to transfer data between the ROM 5 and the Y-RAM 7.

Since the instruction fetch operation is the same as that shown in FIG. 7, a detailed description of that portion will be omitted. In the ID stage, clock signal Clock1 to clock signal Clock2
During this period, the instruction code fetched by the CPU core 2 is decoded, and the clock signal Clock of the ID stage is clocked.
The result of decoding the instruction code at the timing of 2 is DS
The P control signal 20 is output to the DSP engine 3.
When the DSP control signal 20 is input from the CPU core 2, the DSP engine 3 decodes the DSP control signal 20 input during the period up to the MA stage. The register storing the source data is accessed in synchronization with the rising timing of the clock signal Clock1 of the WB / DSP stage, and the internal bus A of the DSP engine 3 is accessed.
2, the register value is output to B2. In this example, the registers storing the source data are Sx and S
It becomes the register specified by y. Registers that can be designated as Sx and Sy are arbitrary registers inside the DSP engine 3 (in FIG. 4, arbitrary registers within Reg. Can be designated as Sx and Sy). The data output to the internal buses A2 and B2 of the DSP engine 3 is operated by the arithmetic logic unit (ALU) 302, and the result is the DSP.
It is output to the internal bus C2 of the engine 3. The calculation result output to the internal bus C2 of the DSP engine 3 is WB / D.
It is stored in the destination register in synchronization with the rising timing of the clock signal Clock2 of the SP stage. In this example, the destination register is the register designated by Dz. The register that can be designated as Dz is any register inside the DSP engine 3 (in FIG. 4, any register inside Reg.). In the above DSP instruction, IF, ID, EX, MA,
The operation is completed in the five pipeline stages of WB / DSP.

FIG. 11 shows a time chart of a data read operation command from the X, Y memories 4 to 7 to the DSP engine 3. As an example of a data read operation command from the X, Y memories 4 to 7 to the DSP engine 3, MOVX.W
The operation will be described by taking @Ax, Dx MOVY.W @Ay, Dy as an example. The instructions are Ax and A
This is an instruction to transfer the data stored at the address designated by y to the register designated by Dx and Dy. The operation of instruction fetch and instruction decode is the same as that in FIG. 10, and thus detailed description thereof will be omitted.

From the X, Y memories 4 to 7 to the DSP engine 3
When executing a data read operation instruction to the CPU core 2, the memory address to be accessed is generated by the CPU core 2. Therefore, the register storing the address to be accessed is accessed in synchronization with the rising timing of the clock signal Clock1 in the EX stage, and the CP
The register value is output to the internal buses A1 and A2 of the U core 2. In this example, the register storing the address to be accessed is the register designated by Ax and Ay. Registers that can be specified as Ax are registers A0x and A1x included in the CPU core 2, and registers that can be specified as Ay are registers A0y and A1 included in the CPU core 2.
It is y. The data output to the internal buses A1 and A2 of the CPU core 2 is stored in the memory address buffer (MABX, MBX).
ABY) and the clock signal Cl of the EX stage
The data is output to the address buses XAB and YAB in synchronization with the rising timing of ock2. On the other hand, the data output to the internal buses A1 and A2 of the CPU core 2 is ALU21.
3, PAU 212 performs address calculation. In this case, ALU 213 and PAU 212 perform 0 addition operation. The calculation result is output to the internal buses C1 and C2 of the CPU core 2. Internal buses C1 and C of the CPU core 2
The calculation result output to 2 is stored in the pointer register (in this case, the register designated by Ax and Ay) in synchronization with the rising timing of the clock signal Clock2 of the EX stage. In the X and Y memories 4 to 7, M
In the period from the rising of the clock signal Clock1 of the A stage to the rising of the clock signal Clock2, EX
The addresses output to the address buses XAB and YAB are decoded at the rising timing of the stage clock signal Clock2, and the next clock signal Cl is output from the rising of the clock signal Clock2 of the MA stage.
Data access is performed during the rising edge of ock1. Therefore, the clock signal Clock of the MA stage
Data is output to the data buses XDB and YDB from the rising edge of 2. The data output to the data buses XDB and YDB is the clock signal Clo of the WB / DSP stage.
The internal bus D of the DSP engine 3 is fetched by the DSP engine 3 in synchronization with the rising edge of ck1.
Data is supplied to 1 and D2. The data on the internal buses D1 and D2 of the DSP engine 3 are stored in the destination register in synchronization with the rising timing of the clock signal Clock2 of the WB / DSP stage, and the operation ends. In this example, the destination register is the register designated by Dx and Dy. Registers that can be designated as Dx are registers X0 and X1 included in the DSP engine 3, and registers that can be designated as Dy are registers Y0 and Y1 included in the DSP engine 3. As described above, in the data read operation command from the memory to the DSP engine 3, the IF, ID, EX, MA,
The operation is completed in the five pipeline stages of WB / DSP. Such parallel data read operation is performed by the C via the buses XAB, XDB and YAB, YDB which are independent of each other.
This is because the PU core 2 can access the X and Y memories 4 to 7.

FIG. 12 shows a time chart of the data writing operation from the DSP engine 3 to the X, Y memories 6 and 7. As an example of a data write operation command from the DSP engine 3 to the X, Y memories 6 and 7, MOVX.W Da,
The operation will be described by taking @Ax MOVY.W Da, @Ay as an example. This instruction is an instruction to transfer the data stored in the register designated by Da to the address stored in the register designated by Ax and Ay.

Instruction fetch and instruction decode operations are shown in FIG.
Since it is the same as 1, the detailed description of that part will be omitted. DS
When executing a data write operation command from the P engine 3 to the X, Y memories 6 and 7, the memory address to be accessed is generated by the CPU core 2. Therefore, the register storing the address to be accessed is accessed in synchronization with the rising timing of the clock signal Clock1 in the EX stage, and the value of the register is output to the internal buses A1 and A2 of the CPU core 2. In this example, the register storing the address to be accessed is the register designated by Ax and Ay. The register that can be designated as Ax is the register A0 included in the CPU core 2.
x, A1x, and registers that can be specified for Ay are CPUs
The registers A0y and A1y included in the core 2. CP
The data output to the internal buses A1 and A2 of the U core 2 are
The address buses XAB, Y are stored in the memory address buffers (MABX, MABY) and are synchronized with the rising timing of the clock signal Clock2 of the EX stage.
It is output to AB.

MA stage clock signal Clock1
The internal register of the DSP engine 3 in which the data to be transferred is stored is accessed in synchronization with the rising timing of the internal bus D1 of the DSP engine 3.
The value of the register is output to D2 and stored in the memory data buffers (MDBX, MDBY). In the case of this example, D that stores the data to be transferred
The internal register of the SP engine 3 becomes the register designated by Da. Registers that can be designated by Da are the registers A0 and A1 included in the DSP engine 3. In synchronization with the rising timing of the clock signal Clock2 of the MA stage, the memory data buffer (MDBX,
The data stored in MDBY) is the data bus XDB, Y
It is output to DB. In the X, Y memories 6 and 7, the addresses output to the address buses XAB and YAB are decoded at the rising timing of the EX stage clock signal Clock2 in the period from the rising of the clock signal Clock1 of the MA stage to the rising of the clock signal Clock2. Performed, clock signal Cl of the MA stage
Next clock signal Clock from the rising edge of ock2
Data access is performed during the rising edge of 1.
Therefore, the data output to the data buses XDB and YDB are written from the rising edge of the clock signal Clock2 of the MA stage. As described above, in the data write operation command from the DSP engine 3 to the X, Y memories 6 and 7,
The operation is completed in four pipeline stages of IF, ID, EX and MA. Such parallel data writing operation is
This is because the CPU core 2 can access the X, Y memories 4 and 6 via mutually independent buses XAB and XDB and TAB and YDB.

FIG. 13 shows a time chart of the data reading operation from the memory to the DSP engine 3. As an example of a data read operation instruction from the memory to the DSP engine 3, MOVS.L @As, Ds will be described as an example of the operation. This instruction is an instruction to transfer the data stored at the address designated by As to the register designated by Ds.

The basic operation is the same as the data reading operation from the X, Y memories 4 to 7 to the DSP engine 3 shown in FIG. The difference between FIG. 11 and FIG. 13 is that the target memory is the X and Y memories 4 to 7 in FIG. 11, so the X bus and the Y bus are used, whereas in FIG. 13, the target memory is supported by the microcomputer 1. It means that the buses IAB and IDB are used because the memory is connected to the space. EX stage clock signal Clock
In synchronization with the rising edge of 1, the register holding the address to be accessed is accessed, and C
The register value is output to the internal bus A1 of the PU core 2. In this example, the register storing the address to be accessed is the register specified by As. As
Registers that can be specified by Re are included in the CPU core 2.
Any register in g. The data output to the internal bus A1 of the CPU core 2 is stored in the address buffer 205.
Stored in the EX stage clock signal Clock2
Address bus IA synchronized with the rising timing of
Output to B. On the other hand, the data output to the internal bus A1 of the CPU core 2 is subjected to address calculation by an arithmetic logic unit (ALU) 213. In this case, the arithmetic logic unit (ALU) 213 performs 0 addition operation. The calculation result is output to the internal bus C1 of the CPU core 2. The calculation result output to the internal bus C1 of the CPU core 2 is stored in the pointer register (in this case, the register designated by As) in synchronization with the rising timing of the clock signal Clock2 of the EX stage. In the memory to be accessed, the address output to the address bus IAB is decoded at the rising timing of the EX stage clock signal Clock2 in the period from the rising of the clock signal Clock1 of the MA stage to the rising of the clock signal Clock2. Data access is performed in the period from the rising of the clock signal Clock2 of the stage to the rising of the next clock signal Clock1. Therefore, the clock signal Clo of the MA stage
Data is output to the data bus IDB from the rising edge of ck2. The data output to the data bus IDB is W
The data is taken into the DSP engine 3 in synchronism with the rising timing of the clock signal Clock1 of the B / DSP stage, and the relevant data is transferred to the internal bus D1 of the DSP engine 3.
Is supplied to. Clock signal C of WB / DSP stage
DSP in synchronization with the rising timing of lock2
The data on the internal bus D1 of the engine 3 is stored in the destination register, and the operation ends. In this example, the destination register is the register designated by Ds. The register that can be designated as Ds is any register in the DSP engine 3. As described above, in the data read operation instruction from the memory to the DSP engine 3, the operation is completed in the five pipeline stages of IF, ID, EX, MA, and WB / DSP.

FIG. 14 shows a time chart of the data writing operation from the DSP engine 3 to the memory. As an example of a data write operation command from the DSP engine 3 to the memory, the operation will be described by taking MOVS.LDs, @As as an example. This instruction is an instruction to transfer the data stored in the register designated by Ds to the address designated by As.

The basic operation is the same as the data writing operation from the DSP engine 3 to the X and Y memories shown in FIG. The difference between FIG. 12 and FIG. 14 is that since the target memory is the X and Y memories in FIG. 12, the buses XAB, XDB and the buses YAB, YDB are used, whereas in FIG. 14, the target memory is a microcomputer. Since the memory is connected to the space supported by 1, the bus IAB, ID
It means that B is used.

In synchronization with the rising timing of the EX stage clock signal Clock1, the register holding the transfer destination address is accessed, and the CPU core 2
The value of the register is output to the internal bus A1. In this example, the register storing the address to be accessed is the register specified by As. The register that can be designated by As is an arbitrary register in the register Reg. Included in the CPU core 2. Internal bus A1 of CPU core 2
The data output to the address buffer 205 is stored in the address buffer 205 and output to the address bus IAB in synchronization with the rising timing of the clock signal Clock2 of the EX stage. On the other hand, the data output to the internal bus A1 of the CPU core 2 is subjected to address calculation by an arithmetic logic unit (ALU) 213. In this case, the arithmetic logic unit (AL
U) 213 performs 0 addition operation. The calculation result is CP
It is output to the internal bus C1 of the U core 2. The calculation result output to the bus C1 of the CPU core 2 is stored in the pointer register (in this case, the register designated by As) in synchronization with the rising timing of the clock signal Clock2 of the EX stage.

MA stage clock signal Clock1
The value of the register inside the DSP engine 3 which stores the data to be transferred is output to the internal bus D1 of the DSP engine 3 and stored in the memory data buffer (MDBI) in synchronization with the rising timing of the. The data stored in the memory data buffer (MDBI) is output to the data bus IDB in synchronization with the rising timing of the clock signal Clock2 of the MA stage. In this example, the register inside the DSP engine 3 which stores the data to be transferred is the register designated as Ds.
The register that can be designated as Ds is any register in the DSP engine 3. In the memory to be accessed,
In the period from the rising of the clock signal Clock1 of the MA stage to the rising of the clock signal Clock2, E
The address output to the address bus IAB is decoded at the rising timing of the X stage clock signal Clock2, and the clock signal Clo of the MA stage is clocked.
Next clock signal Clock1 from the rising edge of ck2
Data access is performed during the rising edge of. Therefore, the data output from the DSP engine 3 is written in the memory at the rising timing of the clock signal Clock2 of the MA stage. As described above, in the data write operation command from the DSP engine 3 to the external memory,
The operation is completed in four pipeline stages of IF, ID, EX and MA.

Next, as an example of the DSP operation instruction, PA
DD Sx, Sy, Du PMUL Se, Sf, D
g MOVX.W @Ax, Dx MOVY.W @
Taking Ay and Dy as an example, the operation will be described with reference to FIG. This instruction adds and multiplies the data stored in the register in the DSP engine 3, and X-RO
This is an instruction to transfer data from the M4, the X-RAM 6, the Y-ROM 5, and the Y-RAM 7 to the DSP engine 3, and is an operation that combines the operations of FIG. 10 and FIG. The operation of instruction fetch and instruction decode is the same as that in FIG. 10, and thus detailed description thereof will be omitted.

When executing a data read operation instruction from the X and Y memories to the DSP engine 3, the CPU core 2 generates the address of the memory to be accessed. Therefore, the register holding the address to be accessed is accessed in synchronization with the rising timing of the clock signal Clock1 in the EX stage, and the value of the register is output to the internal buses A1 and A2 of the CPU core 2. In this example, the register storing the address to be accessed is the register designated by Ax and Ay. Registers that can be specified as Ax are registers A0x and A1x included in the CPU core 2, and registers that can be specified as Ay are C.
The registers A0y and A1y included in the PU core 2.
The data output to the internal buses A1 and A2 of the CPU core 2 are stored in the memory address buffers (MABX and MABY), and are synchronized with the rising timing of the clock signal Clock2 of the EX stage to synchronize with the address bus XA.
It is output to B and YAB. On the other hand, CPU internal buses A1 and A
The data output to 2 is subjected to address calculation by ALU 213 and PAU 212 (in this case, ALU 213 and PAU 212 perform 0 addition calculation), and the result is C.
It is output to the internal buses C1 and C2 of the PU core 2. CP
The calculation result output to the internal buses C1 and C2 of the U core 2 is stored in the pointer register (in this case, the register designated by Ax and Ay) in synchronization with the rising timing of the clock signal Clock2 of the EX stage. In the X and Y memories, the clock signal C of the MA stage
Clock signal Clock2 from the rising edge of clock1
Clock signal Cl of the EX stage during the rising edge of
Address bus XA at the rising edge of ock2
The addresses output to B and YAB are decoded, and data access is performed in the period from the rising of the clock signal Clock2 of the MA stage to the rising of the next clock signal Clock1. Therefore, data is output to the data buses XDB and YDB from the rising of the clock signal Clock2 of the MA stage. The data output to the data buses XDB and YDB is WB / DSP.
D is taken into the DSP engine 3 in synchronization with the rising timing of the clock signal Clock1 of the stage, and D
Data is output to the internal buses D1 and D2 of the SP engine 3. Clock signal Clock of WB / DSP stage
The data on the internal buses D1 and D2 of the DSP engine 3 are stored in the destination register (Distination Reg.) In synchronization with the rising edge of 2, and the operation ends. In this example, the destination register is the register designated by Dx and Dy. Registers that can be specified as Dx are X0, X1 in the DSP engine 3,
The register that can be specified as Dy is Y in the DSP engine 3.
0 and Y1.

In parallel with the above data transfer, DSP arithmetic operation is also performed at the same time. The register storing the source data is accessed in synchronization with the rising timing of the clock signal Clock1 of the WB / DSP stage, and the internal buses A1, A2, B1, of the DSP engine 3 are accessed.
The value of the register is output to B2. In this example, the register storing the source data is the register designated by Sx and Sy in the case of ADD (addition) operation,
In the case of MUL (multiplication) operation, the register is designated by Se and Sf. The registers that can be designated as Sx, Sy, Se and Sf are arbitrary registers inside the DSP engine 3. The data output to the internal buses A1 and B1 of the DSP engine 3 is multiplied by the MAC 304, and the result is output to the internal bus C1 of the DSP engine 3. DS
The data output to the internal buses A2 and B2 of the P engine 3 are subjected to addition operation by the ALU 302, and the result is DS.
It is output to the P engine 3 internal bus C2. The operation result output to the internal buses C1 and C2 of the DSP engine 3 is the clock signal Clock2 of the WB / DSP stage.
It is stored in the destination register in synchronization with the rising timing of. The destination register in this example is the register designated by Du for ADD operation and Dg for MUL operation. The registers that can be designated as Du and Dg are arbitrary registers inside the DSP engine 3.

As described above, the data stored in the register in the DSP engine 3 is added and multiplied, and X
-ROM4 and X-RAM6 and Y-ROM5 and Y-RAM7
From the instruction to the data transfer to the DSP engine 3, the operation is completed in five pipeline stages of IF, ID, EX, MA and WB / DSP.

As a second example of the DSP operation instruction, Inst1: PADD A0, M0, A0 PMUL
A1, X0, A1 MOVX.W @ R4, X1 MO
The operation of VY.W@R6, Y0 Inst2: ADD R8, R9 Inst3: ADD R10, R11 Inst4: ADD R12, R13 will be described with reference to FIG. These four instructions are the address bus IA
This is an example in which different operations are realized in the same clock cycle by using B, XAB, and YAB simultaneously. I
Since the instruction operation from nst1 to Inst4 is the same as that in FIGS. 7 and 15, detailed description thereof will be omitted.

First, in the IF stage of Inst1,
The instruction fetch of st1 is performed. At the time of the ID stage of Inst1, it becomes the IF stage of Inst2.
Instruction fetch is performed.

In the EX stage of Inst1, while performing an address operation for accessing the X and Y memories, Inst2 performs instruction decoding for the ID stage and Inst3 performs instruction fetch for the IF stage. .

In the MA stage of Inst1, the address calculated in the EX stage is output to the address buses XAB and YAB (the timing of actually outputting the address is from the rising timing of the clock signal Clock2 of the EX stage). , Data bus XDB
, And data is fetched from YDB. At this time Ins
At t2, because of the EX stage, the ADD operation of R8 and R9 is performed to complete the operation, and since Inst3 is the ID stage, instruction decoding is performed. Since Inst4 is the IF stage, the address in which Inst4 is stored is output to the address bus IAB. Address bus IAB
The output timing of the clock signal Clock2 is from the rising timing of the clock signal Clock2 half cycle before the IF stage of Inst4. This timing is Inst
The timing is the same as the timing of outputting an address to the address buses XAB and YAB in 1 (the latter half of the EX stage and the first half of the MA stage). That is, the address buses XAB and YAB are used for data transfer,
The address bus IAB is used for instruction fetch. In the microcomputer 1, internal address buses IAB, XAB, YA connected to the CPU core 2 respectively.
Since there are B and internal data buses IDB, XDB, and YDB, it is possible to execute different memory access operations in the same clock cycle using the three types of internal buses.

After that, Inst1 completes the operation by performing DSP operation in the WB / DSP stage,
2 has already completed the operation, and Inst 3 has completed the operation by performing ADD calculation of R10 and R11 because it is the EX stage.
In st4, instruction decoding is performed because of the ID stage.

In the next cycle, only the EX stage of Inst4 is performed, the ADD operation of R12 and R13 is performed, and the operation is completed.

According to this embodiment, the following operational effects are obtained.
The built-in memory is divided into Y memories 5 and 7 and X memories 4 and 6 in consideration of sum of products calculation by the DSP engine 3, and C
The PU core 2 can access the Y memories 5 and 7 and the X memories 4 and 6 in parallel by the internal buses XAB and XDB and the internal buses YAB and YDB, respectively. This allows two data from the internal memories 4-7 to be simultaneously DSP
It is made transferable to the engine 3. Furthermore, internal bus XA
Since the B, XDB and the internal bus buses YAB, YDB are also individualized with the internal buses IAB, IDB which are interfaced to the outside, the CPU core 2 accesses the X memories 4, 6 and the Y memories 5, 7 in parallel. External memory access is also enabled. As described above, the three types of address buses IAB, XAB, and YAB, which are respectively connected to the CPU core 2, are provided.
And because there are data buses IDB, XDB, YDB,
It is possible to execute different memory access operations in the same clock cycle using the three types of internal buses. Therefore, even when a program or data exists in the external memory, it is possible to easily cope with the speedup of the arithmetic processing.

By constructing each of the X memories 4 and 6 and the Y memories 5 and 7 from the RAM and the ROM, the usability of the microcomputer can be further improved.

As described above, the built-in memory is the X memory 4,
6 and Y memories 5 and 7, each of which is provided with a ROM and a RAM.
By using the OM as the program memory, the data memory and the program memory can be separated, two pieces of data are transferred in parallel to the DSP engine 3, and instruction fetch, data transfer, and operation are performed in a parallel pipeline. It can be done efficiently by processing.

CPU core 2 is modulo address output unit 2
By including 00, it is possible to speed up the address generation for the iterative calculation such as the product-sum calculation in the CPU core 2.

As for the CPU instruction, the instruction is assigned to the space in which the most significant 4 bits of the instruction code are "0000" to "1110". The DSP instruction is the highest 4 of the instruction code.
All bits are assigned to "1111". Further, the instruction in which the most significant 6 bits of the instruction code are assigned to the space of “111100” and “111101” is D
Even the SP instruction has a 16-bit length instruction code.
An instruction in which the most significant 6 bits of the instruction code is "111110" is an instruction code having a 32-bit length. No instruction is assigned to the space in which the most significant 6 bits of the instruction code are "111111", which is an unused area. In this way, by providing the above rules for code allocation for instructions of maximum 32 bits, if the most significant 6 bits of the instruction code are decoded, the instruction is a CPU instruction or a DSP of 16 bit length. Command or 32
Whether or not it is a DSP instruction having a bit length can be determined by a decoder having a small logic scale, and it is not always necessary to decode all 32 bits at once.

As described with reference to FIG. 17, after the instruction fetch timing, the unprocessed instruction code data is set in the instruction register 25, and the instruction to be executed at this time is the 16-bit CPU instruction. 1
The upper 16 bits of either the 6-bit DSP instruction or the 32-bit DSP instruction can always be supplied to the first decoding circuit 240.

The code of the A field of the 32-bit DSP instruction is set in the upper area UIR in the instruction register 25 and has the same format as the A field.
The 6-bit DSP instruction is also set in the upper area UIR.
Therefore, in any of them, the CPU core 2 can similarly perform the necessary address calculation and the data path selection required for the data fetch. That is, 16-bit data fetch for executing a 32-bit DSP instruction and 16
The decoding circuits 240 and 241 can be shared for data fetch for executing the bit DSP instruction, and in this respect also, the logic scale of the microcomputer 1 can be reduced.

Although the invention made by the present inventor has been specifically described based on the embodiments, the present invention is not limited to the embodiments and various modifications can be made without departing from the scope of the invention. Yes. For example, C
Identification of the PU instruction, 16-bit DSP instruction, and 32-bit DSP instruction is not limited to using the most significant 6 bits of the instruction, and can be increased or decreased according to the number of instruction codes. Further, the function of shifting the lower 16 bits to the upper part of the instruction register can be replaced with another function. Also, CPU
The number of registers and the types of arithmetic units included in the core and the DSP engine are not limited to those in the above embodiment, and can be changed as appropriate.
Also, the number of memories can be increased without being limited to two. The number of address buses and data buses connected to the memories can be increased according to the number of memories. For example, in addition to the X and Y memories, a new Z
Provide memory. Accordingly, the address bus ZAB is connected between the CPU and the Z memory, and the data bus ZDB is connected between the DSP engine and the Z memory. With such a configuration, not only the data from the X and Y memories are loaded into the DSP engine at the time of multiply-accumulate operation, but also the data which has been processed before the currently executed instruction is transferred to the Z memory circuit via the Z bus. It is possible to write at the same time. Since the calculation data can be fetched and written into the memory with one instruction, the overall throughput of the microcomputer is further improved. INDUSTRIAL APPLICABILITY The present invention is most suitable for use as a device-embedded control microcomputer applied to information compression / expansion processing and filtering processing in mobile communication devices, servo control, image processing in printers, and the like.

[0108]

The effects obtained by the typical ones of the inventions disclosed in the present application will be briefly described as follows.

That is, the built-in memory is divided into a first memory and a second memory in consideration of the sum of products operation by the digital signal processor, and is parallelized by the third bus and the second bus, respectively. Being accessible, the central processing unit can simultaneously transfer two pieces of data from the internal memory to the digital signal processing unit.

Further, since the third bus and the second bus are also separated from the first bus which is externally interfaced, the central processing unit is parallel to the access of the second memory and the first memory. Then, the external memory can be accessed.

As described above, since there are the first to third types of address buses and data buses connected to the central processing unit respectively, different memories can be used in the same clock cycle by using the three types of internal buses. Since the access operation can be executed, it is possible to easily cope with the case where the program or the data exists in the external memory and realize the high-speed operation processing.

Further, the built-in memory includes the first memory and the second memory.
Of memory, and each memory is a ROM
By providing the RAM and the RAM, and using the RAM as the data memory and the ROM as the program memory, the data memory and the program memory can be separated from each other, and two pieces of data are transferred in parallel to the digital signal processing unit. Fetch, data transfer, and operation can be efficiently performed by parallel pipeline processing.

Therefore, the digital signal processing unit and the central processing unit are combined into one LS.
When mounted on I, high speed digital signal processing can be realized.

For an instruction in which a CPU instruction and a DSP instruction are mixed, a part of the instruction code is decoded to determine whether the instruction is a CPU instruction or a 16-bit DSP.
By assigning an instruction code so that it can be identified whether it is an instruction or a 32-bit DSP instruction, the type of the instruction can be determined by a decoder of a small logical scale.
It is not always necessary to decode all 32 bits at once. Therefore, when the digital signal processing unit is mounted on one LSI together with the central processing unit, it is possible to suppress an increase in the physical scale as much as possible.

As the instruction format of the DSP instruction, the first code area (16-bit DSP exemplified in FIG. 18) that defines the data transfer with the digital signal processing unit to the central processing unit is executed.
An instruction of the first format having an instruction bit 9 to bit 0) and a second code area of the same format as the first code area (A field of a 32-bit DSP instruction exemplified in FIGS. 20 and 21) ), And a third code area (32-bit illustrated in FIG. 20 and FIG. 21) that specifies the arithmetic processing using the transfer data defined by the second code area to the digital signal processing unit. By adopting the second format instruction having the B field of the DSP instruction), the means for executing the respective instructions of the first and second formats is provided for the first code area and the second code area. A decoding means having a common decoding logic can be adopted, and also in this respect, the logic scale of the microcomputer can be reduced.

[Brief description of drawings]

FIG. 1 is an overall block diagram of a microcomputer according to an embodiment of the present invention.

FIG. 2 is an example address map of a microcomputer.

FIG. 3 is a CPU showing a modulo address output section in detail.
It is a block diagram of a core.

FIG. 4 is a block diagram of an example of a DSP engine.

FIG. 5 is an explanatory diagram illustrating an example of a command format and a command code of a microcomputer.

FIG. 6 is a block diagram showing a connection configuration of a decoder of a CPU core and a decoder of a DSP engine.

FIG. 7 is an execution time chart of an ALU operation instruction inside a CPU core.

FIG. 8 is an execution time chart of an instruction for reading data from a memory to a CPU core.

FIG. 9 is an execution time chart of an instruction to write data from the CPU core to the memory.

FIG. 10 is an example time chart when executing a DSP instruction.

FIG. 11 is an execution time chart of an instruction for reading data from an X, Y memory to a DSP engine.

FIG. 12 is an execution time chart of an instruction for writing data from the DSP engine to the X and Y memories.

FIG. 13 is an execution time chart of an instruction for reading data from a memory to a DSP engine.

FIG. 14 is an execution time chart of an instruction for writing data from the DSP engine to the memory.

FIG. 15 is an execution time chart of an example of a DSP operation instruction.

FIG. 16 is an example time chart when the DSP operation instructions are continuously executed.

FIG. 17 is a block diagram showing another embodiment corresponding to FIG.

FIG. 18: Built-in memory of microcomputer and DSP
FIG. 6 is an instruction format diagram showing a code of a 16-bit DSP instruction that defines data transfer with the internal register of the engine 3.

FIG. 19: External memory and DSP of microcomputer
FIG. 6 is an instruction format diagram showing a code of a 16-bit DSP instruction that defines data transfer with the internal register of the engine 3.

FIG. 20 is an instruction format diagram showing a code of a field of a 32-bit DSP instruction and a mnemonic corresponding to the code of the field.

FIG. 21 is an instruction format diagram showing a code of a field of a 32-bit DSP instruction and a mnemonic corresponding to the code of the field.

[Explanation of symbols]

1 microcomputer 2 CPU core (Central processing unit) 20 DSP control signal 24 decoder 240 First Decoding Circuit 241 second decoding circuit 242 code conversion circuit 243 CPU decode signal 244 DSP decode signal 245 code conversion control signal 247 CPU control signal 25 instruction register 250,251 Instruction prefetch buffer 200 Modulo address output section 206,207 memory address buffer 212 Address calculator 213 Arithmetic logic operation unit 214 Modulo Start Address Register 215 Modulo End Address Register 216, 226 Modulo address register 3 DSP engine (digital signal processing unit) 34 Decoder 302 arithmetic logic unit 304 multiplier 309, 310, 311 memory data buffer 4 X-ROM (second memory) 5 Y-ROM (first memory) 6 X-RAM (second memory) 7 Y-RAM (first memory) 12 External memory interface

   ─────────────────────────────────────────────────── ─── Continued front page    (72) Inventor Hironobu Hasegawa             5-20-1 Kamimizuhonmachi, Kodaira-shi, Tokyo Stock             Ceremony Company Hitachi Semiconductor Division (72) Inventor Toru Maji             5-20-1 Kamimizuhonmachi, Kodaira-shi, Tokyo Stock             Ceremony Company Hitachi Semiconductor Division (72) Inventor Takaki Noguchi             5-20-1 Kamimizuhonmachi, Kodaira-shi, Tokyo Stock             Ceremony Company Hitachi Semiconductor Division (72) Inventor Yasushi Akao             5-20-1 Kamimizuhonmachi, Kodaira-shi, Tokyo Stock             Ceremony Company Hitachi Semiconductor Division (72) Inventor Shiro Baba             5-20-1 Kamimizuhonmachi, Kodaira-shi, Tokyo Stock             Ceremony Company Hitachi Semiconductor Division F-term (reference) 5B013 DD03                 5B033 AA14 BA01 BA03 BB03 BF00                       DC08                 5B062 CC06 DD10

Claims (17)

[Claims] 1. A CPU, a memory for access control by the CPU, a data bus for transferring data between the memory and the CPU, and a DSP connected to the data bus. The CPU has a 16-bit fixed-length CPU instruction, an instruction register for fetching a 16-bit or 32-bit DSP instruction for the DSP, and a part of the instruction fetched by the instruction register. A first control signal for controlling the operation of the CPU and a second control signal for controlling the operation of the DSP according to the identification result. And a decoder for generating the decoder, wherein the DSP includes a decoder for decoding the second control signal received from the CPU. Lee Black computer. 2. The decoder in the CPU according to claim 1, wherein the decoder in the higher order 6 of the instruction register.
A microdecoder having a first decode circuit for decoding bits and outputting a CPU decode signal and a DSP decode signal, and a code conversion circuit for outputting a signal obtained by encoding the lower 16 bits of the instruction register. Computer. 3. The code conversion circuit according to claim 2, wherein when the first decode circuit identifies the 32-bit DSP instruction,
A signal obtained by encoding the lower 16 bits of the instruction register is output, and when an instruction other than that is identified, a code indicating that the output is invalid is output, and the DSP decode signal and the output of the code conversion circuit are output. Is used as the second control signal. 4. A central processing unit, a digital signal processing unit, and an internal bus commonly connected to the central processing unit and the digital signal processing unit, wherein the central processing unit is the digital signal processing unit. A first format instruction of a first length having a first code area for defining data transfer between the central processing unit and a second code area having the same bit length as the first code area; Execution of a second length second format instruction longer than the first length having a third code area that defines for the digital signal processor the arithmetic processing using the transfer data defined by the second code area. A microcomputer provided with execution control means for performing the operation. 5. The method according to claim 4, wherein each of the first format instruction and the second format instruction has a fourth code area, and the fourth code area has the first format instruction and the second format. A microcomputer indicating that the instruction is in the first format or the second format. 6. The execution control unit according to claim 5, wherein the execution control unit includes an instruction register commonly used for the first format instruction and the second format instruction, and the first instruction included in the instruction fetched by the instruction register. And a fourth code area, or decoding means for decoding the second and fourth code areas, and an execution circuit for performing address calculation and data transfer control according to the decoding result. Computer. 7. The instruction register according to claim 6, wherein the instruction register holds an upper area shared by holding the first and fourth code areas or the second and fourth code areas and a third area holding the third code area. The decoding means outputs a control signal indicating that the instruction register holds the second format instruction based on the decoding result of the fourth code area, and the control section A microcomputer comprising means for supplying code data in the third code area from the lower area to the digital signal processing device based on a signal. 8. A CPU, a memory accessed by the CPU, a data bus connected to the memory and the CPU, and a DSP connectable to the CPU, wherein the CPU is connected to the data bus. And an instruction register capable of fetching an instruction supplied from the memory via the data bus, and a decoder connected to the instruction register, the instruction being supplied via the data bus. C above
A first instruction of a first length for a PU and a second instruction of a first length or a second length longer than the first length for the DSP, wherein the decoder is fetched by the instruction register Decoding a part of a plurality of bits of the instruction to identify whether the instruction fetched in the instruction register is the first instruction or the second instruction, and the decoder uses the instruction as the first instruction. When identifying the instruction fetched by the register, the CPU
A second control signal for controlling the DSP when generating a first control signal for controlling the second instruction and identifying an instruction fetched by the instruction register as the second instruction. A microcomputer having a decoding unit for decoding the second control signal. 9. The instruction register according to claim 8, wherein the instruction register has a second length including an upper area of the first length and a lower area of the first length, and the decoder is the upper area of the instruction register. And a code conversion circuit for decoding the instruction code fetched by the first control signal and the decoded signal, and the code conversion circuit is configured so that the decoder converts an instruction fetched by the instruction register. When identifying the instruction as the second instruction, a signal obtained by compressing the instruction code fetched in the lower area of the instruction register is output, and the decoder fetches the instruction fetched by the instruction register as the second instruction. When discriminating as an instruction other than an instruction, a code indicating that the output signal is invalid is output, and the decode signal and the code conversion are performed. The output signal of the road is,
A data processing device used as the second control signal. 10. A data processing method for a microcomputer having at least two instruction types, the data processing method comprising: a first step of generating a first instruction address relating to a first instruction; and the first instruction address. The second step of fetching the first instruction relating to the above, and the third step of decoding the first part of the first instruction and determining whether the first instruction is a DSP type or a CPU type; And a fourth step of generating the CPU type control signal if the first instruction is the CPU type. 11. The method according to claim 10, wherein the third step includes a step of determining whether the first instruction has a first size or a second size, and the first size is the second size. A data processing method characterized by being larger than a size. 12. The data processing method according to claim 11, further comprising a step of transcoding a second portion of the first instruction when the first instruction has the first size. Data processing method. 13. The data processing method according to claim 11, further comprising a step of moving data in the instruction register from a lower side to an upper side when the first instruction has the second size. A data processing method characterized by the above. 14. The data processing method according to claim 12 or 13, wherein the first size is 32 bits and the second size is 16 bits. 15. The method according to claim 14, wherein the first instruction is the DSP type instruction,
The data processing method, wherein the first size is 32 bits and the second size is 16 bits. 16. The data processing method according to claim 14, further comprising the step of generating a DSP control signal for operating a DSP engine when the first instruction is the DSP type instruction. A data processing method characterized by. 17. A microcomputer having a decoder for discriminating between a 16-bit instruction and a 32-bit instruction.