JP2003130926A - Semiconductor tester - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor tester provided with a timing setting change-over means which enables device tests to be performed continuously being kept intact, without transferring a program, when the device tests are performed splitting devices into a plurality, and only conditions for timing setting are different. SOLUTION: This tester concerns a semiconductor tester provided with a timing setting memory TSM which stores a predetermined plurality of timing settings for specifying the timing edges of generated pulses to be used for testing devices to be tested. The semiconductor tester is also provided with a TS number resource selection control means which supplies a TS number value from a TS number resource different from TS number data TSD generated by a pattern generator PG, to the memory TSM.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor test apparatus having a structure for generating a test waveform or the like (application waveform, strobe signal, etc.) generated for testing a device under test (DUT) under a predetermined timing condition. . In particular, a semiconductor that includes a unit that can generate a test waveform under a different timing condition independently of the timing condition stored in the pattern memory of the pattern generator, and can share pattern programs with different timing conditions. Regarding test equipment.

[0002]

2. Description of the Related Art As a test waveform generated by a semiconductor test device for testing a DUT, for example, a driver waveform of several hundred channels or more applied to the DUT or a response signal from the DUT is received and compared at a predetermined timing. There are strobe signals of several hundred channels or more. These pulses are generated as pulses in which each edge is prescribed. Each of the leading edge / trailing edge is individually output as a pulse waveform delayed by a predetermined time based on a predetermined timing condition (timing set: TS). FIG. 1 is a conceptual configuration diagram of a main part of a semiconductor test apparatus according to the present application. This component includes a memory device 100, a pattern generator PG, a test cycle generator 10, a timing generator / waveform shaper TGFC, pin electronics PE, a logical comparator DC, and the like. Here, since the semiconductor test apparatus is publicly known and well known in the art, other signals and constituent elements, and detailed description thereof will be omitted except for the main part of the present application. Therefore, the pin electronics PE and the logical comparator D
The description of C is omitted.

The storage device 100 is a hard disk device having a capacity of hundreds of gigabytes, and although not shown, a high-speed semiconductor memory having a capacity of hundreds of megabytes, for example, an SBM (Super Buffer M).
emory). In order to test the device, the SBM is larger than the memory capacity of the pattern program memory PPM included in the PG, and stores the next-time pattern program 120 for a plurality of times in a predetermined divided unit and stands by. Then, based on the request from the PG, the next next-time pattern program 120 is transferred to the pattern program memory PPM at an extremely high speed. This transfer time is, for example, several seconds or more, depending on the number of transfer words and the system configuration. During the period from the start of the transfer to the completion of the transfer, the device test is suspended, so that the throughput of the device test is lowered. Further, if the reading from the hard disk drive to the SBM is not completed, this reading time is also added, and the throughput of the device test is further reduced.

A pattern generator PG (Pattern Generato)
r) is different between the memory tester for memory device test and the logic tester for logic device test. Here, the test pattern PAT1 and the expected value pattern PAT2 are generated in one memory tester by the internal ALPG.
The generated data calculated and generated by the (Algorithmic Pattern Generator) is used as the test pattern PAT1 and the expected value pattern PAT2. However, when the random expected value pattern PAT2 is required, the stored data stored in the dedicated expected value storage memory (corresponding to the pattern program memory PPM in FIG. 2) is the expected value pattern PAT.
Applied as 2. Here, it is assumed that a dedicated expected value storage memory is applied. In the other logic tester, the test pattern PA is stored in a large-capacity test pattern storage memory (corresponding to the pattern program memory PPM in FIG. 2).
T1 and expected value pattern PAT2 are stored and used. The PG executes a predetermined program control command, accesses the pattern program memory PPM by the program address corresponding to the PG, reads the test period pattern RD1, the TS number data TSD, the test pattern PAT1, and the expected value pattern. Output PAT2 and others. In addition, the pattern generation cycle is the test cycle generation unit 10
Are generated in a cycle based on the rate clock RTCLK.

Next, the pattern program memory P of FIG.
The stored contents of the pattern program and timing set when the program is transferred to the PM four times will be described. This is one timing set (TS number) for each tester channel in the pattern program of 4 times.
This is a simple case in which device tests are performed by sequentially applying only those different in A, B, C, and D. This is often used when ranking DUTs by characteristics. First
First, the program is the pattern program memory PPM.
The pattern program A and the timing set A are transferred. Second
As the program, the next pattern program A and timing set B are transferred from the next pattern program 120. Here, the pattern program A side has the same contents as before. Thereafter, similarly, in the third program, the next pattern program A and the timing set C are transferred from the next pattern program 120, and in the fourth program, the next pattern program A and the timing set D are transferred. Here again, the contents on the pattern program A side are the same as before. According to this, in order to change the timing set to A, B, C, D, it is necessary to transfer the pattern program A, which does not need to be changed, to the pattern program memory PPM. Along with this, a transfer time is required to transfer the pattern program.

Next, a flow chart of the device test corresponding to FIG. 2 will be described with reference to FIG. Step S1 is
Transfer the timing set used in the whole at once. Here, the delay amount data for each individual tester channel corresponding to the timing sets A, B, C, D is written in the timing set memory TSM of all the tester channels. A step S2 transfers the first pattern program for the first test. That is, the pattern program A and the timing set A shown in FIG. 2 are transferred. It takes, for example, several tens of seconds to transfer several tens of M words.
This period is the suspension period A because the device test is not actually executed. A step S3 executes a predetermined device test based on the transferred pattern program. That is, it is a test execution period B in which a device test is actually executed, and is an execution time of, for example, several seconds to several tens of seconds. Step S4 is similar to step S2, and transfers the next second pattern program for the second test. This period also becomes the device test suspension period A. Step S5 is the same as step S3,
It is the test implementation period B of the next second test. The subsequent steps S6 and S8 are similar to step S2, and the next pattern program is transferred. This period also
This is the device test suspension period A. Steps S7 and S9 are also the same as step S3, and are the next test implementation period B. From the above description of FIGS. 2 and 3, it is understood that the suspension period A occurs every time the next program is transferred. The larger the number of the suspension periods A, the longer the time required for the device test to be completed. Further, it is also a factor of lowering the throughput. As described above, even if only the timing sets A, B, C, and D are different, it is necessary to transfer the next timing set, and as a result, the pause period A is required.

Returning to FIG. 1, the test cycle generator 10 generates a test cycle that can be changed on the fly. That is, when the test cycle pattern RD1 is received, a rate clock RTCLK obtained by dividing the fixed reference clock CLK by a predetermined frequency is generated so as to have a specified cycle time based on the test cycle pattern RD1.
Supply to G and TGFC. Further, the fractional time information FD, which is the fractional time between the specified cycle time and the reference clock CLK.
2 supplies to TGFC.

Timing generation / waveform shaping section TGFC (Ti
ming generator format control) is for generating driver pulses DRP of a predetermined plurality of channels, for example, 1024 channels to be applied to the DUT, and strobe signals STB3 of a predetermined plurality of channels to be supplied to DC.
The internal elements according to the present application include a timing set memory TSM having a predetermined number of channels and a clock generator 20.

The timing set memory TSM is a memory for storing a plurality of types of timing set data (delay amount data) which defines the timing of the edge of the generated pulse. For example, when the TS number data TSD has a 10-bit width, it is 1024. With types. The TS number data TSD which is the TS number from the PG is received at the address input terminal a, and the timing delay data DL5 read based on this is supplied to the clock generation unit 20.

Here, when writing the timing data to the timing set memory TSM, initially, the timing data (four types of TS numbers A to D in the case of FIG. 2) used in all the pattern programs are collectively written. Written. By the way, the TS number data TSD designating the TS number is integrally stored in the pattern program memory PPM as a part of the pattern program.
Therefore, the test pattern PAT1 and the expected value pattern PA
Even if there is a device test in which T2 is the same and only the TS number data TSD is different, it is necessary to apply another pattern program. As a result, the capacity of the entire pattern program for device testing increases. Along with this increase, there is a drawback that the number of next-time pattern programs 120 that are divided into a plurality of pieces and increase.

The clock generator 20 generates and outputs a pulse that is actually delayed at a predetermined timing based on a predetermined waveform shaping condition, and outputs the fractional time information F.
D2 and the timing delay data DL5 are added together to obtain a final delay amount to which a predetermined skew correction amount is added, and a variable delay means VD1 is provided to generate a delay pulse delayed by a predetermined amount based on the rate clock RTCLK. . When one of the driver pulses DRP is output, the driver pulse DRP having the leading edge and the trailing edge shaped by the delay pulse is output so that the predetermined waveform shaping is performed based on the condition of the received test pattern PAT1. When outputting the strobe signal STB3, the delay pulse is output as a strobe pulse based on the condition of the received test pattern PAT1.

[0012]

As described above, in the prior art, even if the timing set is different from the timing sets A, B, C and D as shown in FIG. In order to transfer a program including the above, a pause period A is required as shown in FIG. As a result, there is a problem that the capacity of the entire pattern program for device testing increases. In addition, it takes time to complete the device test,
It is also a factor that reduces the throughput. Therefore, the problem to be solved by the present invention is to divide the device test into a plurality of lines, and if only the conditions of the timing set are different, continue the device test without transferring the program. It is an object of the present invention to provide a semiconductor test apparatus including a timing set switching unit that can be implemented. Further, when one pattern program is divided into a plurality of parts and only the conditions of the timing set are different among them, the divided pattern programs are shared as one, and a timing set switching means for switching the timing set in a predetermined manner is provided. It is to provide a semiconductor test device provided with.

[0013]

A first solution will be described.
In order to solve the above problems, in a semiconductor test apparatus including a timing set memory TSM that stores a predetermined plurality of timing sets that define timing edges of generated pulses used for testing a device under test, the pattern generator PG is Other than the TS number data TSD for selecting and designating the timing set stored together with the pattern data of
TS number resource selection control means capable of supplying the TS number value from the S number resource to the timing set memory TSM (for example, TS selector 3, TS register R1, and TS
The semiconductor test apparatus is provided with a selection control register R2). According to the above invention, when the device test is performed by dividing into a plurality of lines and only the conditions of the timing set are different, the timing set switching means that can continuously perform the device test without transferring the program. A semiconductor test apparatus including

Next, the second solving means will be shown. In order to solve the above problems, a timing set memory TSM that stores a plurality of predetermined timing sets that define timing edges of generated pulses used for testing a device under test.
In a semiconductor test apparatus including a pattern generator PG
The TS number resource selection control means (for example, the TS selector 3) that can supply the TS number value from the TS number resource different from the TS number data TSD for selecting and specifying the timing set generated from the timing set memory TSM.
And a TS register R1 and a TS selection control register R2).

Next, a third solving means will be shown. In order to solve the above problems, a timing set memory TSM that stores a plurality of predetermined timing sets that define timing edges of generated pulses used for testing a device under test.
A semiconductor test device that supplies a TS number value for selecting and designating a predetermined timing set from the pattern generator PG to the timing set memory TSM, and generates and outputs a generated pulse at a predetermined timing based on the TS number value. 1, the TS number data TSD supplied from the pattern generator PG is set to T in the TS number normal supply mode.
The TS number value is supplied to the timing set memory TSM as the S number value, and secondly, in the TS number independent supply mode, the TS number value from the TS number resource (for example, the TS register R1) different from the TS number data TSD is set to the timing set. TS number resource selection control means that can be supplied to the memory TSM (for example, TS selector 3 and TS register R
1 and a TS selection control register R2).

Next, a fourth solving means will be shown. In order to solve the above problems, a timing set memory TSM that stores a plurality of predetermined timing sets that define timing edges of generated pulses used for testing a device under test.
In a semiconductor test apparatus for supplying a TS number value for selecting and designating a predetermined timing set from the pattern generator PG to the timing set memory TSM, and generating and outputting a generated pulse at a predetermined timing based on the TS number value. TS number data T for selecting and designating a timing set that is pattern data generated from the generator PG
The TS number value of SD is used as the timing set memory TSM.
A normal operation mode for supplying to the timing set memory TSM is called a TS number normal supply mode, and a TS number value independent of the TS number data TSD is supplied to the timing set memory TSM from another system different from the TS number data TSD. When the mode is called the TS number independent supply mode, the above T
In the S number normal supply mode, the TS number data TSD supplied from the pattern generator PG is supplied to the timing set memory TSM as the TS number value, and the TS
In the number independent supply mode, the above TS number data TS
TS number resource selection control means (for example, TS selector 3, TS register R1, and TS selection control register R2) capable of supplying a TS number value from a TS number resource different from D to the timing set memory TSM. There is a semiconductor test equipment that does.

Next, a fifth solving means will be shown. The fourth here
The figure shows the solution according to the invention. A pattern program memory PPM for storing a program for testing a device under test (DUT) is provided, and the pattern program memory PPM generates pattern data for generating a test waveform or the like (applied waveform or strobe signal) for testing the DUT, and Timing generation / waveform is generated by generating TS number data TSD together with other pattern data for selecting and designating a predetermined TS number from a plurality of predetermined timing set numbers (TS numbers) that define the timing edges of the generated pulses. The timing generator / waveform shaper TGF is provided with a pattern generator PG supplied to the shaper TGFC.
C has a timing set memory TSM for storing a timing set therein, and the timing set memory T
The SM receives as input a predetermined TS number input signal for selecting and specifying the TS number value of the timing set, and generates a timing edge generation pulse (for example, strobe) delayed by a predetermined time based on the timing set selected and specified by the TS number input signal. Signal STB3) is generated and output, or a generated pulse whose waveform is shaped into a predetermined test waveform at a timing edge delayed by a predetermined amount (for example, driver pulse DRP)
In a semiconductor test apparatus having a configuration for outputting a pattern, TS which is pattern data generated from the pattern generator PG
A normal operation mode for supplying the TS number value of the number data TSD to the timing set memory TSM is called a TS number normal supply mode, and is independent of the TS number data TSD from another system different from the TS number data TSD. When the operation mode for supplying the TS number value to the timing set memory TSM is called the TS number independent supply mode, the TS number data TSD supplied from the pattern generator PG in the TS number normal supply mode is TS.
It is supplied to the timing set memory TSM as a number value, and in the TS number independent supply mode, a TS from a TS number resource different from the TS number data TSD is supplied.
There is a semiconductor test apparatus including a TS number resource selection control means (for example, a TS selector 3, a TS register R1, and a TS selection control register R2) capable of supplying a number value to the timing set memory TSM.

Next, a sixth solving means will be shown. The fourth here
The figure shows the solution according to the invention. One aspect of the TS number resource selection control means includes a TS switching means, a TS selection mode register, a TS number value storage means, and a TS number designating means. In the supply mode, the TS generated from the pattern program memory PPM of the PG
Number data TSD is selected and supplied to the timing set memory TSM, and secondly, in the TS number independent supply mode, the TS number value output from the TS number value storage means is supplied to the timing set memory TSM ( For example, the TS selector 3), and the TS selection mode register controls switching of the operation mode of the TS number normal supply mode or the TS number independent supply mode (for example, the selection control signal R2s of the TS selection control register R2).
a), wherein the TS number value storage means is a storage device (for example, TS register R1) having at least a storage capacity capable of storing a plurality of TS number values applied in the test implementation of the DUT, and the TS number Based on a TS control program (for example, main program PRO1) capable of controlling the designation of the TS number value, the designating means corresponds to the execution of the device test among the TS number values stored in the TS number value storing means. It is a register (for example, the TS selection signal R2sb of the TS selection control register R2) that receives and holds a control signal for selectively designating a number value, and the above-mentioned semiconductor test device is provided with the above.

Next, a seventh means for solving the problems will be described. 8th here
The figure shows the solution according to the invention. One aspect of the above-mentioned TS number resource selection control means includes a TS number conversion means and a TS number designating means, and the TS number conversion means specifies a plurality of TS number values to be applied to a pattern program for test execution of a DUT. It is a memory (for example, address conversion means 50) for storing, and the address input end of the memory is divided into a first address input end a1 and a second address input end a2, and one of the first address input ends a1 has A predetermined number of bits or the total number of bits of the TS number data TSD is input, and a switching signal (for example, a TS selection signal of the TS selection control register R2) output from the TS number designating means is input to the other second address input terminal a2. R2sb)
Is input, and based on this, the converted TS number value converted from the TS number conversion means to a predetermined TS number value (for example, TS
The converted data 50s) is read and output.
The TS number designating means converts the TS number values stored in the TS number converting means into the TS number values to be applied by the pattern program, so that the TS number
A TS number switching control signal based on a TS control program capable of controlling the designation of the number value is provided, for example, on a tester bus TBU.
A register for receiving and latching via S (eg TS
It is the TS selection signal R2sb) of the selection control register R2, and there is the above-mentioned semiconductor test device characterized by comprising the above. As a result, even when a plurality of timing sets are randomly present in one pattern program, it is possible to apply a subdivided divided pattern program having different TS number values as a shared pattern, and the on-the-fly execution is possible. It will be possible.

Next, an eighth solution means will be shown. 6th here
The figure shows the solution according to the invention. When a pattern program having only different TS number values is called a shared pattern, one aspect of the TS control program is as follows.
The converted TS selected and output by the TS number conversion means immediately before execution of the shared pattern that appears a plurality of times
There is the above-mentioned semiconductor testing device characterized in that the TS number designating means is controlled in a predetermined manner so that the number value becomes the TS number value applied in the common pattern.

Next, the ninth solving means will be described. The fifth here
The figure shows the solution according to the invention. In the pattern program stored in the pattern program memory PPM of the pattern generator PG, one mode of the common pattern is a pattern program in which at least two consecutive TS number values are different from each other. There is a device.

Next, a tenth solving means will be described. Here, FIG. 5 shows a solving means according to the present invention. In the pattern program stored in the pattern program memory PPM of the pattern generator PG, when there is a condition that the common pattern is transferred and stored in the pattern program memory PPM at least twice in succession only in the TS number value. Then, this is applied as a shared pattern to be transferred to and stored in the pattern program memory PPM once, and the main program PRO1 is additionally provided in the pattern program, and the TS number value is sequentially specified based on the main program PRO1. Then, there is the above-mentioned semiconductor test device characterized in that one shared pattern is called by a subroutine and executed.

Next, the eleventh solving means will be shown. Here, FIG. 10 shows a solving means according to the present invention. In the pattern program stored in the pattern program memory PPM of the pattern generator PG, one aspect of the shared pattern is that the shared pattern is divided into pattern program units having different TS number values. There is a device.

Next, a twelfth solving means will be shown. Here, FIG. 10 shows a solving means according to the present invention. In the pattern program stored in the pattern program memory PPM of the pattern generator PG, the common pattern is divided into units applicable as the common pattern, and the divided common pattern is sequentially switched to a predetermined TS number value. Then, the above-mentioned semiconductor test apparatus is characterized in that the main side program PRO1 for calling the divided shared pattern as a subroutine is stored in the pattern program memory PPM in a predetermined manner.

If desired, the means of the present invention may be appropriately combined with the respective element means of the above-mentioned solving means to form other practical constituent means. Further, although the reference numerals given to the above respective elements correspond to the reference numerals shown in the embodiments of the present invention and the like, the present invention is not limited to this, and constituent means to which other practical equivalents are applied. Also good.

[0026]

BEST MODE FOR CARRYING OUT THE INVENTION The present invention will be described below with reference to FIGS. 4, 5, 6 and 7. The elements corresponding to those of the conventional configuration are designated by the same reference numerals, and the description of the overlapping portions will be omitted.

FIG. 4 is a conceptual configuration diagram of a main part of the semiconductor test apparatus of the present invention according to the present application. The different components of the present invention are
In the internal configuration of the timing generation / waveform shaping unit TGFC, the TS selection control register R2 and the TS register R1
And a TS selector 3. Here, it is assumed that the TS number data TSD has a 10-bit width.

The TS selection control register R2 is a 3-bit wide register, and the setting contents can be changed from the tester bus TBUS at any time. The PG program has the PR shown in FIG.
As indicated by O1, a control command capable of setting and controlling the TS selection control register R2 is described. This description can be as small as a few words. This allows the tester bus T
The setting conditions can be changed via BUS. The time required to change this setting is several microseconds. Of the 3-bit register output, the 1-bit select control signal R2sa is supplied to the select input terminal s of the TS selector 3. The 2-bit TS selection signal R2sb is supplied to the TS register R1.

The TS register R1 is a memory or a register having a width of 10 bits and 4 words. The TS number value R1s selected by the 2-bit TS selection signal R2sb from the TS selection control register R2 is transferred to the B of the TS selector 3.
Supply to the input terminal. Prior to starting the device test, the TS values corresponding to the TS numbers A to D to be used are set in the registers.

The TS selector 3 is a 2-input 1-output type multiplexer, and has the select control signal R2sa.
Is "0", the TS number data TSD from the PG is output as the TS number data TSDx so that the existing program can be applied. On the other hand, when the select control signal R2sa is "1", the new program corresponding to the present invention is applied, and the TS register R1 is applied.
The TS number value R1s based on is output as the TS number data TSDx.

According to the above-mentioned configuration of the invention, the TS number data TSDx supplied to the timing set memory TSM is P
By providing the constituent means that can be changed at any time regardless of the timing sets A to D stored in G, in the example shown in FIG.
This program has the advantage that it can be tested. Therefore, the overall program capacity can be significantly reduced. Further, the number of device test suspension periods A shown in FIG. 3 is also reduced from four to one, and as a result, there is an advantage that the device test throughput can be significantly improved.

Next, the procedure will be described with reference to the conceptual diagram of the shared pattern program shared in one in FIG. 5, the flowchart in FIG. 6, and the description content of the main side program PRO1 in FIG. In the actual application, firstly, the main program PRO1 corresponding to FIG. 7 is used as the pattern program.
Is described, and the sub-side program PRO2 is called from now on. Secondly, the sub-program PRO2 is divided into a main program and a pattern program, and the main program side calls the sub-program PRO2 by a subroutine such as "MEAS MPAT". There are forms.

In the present invention, it is assumed that four different timing sets A to D are sequentially executed and tested on all the tester channels by one shared pattern program shown in FIG. The shared pattern program includes a main-side program PRO1 and a sub-side program PRO2. One side main program PR
O1 is a program of about several words as shown in the principle program description example of FIG. The other sub-side program PRO2 is a pattern program A that is commonly applied, and the timing set portion therein is not used. Of course, the conventional second to fourth programs are unnecessary.

Next, the flowchart of FIG. 6 will be described together with a description example of the main program shown in FIG. Step S1 is the same as the conventional one and collectively transfers the timing sets used throughout. Furthermore, T shown in FIG.
In order to specify the timing sets A to D in the S register R1, four TS number values are written in advance.

In step S21, the shared pattern program is loaded from the storage device 100 into the pattern program memory PP.
Transfer to M. This period is a suspension period because the device test is not actually executed.

A step S22 writes the setting data for selecting and designating the timing set A into the TS selection control register R2 via the tester bus TBUS. Of course, TS
The selector 3 is selected on the TS register R1 side. This execution time is only a few microseconds. As shown in Fig. 7, "SET TS
The description of "A" corresponds to this. In step 23, the first test is executed based on the shared pattern program and the timing set A selected and designated. The description of the first "CALL PAT1" shown in FIG. 7 corresponds to this, and the sub-side program PRO2 is called as a subroutine. Eventually, when the execution by the sub-side program PRO2 is completed, the process returns to the calling source. This period is the test execution period B in which the device test is actually performed.

Step 24 is a TS selection control register R
The setting data for selecting and designating the next timing set B is written in 2. This execution time is only a few microseconds. The description of “SET TS B” shown in FIG. 7 corresponds to this. Step 25 is similar to step 23, and the second test is executed based on the shared pattern program and the timing set B selected and designated. The description of the second “CALL PAT 1” shown in FIG. 7 corresponds to this. During this period,
It is a test execution period B in which a device test is actually executed.

Step 26 is a TS selection control register R
The setting data for selecting and designating the next timing set C is written in 2. This execution time is only a few microseconds. The description of “SET TS C” shown in FIG. 7 corresponds to this. Step 27 is the same as step 23, and the third test is executed based on the shared pattern program and the timing set C selected and designated. The description of the third "CALL PAT 1" shown in FIG. 7 corresponds to this. During this period,
It is a test execution period B in which a device test is actually executed.

Step 28 is a TS selection control register R
The setting data for selecting and designating the next timing set D is written in 2. This execution time is only a few microseconds. The description of “SET TS D” shown in FIG. 7 corresponds to this. Step 29 is the same as step 23, and the fourth test is executed based on the shared pattern program and the timing set D selected and designated. The description of the fourth “CALL PAT 1” shown in FIG. 7 corresponds to this. During this period,
It is a test execution period B in which a device test is actually executed.

As shown in the flow chart of FIG. 6, according to the configuration of the above-described invention, the number of times of transferring the pattern program can be reduced to one in the present invention from four in the conventional case. As a result, first, the suspension period A is reduced from four times to one time, and as a result, a great advantage that the throughput of the device test can be significantly improved is obtained. Further, there is a great advantage that the capacity of the next-time pattern program 120 stored in the storage device 100 can be drastically reduced to 1/4 as a whole.

The technical idea of the present invention is not limited to the specific configuration examples and connection mode examples of the above-described embodiment. Furthermore, based on the technical idea of the present invention, the above-described embodiments may be appropriately modified and widely applied. For example, the TS register R1 of the above-described embodiment is a simple concrete example in which a timing set of 4 words is stored, but by applying a memory, a timing set of several hundred words or more can be stored, and this is selected. TS with a specified bit width
The selection control register R2 may be provided.

In the above-mentioned embodiment, the writing to the TS selection control register R2 has been described as a specific example of writing by applying the tester bus TBUS, but if desired, generation of a plurality of bits of pattern data output from the PG may be generated. It may be applied and configured so as to be connected so as to directly write to the TS selection control register R2. In this case, there is an advantage that the PG can be changed at a timing synchronized with the generation of another pattern.

In the embodiment shown in FIG. 5, the specific configuration example in which the same setting data is set in the TS selection control registers R2 of all the tester channels can be operated under the simple condition has been described. A TS register R1 capable of storing a timing set of a desired number of words, for example, several hundreds of words for each tester channel, and a TS selection control register R2 having a bit width capable of selectively designating the TS register R1 are provided. For PRO1 for each tester channel (or for each tester channel group)
By writing a program so that different setting values can be set in the above, it is possible to apply even under different conditions of the TS number value R1s. In this case, the pattern program divided into a large number can be applied as a common pattern program more frequently, resulting in a more practical implementation means.

As shown in another conceptual structural example of FIG. 8, there is a structural example in which an address converting means 50 is provided instead of the TS register R1 and the TS selector 3 of FIG. In this configuration example, for example, a maximum of 32 types of TS number data TSD can be generated from the PG and can be switched on the fly. The address conversion means 50 is 1024
Memory of word x 10 bit width, 1 from PG
The lower 6 bits of the TS number data TSD of 0 bit width are received by the first address input terminal a1 and the TS number data T
The upper 4 bits of SD are supplied to the first address input terminal a1 of the timing set memory TSM. Further, the TS selection control signal R2s having a 4-bit width from the TS selection control register R2 is received at the second address input terminal a2 of the address conversion means 50, and the TS conversion data 50s having a 6-bit width read based on both addresses is received. Timing set memory TS
It is supplied to the second address input terminal a2 of M. As a result,
T based on the lower 6 bits in the TS number data TSD
The S number can be switched, and up to 16 pattern programs can be shared based on the 4-bit width of the TS selection control register R2. The memory capacity may be increased to supply all the 10-bit TS number data TSD from the PG to the first address input terminal a1 of the address conversion means 50 having the corresponding memory capacity. . According to the configuration of FIG. 8, the pattern program A is shared as shown in the description example in which only the timing set is different among the four pattern programs of FIG.
Since it can be applied even when a plurality of timing sets are randomly present, there is an advantage that the applicable frequency is further increased.

Further, the constituent means shown in FIG. 8 is applied to FIG.
The pattern division example in the pattern program memory PPM of (a) is a case where one pattern program can be divided into eight sub-side programs PRO2 to PRO9 at boundaries that do not hinder the division into a plurality of small sections. , Only when the timing set is different. First, an analysis means for analyzing the data content of the pattern program is provided to sequentially analyze and compare the data content. As a result, for example, it is detected that PRO3, PRO4, and PRO5 in FIG. 10A have different timing sets but can be shared, and PRO8 and PRO9 have two timing sets that are different but can be shared. To be detected. Based on these detections, a compressed pattern program can be obtained as shown in the example of the compression result of the pattern program of FIG. As a result,
As a result of an empty space being generated in the pattern program memory PPM, this portion becomes an additional storage area. As a result, it becomes possible to shift-store a part of the next pattern program 120 to this part. Therefore, in the case of the compression method of FIG. 10, the capacity of the entire pattern program can be compressed and reduced. Accordingly, if the number of pattern programs 120 can be reduced next time, there is an advantage that the throughput of the device test can be improved.

[0046]

The present invention has the following effects based on the above description. As described above, according to the present invention, the TS number data to be supplied to the timing set memory TSM is provided with the configuration means capable of independently changing the setting regardless of the timing set stored in the PG. There is an advantage that a plurality of programs, which are different only in the set, can be shared as one and tested. In addition, as a result of reducing the number of device test suspension periods A shown in FIG. 3, the throughput of the device test can be significantly improved. Moreover, since the entire program capacity can be compressed by sharing, there is an advantage that it can be significantly reduced. Therefore, the technical effect of the present invention is great, and the economic effect in industry is also great.

[Brief description of drawings]

FIG. 1 is a conceptual configuration diagram of a main part of a conventional semiconductor test apparatus according to the present application.

FIG. 2 shows a conventional pattern program memory PPM 4
Example of stored contents of pattern program and timing set when transferring one program.

FIG. 3 is a flowchart of a device test corresponding to FIG.

FIG. 4 is a conceptual configuration diagram of a main part of a semiconductor test apparatus according to the present invention of the present invention.

FIG. 5 is a conceptual diagram of a shared pattern program shared by one of the present invention.

FIG. 6 is a flowchart of a device test of the present invention.

FIG. 7 is a principle program description example of a main program PRO1 according to the present invention.

FIG. 8 is another conceptual configuration example of a main part of the semiconductor test apparatus according to the present invention of the present invention.

FIG. 9 is an example of the stored contents of a pattern program and a timing set in the case where four pattern programs differ in only the timing set at many places.

FIG. 10 is a pattern program memory PPM of the present invention.
3 is an example of pattern division and a pattern program example in which a shared part is compressed.

[Explanation of symbols]

R1 TS register VD1 Variable delay means PRO1 Main side program PRO2 to PRO9 Sub side program R2 TS selection control register 3 TS selector 10 Test cycle generation section 20 Clock generation section 50 Address conversion means 100 Storage device 120 Next pattern program DUT Device under test PG Pattern Generator PPM Pattern Program Memory TBUS Tester Bus TGFC Timing Generator / Waveformer (Timing Gener)
ator Format Control) TSM Timing Set Memory

Claims (12)

[Claims] 1. A semiconductor test apparatus having a timing set memory for storing a predetermined plurality of timing sets for defining timing edges of generated pulses used for testing a device under test, and storing the same in a pattern generator together with other pattern data. Other TS that selects and specifies the timing set without applying the TS number data that specifies and specifies the selected timing set
A semiconductor test apparatus, comprising: TS number resource selection control means capable of supplying a TS number value from a number resource to the timing set memory. 2. A semiconductor test apparatus having a timing set memory for storing a plurality of predetermined timing sets for defining timing edges of generated pulses used for testing a device under test, wherein a timing set generated from a pattern generator is selected. A semiconductor test apparatus comprising: a TS number resource selection control means capable of supplying a TS number value from a TS number resource different from the designated TS number data to the timing set memory. 3. A timing set memory for storing a plurality of predetermined timing sets for defining timing edges of generated pulses used for testing a device under test,
In a semiconductor test apparatus for supplying a TS number value for selecting and designating a predetermined timing set from the pattern generator to the timing set memory, and generating and outputting a generated pulse at a predetermined timing based on the TS number value. In the normal supply mode, the TS number data supplied from the pattern generator is supplied to the timing set memory as a TS number value. Secondly, in the TS number independent supply mode, the TS number resource different from the TS number data is used. 2. A semiconductor test apparatus, comprising: TS number resource selection control means capable of supplying the TS number value of 1. to the timing set memory. 4. A TS number for selecting and designating a predetermined timing set, comprising a timing set memory TSM for storing a plurality of predetermined timing sets defining timing edges of generated pulses used for testing a device under test (DUT). In a semiconductor test apparatus that supplies a value from the pattern generator PG to the timing set memory TSM and generates and outputs a generated pulse at a predetermined timing based on the value, a timing set that is pattern data generated from the pattern generator PG is generated. TS number data TSD to select and specify
A normal operation mode for supplying the TS number value of the TS number data to the timing set memory TSM is called a TS number normal supply mode, and a TS number value independent of the TS number data TSD from another system different from the TS number data TSD. Of the operation mode for supplying the timing set memory TSM
In the number independent supply mode, the pattern generator P is used in the TS number normal supply mode.
The TS number data TSD supplied from G is supplied to the timing set memory TSM as a TS number value, and the TS
In the number independent supply mode, the TS number data TSD
A semiconductor test apparatus, comprising: TS number resource selection control means capable of supplying a TS number value from a TS number resource different from that to the timing set memory TSM. 5. A pattern program memory PPM for storing a program for testing a device under test (DUT), the pattern program memory PPM generating pattern data for generating a test waveform for testing the DUT,
Also, TS number data TSD for selecting and designating a predetermined TS number from a plurality of numbers (TS numbers) of a plurality of timing sets that define the timing edges of the generated pulses.
To generate timing together with other pattern data.
The pattern generator PG supplied to the waveform shaping unit TGFC and the timing generation / waveform shaping unit TGFC have a timing set memory TSM for storing a timing set therein, and the timing set memory TSM selects a TS number value of the timing set. Timing of receiving a predetermined TS number input signal to be designated as an input and generating and outputting a generated pulse of a timing edge delayed by a predetermined timing based on the timing set selected and designated by the TS number input signal, or timing delayed by a predetermined delay In a semiconductor test apparatus having a configuration of outputting a generated pulse whose waveform is shaped into a predetermined test waveform at an edge, a TS number value of TS number data TSD which is pattern data generated from a pattern generator PG is supplied to the timing set memory TSM. Normal operation mode The operation mode for supplying a TS number value independent of the TS number data TSD to the timing set memory TSM from another system different from the TS number data TSD is called the TS number independent supply mode. When the TS number normal supply mode is set, the pattern generator P
The TS number data TSD supplied from G is supplied to the timing set memory TSM as a TS number value, and the TS
In the number independent supply mode, the TS number data TSD
A semiconductor test apparatus, comprising: TS number resource selection control means capable of supplying a TS number value from a TS number resource different from that to the timing set memory TSM. 6. The TS number resource selection control means is T
An S switching means, a TS selection mode register, a TS number value storage means, and a TS number designating means are provided. First, the TS switching means is operated from the pattern program memory PPM of the PG in the TS number normal supply mode. The generated TS number data TSD is selected and supplied to the timing set memory TSM. Secondly, in the TS number independent supply mode, the TS number value output from the TS number value storage means is supplied to the timing set memory TSM. The TS selection mode register controls to switch the operation mode between the TS number normal supply mode and the TS number independent supply mode, and the TS number value storage means is applied in the test execution of the DUT. A storage device having at least a storage capacity capable of storing a plurality of TS number values, the TS number designation Means can control the designation of TS number values
A register for receiving and holding a control signal for selecting and designating a TS number value corresponding to the execution of the device test among the TS number values stored in the TS number value storage means based on the S control program, The semiconductor test apparatus according to claim 1, comprising the above. 7. The TS number resource selection control means is T
An S number converting means and a TS number designating means are provided. The TS number converting means is a memory for storing a plurality of TS number values applied to a pattern program for test execution of the DUT, and an address input terminal of the memory. Is divided into a first address input end and a second address input end, and one of the first address input ends receives a predetermined number of bits or the total number of bits of the TS number data TSD, and the other second input end. A switching signal output from the TS number designating means is input to the address input terminal, and based on the switching signal, the converted TS number value converted into a predetermined TS number value is read out and output. , So that the TS number designating means can convert the TS number values stored in the TS number converting means into the TS number values to be applied by the pattern program. , Based on the TS control program that can control the specification of the TS number value TS
6. A semiconductor test apparatus according to claim 1, wherein the register is a register for receiving and latching a number switching control signal, and including the above. 8. When a pattern program having only different TS number values is referred to as a shared pattern, the TS control program is selectively output by the TS number conversion means immediately before execution of the shared pattern that appears a plurality of times. 8. The semiconductor test apparatus according to claim 6, wherein the TS number designating means is controlled in a predetermined manner so that the TS number value becomes a TS number value applied in the common pattern. 9. The pattern program stored in the pattern program memory PPM of the pattern generator PG, wherein the shared pattern is a pattern program that differs only in the TS number values that continue at least twice. 8. The semiconductor test device according to 8. 10. In the pattern program stored in the pattern program memory PPM of the pattern generator PG, the shared pattern is a TS that is continuous at least twice.
When there is a condition that a pattern program having a different number value is transferred to and stored in the pattern program memory PPM, it is applied as a shared pattern to be transferred and stored once in the pattern program memory PPM. Prepared by adding a side program,
9. The semiconductor test apparatus according to claim 8, wherein a TS number value is sequentially specified based on the main program, and one shared pattern is called by a subroutine to be executed. 11. The pattern program stored in the pattern program memory PPM of the pattern generator PG, wherein the shared pattern is divided into pattern program units having different TS number values only. 8. The semiconductor test device according to 8. 12. In a pattern program stored in a pattern program memory PPM of a pattern generator PG, the common pattern is divided into units applicable as a common pattern, and a predetermined TS number is assigned to the divided common pattern. 9. The semiconductor test apparatus according to claim 8, further comprising: a main-side program for sequentially switching control to a value and subroutine-calling the divided shared pattern, which is stored in the pattern program memory PPM in a predetermined manner.