JP2003125016A - Receiver - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a receiver, capable of detecting automatically a mode, even if a signal of a different format on a receiver side is input to switch the signal format. SOLUTION: An input signal is supplied to an AGC circuit 2, controlled to be a fixed amplitude and is sent to an A/D converter 3. Here, the signal is converted into a digital signal to output to a roll-off filter 4. A digital signal is limited in a band by the roll-off filter, to output to a waveform equalizer 7, a clock-regenerating circuit 51 and the AGC circuit 2. In the signal, deterioration of frequency characteristics, due to influences of a phasing or the like caused in a transmission path by the waveform equalizer 7, are corrected to output to a level determinator 8'. The level determinator 8' performs a remapping of the signal to send the signal to a P/S converter 9, which converts the signal into a serial signal to output from a signal output part 10.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a receiver for receiving signals transmitted in a plurality of signal formats, and more particularly to a receiver having a clock recovery function by a synchronous detection method.

[0002]

2. Description of the Related Art Conventionally, when changing the format (modulation method, transmission rate, etc.) of a transmission signal, that is, a signal input to a reception control unit on the receiver side, the signal format preset on the transmitter side is used. It was necessary to confirm and change the signal format setting by a switch provided in the reception control unit or by remote control to match it.

FIG. 2 is a block diagram showing the configuration of a conventional digital repeater wireless relay device. Reception controller 1
The input signal input to the
Supplied to circuit 2. The AGC circuit 2 controls the inputted input signal to a constant amplitude by AGC (Automatic GainControl) and outputs it to the A / D converter 3. The A / D converter 3 converts the input signal into an A / D (Analog-to-Digital
) Convert and output to roll-off filter 4 as a digital signal.

The sampling clock of the A / D converter 3 uses the clock extracted from the input signal by the clock recovery circuit 5 in the subsequent stage. The input signal converted to a digital signal by the A / D converter 3 is band-limited by the roll-off filter 4 whose characteristics are squarely distributed to the transmitter / receiver, and the waveform equalizer 7, clock recovery circuit 5, and AG
Output to C circuit 2. The clock recovery circuit 5 processes the input signal by PLL (Phase Locked Loop) processing.
A clock component synchronized with the input signal is extracted.

As described above, the input signal input is AG
C circuit 2, A / D converter 3, roll-off filter 4
, And is demodulated by the clock recovery circuit 5 and output to the waveform equalizer 7. The waveform equalizer 7 corrects the demodulated signal for the deterioration of the frequency characteristic due to the influence of fading or the like generated in the transmission path, and outputs it to the level determiner 8. The level determiner 8 remaps to the digital signal level mapped in the transmitter and outputs it to the P / S converter 9. The P / S converter 9 performs P / S (parallel-to-serial) conversion on the input signal to convert it into a serial signal, and outputs the serial signal via the signal output unit 10.

[0006]

In the digital modulation / demodulation type wireless relay device, an appropriate signal format can be selected according to the content of the signal to be transmitted and the state of the transmission path.
In many cases, it has a plurality of modulation schemes and supports different transmission rates. When setting up a relay line, the receiver side confirms the modulation method and transmission rate set on the transmitter side in advance, and the signal format is reset by the switch equipped in the reception control unit or the remote control accordingly. Was needed. In addition, even if it is necessary to change the signal format due to the condition of the transmission path during transmission, the receiver side must reset the signal format each time the transmitter side changes. This was one of the causes of lowering work efficiency. An object of the present invention is to eliminate the above-mentioned drawbacks and provide a receiver capable of automatically detecting and switching modes even when signals of different formats are input on the receiver side. To do.

[0007]

In order to achieve the above object, the receiving apparatus of the present invention detects the synchronization state of the clock recovery circuit to identify the format of the input signal, and to determine the modulation method and Even if signals with different transmission rates are input, the signal format set on the receiver side can be automatically switched.

Further, the receiving apparatus of the present invention is an AGC means for inputting a signal transmitted in one of predetermined signal formats and performing automatic amplitude control (hereinafter referred to as AGC) on the input signal. And an analog-to-digital converter (hereinafter referred to as an A / D converter) for converting a signal whose amplitude is controlled by the AGC means into a digital signal, and a roll for band limiting the output digital signal of the A / D converter. An off filter and a clock recovery means for inputting the band-limited signal and extracting a clock based on one of the predetermined signal formats are provided.

Also, the receiving apparatus of the present invention comprises remapping means corresponding to each of the predetermined signal formats. Further, in the receiving device of the present invention, the clock reproducing means is a clock reproducing means corresponding to each of predetermined signal formats,
It is characterized in that the clock regeneration processing is automatically switched according to the signal format of the inputted input signal. Also,
In the receiving device of the present invention, the clock reproduction means detects a synchronization state of the clock reproduction corresponding to each of the predetermined signal formats, and demodulates based on a clock synchronized within a predetermined time. To do.

[0010]

BEST MODE FOR CARRYING OUT THE INVENTION An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing a configuration of the present invention, and FIG. 3 is a block diagram showing an automatic switching selection method of the present invention. In FIG. 1, the reception control unit
The input signal input to 1'is supplied to the AGC circuit 2 in the reception control section 1 '. The AGC circuit 2 controls the inputted input signal to a constant amplitude by AGC (Automatic Gain Control) and outputs it to the A / D converter 3. A
The / D converter 3 converts the input signal into A / D (Analog-to-D
igital) converted to digital signal and rolled off
Output to filter 4.

The sampling clock of the A / D converter 3 uses the clock extracted from the input signal by the clock recovery circuit 5 in the subsequent stage. Roll-off filter
4 is a roll-off type whose input signal converted to digital signal by A / D converter 3 is squarely distributed to the transceiver.
The band is limited by the filter 4 and output to the waveform equalizer 7, the clock recovery circuit 5 ′, and the AGC circuit 2.

The clock recovery circuit 5'switches and inputs the signal band-limited by the roll-off filter 4 to a clock recovery unit provided for each preset input signal format, and synchronizes with the input signal by PLL processing. The extracted clock component is extracted. The mode detection unit 6 detects the synchronization state of the PLL processing, and detects the format of the transmitted signal, that is, the mode set on the transmitter side based on the synchronization state. Then, a control signal for outputting the clock component extracted in the detected mode to the A / D converter 6 from the clock regeneration circuit 5'is output. Clock recovery circuit 5 ′
Outputs the extracted clock to the A / D converter 3 according to the given control signal. In addition, the mode detector 6
A signal corresponding to the detected mode is also supplied to the level discriminator 8'to provide a signal for proper remapping, and the level discriminator 8'performs remapping based on the signal.

As described above, the input signal input is AG
C circuit 2, A / D converter 3, roll-off filter 4
, The clock recovery circuit 5 ′ and the mode detector 6 demodulate and output to the waveform equalizer 7. The signal demodulated according to the mode thus detected is corrected by the waveform equalizer 7 for the deterioration of the frequency characteristic due to the influence of fading or the like generated in the transmission line, and is output to the level determiner 8 '. The level determiner 8'remaps the digital signal level mapped in the transmitter and outputs it to the P / S converter 9. It is converted to a serial signal by the P / S converter 9 and output from the signal output unit 10.

An embodiment of the switching circuit of the present invention will be described below with reference to FIG. FIG. 3 is a diagram for explaining an embodiment of the automatic switching selection method of the present invention. Figure 3
Is the clock recovery circuit 5'of FIG. 1 and the A / D converter 2,
FIG. 4 is a diagram showing a roll-off filter 4, a waveform equalizer 7, and a mode detection unit 6, which is a clock recovery circuit.
5'shows only internal clock recovery sections 5-1 and 5-2 and switching circuits 5-3 and 5-4 which are particularly necessary for the description of the present invention. As an example, FIG. 3 shows two signal formats (for example,
Clock recovery block 5-1 is QPSK, clock recovery block 5-2 is
It supports 16QAM) and has a switchable configuration. Also, for example, in the case of three or more modulation methods,
In addition to QPSK and 16QAM, combinations such as 32QAM, 64QAM, and π / 4 shift QPSK are conceivable. Further, even with the same modulation method, the combination can be further changed by changing the transmission rate.

The input signal whose band is limited by the roll-off filter 4 is a clock recovery unit 5-1 (mode 1) which is a clock recovery circuit of two systems corresponding to two types of signal formats (mode 1 and mode 2). Correspondence) and clock recovery unit
5-2 (corresponding to mode 2) is input. The signal input to the clock recovery circuit 5'is first input to the clock recovery section 5-1 by the switching circuit 5-4, and the clock is extracted by the PLL processing. The switching circuit 5-3 is also set to the state of outputting the signal of the clock recovery block 5-1. The mode detection unit 6 is provided with a counter (not shown) for a fixed time that sufficiently satisfies the time until the synchronization by the PLL processing of the clock recovery unit 5-1 is completed. Also, the control voltage of the crystal oscillator (not shown) mounted in the clock recovery unit 5-1 is monitored, and if the voltage goes out of synchronization, the counter is reset.

A method for detecting that the control voltage is out of synchronization is performed by comparing the control voltage of the crystal oscillator and a predetermined reference voltage with a comparator, and when the control voltage is less than the reference voltage, the synchronization state is achieved. It is detected by deviating from. The mode detector 6 is a roll-off filter.
The signal output from 4 is input to the clock regenerator 5-1 via the switching circuit 5-4, and the recommended oscillator control voltage of the clock regenerator 5-1 is monitored. And the clock recovery unit 5
When the input is started to -1, the counter is started at the same time, and if the out-of-synchronization is not detected by the control voltage and the counting for the fixed time ends, it can be judged that the PLL processing is in the synchronous state and the input signal The format of is determined to be mode 1. If the PLL output of the signal output from the roll-off filter 4 is out of synchronization and the counter is reset and the counter is reset, the mode detector
6 judges that the input signal format is not mode 1. Then, the switching circuit 5-4 is switched, and the signal output from the roll-off filter 4 is input to the clock recovery unit 5-2. In addition, the switching circuit 5-3 is also a clock recovery unit.
Set to output the signal of 5-2.

Here, as a condition for shifting to the clock reproducing unit 5-2, the number of times the counter is reset in the clock reproducing unit 5-1 can be arbitrarily set. In the clock regenerator 5-2 as well, the synchronization state is detected by the control voltage as in the clock regenerator 5-1. It can be seen that the type of the input signal was mode 2 when the clock recovery unit 5-2 is in the synchronized state.

When the clock recovery circuit section 5-2 is not in the synchronized state, the process returns to the clock recovery section 5-1 again. By repeating the above processing, it is possible to automatically identify and switch the signal format regardless of the format of the input signal. Note that the number of detectable input signals can be changed depending on the number of mounted clock recovery circuit units. Further, the switching circuit 5-4 is not always necessary, and simultaneously operates all clock recovery units,
The switching circuit 5-3 may be switched to the best synchronized mode. Further, the counter is incorporated in the clock regenerating unit in the above embodiment, but may be incorporated in the mode detecting unit.

[0019]

As described above, according to the present invention, it is possible to eliminate the need for mode setting on the receiver side when a signal having a different modulation method or transmission rate is transmitted in a digital repeater wireless relay apparatus. It will be possible.

[Brief description of drawings]

FIG. 1 is a block diagram showing the configuration of an embodiment of a wireless relay device of the present invention.

FIG. 2 is a block diagram showing a configuration of a conventional wireless relay device.

FIG. 3 is a diagram for explaining an embodiment of an automatic switching selection method according to the present invention.

[Explanation of symbols]

1, 1 ': reception control unit, 2: AGC circuit, 3: A / D converter, 4: roll-off filter, 5, 5': clock recovery circuit, 5-1 and 5-2: clock recovery unit, 5-3, 5-4:
Switching circuit, 6: mode detector, 7: waveform equalizer,
8 and 8 ': Level detector, 9: P / S converter, 10: Signal output section.

Claims (4)

[Claims] 1. An AGC means for inputting a signal transmitted by one of predetermined signal formats and performing automatic amplitude control (hereinafter referred to as AGC) on the input signal, and an amplitude by the AGC means. An analog-to-digital converter (hereinafter referred to as an A / D converter) that converts a controlled signal into a digital signal, a roll-off filter that band-limits an output digital signal of the A / D converter, and the band A receiving device, comprising: a clock reproducing means for inputting a limited signal and extracting a clock based on one of the predetermined signal formats. 2. The reception control unit of the reception apparatus according to claim 1, further comprising remapping means corresponding to each of the predetermined signal formats. 3. The receiving device according to claim 1, wherein the clock regenerating unit is a clock regenerating unit corresponding to each of predetermined signal formats, and the input is input. A receiving device characterized by automatically switching clock recovery processing according to a signal format of a signal. 4. The receiving device according to claim 3, wherein the clock reproduction means detects a synchronization state of the clock reproduction corresponding to each of the predetermined signal formats, and based on a clock synchronized within a predetermined time. A receiving device characterized by performing demodulation.