JP2003124808A - Prescaler, frequency dividing counter, and pll frequency synthesizer - Google Patents

Abstract

PROBLEM TO BE SOLVED: To constitute a multi-modulous type prescaler by using a single p/p+1 dual-modulus counter. SOLUTION: The prescaler 1 comprises a 4/5 dual-modulous counter and its low-order binary counter, and modulous control over the 4/5 dual-modulous counter is performed with three kinds of control signals p+1, p+2, and p+4 control from a one-shot circuit 3 and a swallow counter 2 to constitute a multi- modulus type prescaler for p/p+1/p+2/p+4, so that the prescaler is used for a frequency-dividing counter and a frequency synthesizer.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an ECL-type bipolar transistor structure for dividing a high frequency RF signal.
A PLL-Prescaler (PLL-Presca) suitable for a one-chip LSI including a prescaler circuit and a counter circuit having a CMOS transistor configuration
ler: prescaler), and more particularly, to a multi-modulus type PLL frequency synthesizer capable of reducing the influence of noise from a CMOS counter circuit on a high-frequency RF circuit and the like.

[0002]

2. Description of the Related Art In the field of mobile phones, etc., a highly integrated one-chip LSI product including blocks for transmission, reception, and a PLL frequency synthesizer in order to realize a demand for smaller and lighter sets and system integration. The development and mass production of has been realized. Hereinafter, the conventional PLL frequency synthesizer will be described in detail.

FIG. 7 shows a conventional dual modulus.
It is a figure which shows the block structure of the PLL frequency synthesizer of a Modulus system. This PLL frequency synthesizer is an ECL- with a bipolar transistor configuration that performs a high-speed frequency division operation of p / p + 1 with respect to an RF input signal RFin.
A prescaler circuit 11 and a main-counter circuit 13 of a unipolar transistor (CMOS) configuration that receives a prescaler output from the prescaler circuit 11 and generates a phase comparison signal according to a set CH, and a prescaler of a CMOS configuration as well. Swallow-counter 1 for controlling 11 p + 1 operation timings
2 and a phase comparator / charge pump circuit 14 that detects and outputs a phase difference between the reference signal Fref and a loop filter 15 that converts the output of the serge pump into a smoothed voltage.
And a voltage controlled oscillator (VCO) 16 that varies the oscillation frequency according to the input voltage from the loop filter 15.

FIG. 8 is a diagram showing the configuration of the prescaler circuit 11 used in the conventional PLL frequency synthesizer shown in FIG. The input signal RFin is supplied to the clock terminal and the inverted output Q is input to the D terminal via the OR circuit 54, and the input signal RFin is input to the clock terminal and the D type flip-flop circuit is input to the D terminal. A D-type flip-flop circuit 52 for inputting the output Q of 51 through the OR circuit 55, and a T for outputting the output Q to the OR circuit 55 by inputting the inverted output Q-to the trigger terminal.
And a plurality of T-type flip-flop circuits 61, 62, 63, 64 for sequentially inputting the inverted output Q of the preceding stage to the trigger terminal. Controls the frequency division number of the ^2n- ary counter 60 configured to input the inverted output Q of the T-type flip-flop circuit 23 to the trigger terminal of the first-stage T-type flip-flop circuit 61 and the 4/5 dual modulus counter 20. And a logic circuit 70 that operates.

FIG. 9 is a timing chart showing the operation of the prescaler circuit. First, referring to FIG. 9, FIG.
The modulus operation of the prescaler circuit shown in FIG.
9, FF4 / 5 is a diagram showing the output timing of the D-type flip-flop circuit 51 of the 4/5 dual modulus counter 50, and FF8 to FF64 are T-type flip-flop circuits 61 of the 2 ^n- ary counter 60, respectively. It is a figure which shows the output timing of -64.

When the output of the NAND circuit 71 is at "H" level, the inverted output Q- of the D-type flip-flop circuit 52 is always at "L" level. In this state, the D-type flip-flop circuit 51 operates as a T-type flip-flop circuit because the inverted output Q-is fed back to the D terminal via the OR circuit 54, and thus performs the 1/2 frequency dividing operation. Also, N
When the output of the AND circuit 71 is at “L” level, the T-type flip-flop circuit 53 becomes the D-type flip-flop circuit 5.
Since the state of the D terminal of the D-type flip-flop circuit 52 is controlled each time it operates with the inverted output Q of 1, the D-type flip-flop circuit 51 performs 1/2 or 1/3 division operation of the input signal RFin. . Therefore, the dual modulus
The counter 50 is a 1 by the T-type flip-flop circuit 53.
By the / 2 frequency division function, 1/4 or 1/5 frequency division, that is,
Operates as a 4/5 dual modulus counter.
Then, the logic circuit 70 outputs all the inverted outputs Q of each stage of the 2 ^n- ary counter 60 and the output Swall of the swallow counter.
Since the 4/5 dual modulus counter controls the 1/5 frequency division operation on the condition that the "L" level of ow (65) is set, the prescaler shown in FIG. The p + 1 modulus control (fraction control, Swallow control) is executed at the timing.

FIG. 10 is a timing chart showing the operations of the main counter and the swallow counter for controlling the prescaler. In the figure, the prescaler output (Prescaler out) is the output (FF64) of the T-type flip-flop 64 shown in FIG. 8, and the scale of the time axis is different from that in FIG. Further, the time chart of FIG. 10 shows an example in which the main counter setting value M = 25 and the swallow counter setting value S = 19. The operation of the figure is as follows.

As shown in FIG. 10, the main counter (Ma
in Counter) 13 outputs the prescaler output (FF64) to 2
Prescaler output 1 cycle width signal is output every 5 counts,
The swallow counter 12 is set (outputs "H" level) at the timing of the trailing edge of the output of the main counter 13, counts the prescaler output by a predetermined number s (= 19), and returns to "L" level. Therefore, the 4/5 dual modulus counter performs the 1/5 frequency division operation at the final timing within each s prescaler operation cycle to execute the p + 1 modulus control.

In the frequency dividing counter configured such that the prescaler circuit for performing the p / p + 1 frequency dividing operation as described above is used and the timing of the p + 1 frequency dividing operation is feedback-controlled by the swallow counter, the total frequency dividing number N Is a prescaler set value p / p + 1, a main counter set value m, and a swallow counter set value s, N = p * (ms) + (p + 1) * s = p * m + s ... can be calculated as equation (1). .

Next, the number of steps of the prescaler, which is a binary value of the set value (decimal) in the dual modulus control, and the set BIT number of the counter system (swallow counter and main counter), will be examined. In order to be able to set the swallow counter set value s from 0 to p-1, the number of prescaler stages [p] = the number of swallow counter set BITs [s] (the symbol in [] represents a decimal set value.) Must be satisfied, and further, the (ms) term that sets the p-scaler operation of the prescaler in Expression (1) cannot be set negatively (when m <s,
It means that the main counter finishes counting first while the swallow counter is counting, and the continuity of CH setting is interrupted.) Therefore, the number of stages of the prescaler and each setting of the counter system B
The relationship of the number of IT is as follows. Prescaler stage number [p] = swallow counter setting BIT number [s] <main counter setting BIT number [m] Equation (2)

By satisfying this condition, the swallow counter set value s can be set from 0 to p−1, so that an apparent full program (Full Program, all integers) capable of setting all CHs as a PLL frequency synthesizer. (Control) counter control is possible.

However, in the conventional dual modulus type PLL frequency synthesizer, as can be seen from the equation (2), the number of stages of the prescaler is the total frequency division setting BI of only the counter system (swallow counter and main counter).
Since it is necessary to set within a range of 1/2 or less of the T number [s + m], the number of BITs set on the main counter side is increased in order to realize the frequency division number required for the entire frequency division counter, The operating frequency of the system increases.

As a result, the transmission / reception system and the PL as described above are
In the application of the PLL frequency synthesizer to a highly integrated one-chip LSI including each block of the L system, logic noise with a low harmonic order from the PLL system is caused by various characteristics of the transmission / reception system block. May be affected.

By the way, a prescaler or a PLL frequency synthesizer capable of performing a plurality of modulus operations is disclosed in Japanese Patent Application Laid-Open Nos. 5-268080 and 2001-4482.
No. 4 publication.

FIG. 11 is a diagram showing a prescaler circuit described in the above-mentioned Japanese Patent Laid-Open No. 5-268080. It is composed of flip-flop circuits FF1, FF2, FF3 and an OR circuit for feeding back the outputs of the respective flip-flop circuits to the input of the flip-flop circuit FF1. The flip-flop circuit FF1 inputs the module signal M1 and outputs M
When 1 is at H level, the output signal bar Q1 and the same bar Q1
It operates as a flip-flop circuit in which R is the same, and when the module signal M1 is at L level, the output signal Q
1R becomes L level, and the output signal bar Q1 operates as a D flip-flop. In addition, the flip-flop circuit F
The output signal Q3 of the F3 operates as a D flip-flop when the output signal Q3 is at the L level when the module signal M3 is at the L level, and when the module signal M3 is at the H level.

With the above configuration, when the module signal M3 is at the L level, the output OUT becomes the clock signal divided by 3 while the module signal M1 is at the L level, and when the module signal M1 is at the H level, the output OUT is 4 times. Divided output. When the module signal M3 is at the H level, the clock signal is divided by 4 while the module signal M1 is at the L level, and the clock signal is divided by 5 while the module signal M1 is at the H level. That is, the prescaler shown in FIG. 9 performs P-1 frequency division operation in addition to P frequency division and P + 1 frequency division operation according to the levels of the module signals M1 and M3.

FIG. 12 shows the above-mentioned JP 2001-44824 A.
It is a figure which shows the frequency divider structure of the two prescaler structure of the publication. A first dual-modulus frequency divider controllable by the modulus control mod1, and a modulus control m
A quadrature modulus prescaler is configured by a cascade connection configuration with a second dual modulus frequency divider that can be controlled by od16, and a combination of frequency division ratios of the respective dual modulus frequency dividers. When applied to a frequency synthesizer, the modulus control mod1, m
od16 is set by a main counter that counts the output of the second dual-modulus frequency divider, and counts 2 the output of the second dual-modulus frequency divider.
Controlled by two swallow counters. That is, the first
The output of the first swallow counter controls mod1 and the output of the second swallow counter controls the mod2.

Regarding the modulus control operation of the frequency divider shown in the figure, the 16/17 frequency divider and the 4/5 frequency divider will be concretely described by using the first and second dual modulus frequency dividers, respectively. To explain, for the 16 × 4 = 64 division of the first dual modulus divider, the dividing operation of 65 by the control of mod1 is performed only once during the counting process of the second dual modulus divider. A multiple 64/65/80/81 modulus control is performed by combining a frequency division operation of 81 by the control of mod1 performed only once during the counting process of the second dual modulus frequency divider for a frequency division of × 5 = 80. Is realized.

[0019]

As described above, FIGS.
In the dual modulus type PLL frequency synthesizer shown in (1), it is necessary to increase the number of BITs set in the main counter in order to enable full program counter control capable of setting all CHs. In the system, the operating frequency of the counter system of the CMOS structure usually has to be raised.

However, in the system LSI in which the analog transmission and reception IC also includes the PLL frequency synthesizer as described above, the LSI circuit is increased by the operating frequency of the CMOS circuit having a characteristic noise characteristic such as shoot-through current. The sneak of noise from the digital block to the analog block is a serious problem. Specifically, in a wireless system in which the RF comparison frequency is 250 GHz and the PLL comparison frequency is 250 kHz, the total set BIT number of the counter system is 13 BIT [N = 800.
0: 2 ^ 13 BIT], and considering from the equation (2) that the swallow counter setting BIT number is 6 [s = 2 ^ 6] and the main counter setting BIT number is 7 [m = 2 ^ 7], the number of stages of the prescaler circuit is 6 ( Since the frequency division number is 64/65),
The operating frequency of the counter system is about 31 MHz. On the other hand, in the reception and transmission blocks of the double conversion type wireless communication device, the IF frequency is often set to 50 to 130 MHz due to the restriction of the attenuation characteristics of the surface acoustic wave SAW filter used in the intermediate frequency (IF) stage.
Depending on the H setting, the 2nd to 4th harmonic components of the counter system directly cover the IF signal, causing deterioration of the reception sensitivity,
A case may occur that causes deterioration of spurious noise of the transmission system.

On the other hand, the prescaler shown in FIG. 11 performs prescaler of 3 and 4 frequency division operation and 4 and 5 frequency division operation, that is, p-1 frequency division operation in addition to p frequency division operation and p + 1 frequency division operation. However, this prescaler allows the prescaler to perform multiple 2-modulus operations (two dual-modulus operations) in order to increase the reference frequency and shorten the lock-up time. The number of prescaler stages and the counter system (swallow counter, main counter)
No consideration has been given to the relationship with the number of BITs set, and it is necessary to increase the number of BITs set for the main counter in view of the number of stages of the prescaler divided by 3 and 4 and divided by 4 and 5. The modulus operation is also limited to the three-modulus operation, and it is not possible to realize a multi-modulus configuration of four or more for further lowering the operating frequency of the counter system.

Further, since the prescaler shown in FIG. 12 constitutes the quadromodulus prescaler by the cascade connection configuration of the first and second dual modulus dividers, it enables a plurality of modulus operations. In the prescaler, for example, the first and second dual modulus dividers are respectively divided into 16/17 divider and 4
As you can see in the example of using the / 5 frequency divider,
When switching the frequency division number of the frequency divider, 16 or 17
Since the frequency division output is switched between the frequency division by 4 and the frequency division by 5, the frequency division output of the 4/5 frequency divider causes a phase variation of 16 (or 17) input pulses of the prescaler. The output of the prescaler and the counter system may be affected by jitter or the like.

The present invention solves the problems as described above, and is suitable for application to a highly integrated one-chip LSI including a transmission / reception block and a PLL frequency synthesizer block, and is capable of preventing the occurrence of jitter noise. The multi-modulus prescaler, which is the principle of operation, constitutes a frequency dividing counter and a PLL frequency synthesizer. That is, (Objective) The purpose of the present invention is to provide a single dual modulus
An object of the present invention is to provide a multi-modulus prescaler capable of setting a large frequency division number using a counter.
It is an object of the present invention to provide a frequency division counter using a multi-modulus prescaler which enables setting of a large frequency division number using a single dual modulus counter. An object of the present invention is to increase the frequency division number of the prescaler without lowering the comparison frequency, thereby lowering the operating frequency of the swallow counter and the main counter, which normally adopt the CMOS configuration and become a noise source, and affect the transmission / reception system circuits. Another object of the present invention is to provide a PLL frequency synthesizer capable of reducing the wraparound noise by increasing the harmonic order of the operating frequency.

[0024]

The prescaler of the present invention includes a p / p + 1 dual modulus counter (for example, 20 in FIG. 3) and the p / p + 1 dual modulus counter.
A lower counter (eg 30 in FIG. 3) for counting the output of the counter, a control terminal (eg 46 in FIG. 3) for inputting a plurality of control signals for controlling the p / p + 1 dual modulus counter, and a lower counter of the lower counter. A plurality of p + 1 modulus operation timings generated by decoding the output, and a control circuit (for example, 40 in FIG. 3) that controls one or a plurality of p + 1 modulus operations according to each of the plurality of control signals. It is characterized by performing a modulus operation.

The frequency dividing counter of the present invention comprises a p / p + 1 dual modulus counter (eg 20 in FIG. 3) and a lower counter (eg 30 in FIG. 3) for counting the output of the p / p + 1 dual modulus counter. , P /
a control terminal (for example, 46 in FIG. 3) for inputting a plurality of control signals for controlling the p + 1 dual modulus counter,
And a control circuit (for example, 40 in FIG. 3) that controls one and a plurality of p + 1 modulus operations corresponding to each of the plurality of control signals at a plurality of p + 1 modulus operation timings generated by decoding the output of the lower counter. A prescaler (for example, 1 in FIG. 2 and FIG. 3) provided, a main counter (for example, 4 in FIG. 2) that counts the output of the lower counter, and an upper bit of the prescaler that is set by the output of the main counter. A swallow counter (for example, 2 in FIG. 2) that outputs a control signal,
And a one-shot circuit (for example, 3 in FIG. 2) that outputs the control signal for controlling the lower bits of the prescaler.

The PLL frequency synthesizer of the present invention compares the phase difference between the divided signal obtained by dividing the output of the voltage controlled oscillator (for example, 7 in FIG. 1) by the frequency dividing counter (for example, FIG. 2) and the reference signal. A PLL frequency synthesizer that generates a phase error signal and controls the output frequency of the voltage controlled oscillator by the low frequency component of the phase error signal (eg, FIG. 1).
In the above, the frequency division counter is a p / p + 1 dual modulus counter (for example, 20 in FIG. 3) that counts the output of the voltage controlled oscillator, and a lower counter (for example, 20) that counts the output of the p / p + 1 dual modulus counter. 3), a control terminal for inputting a plurality of control signals for controlling the p / p + 1 dual modulus counter (for example, 46 in FIG. 3), and a plurality of p + 1 generated by decoding the output of the lower counter. A prescaler including a control circuit (for example, 40 in FIG. 3) that controls one and a plurality of p + 1 modulus operations in response to each of the plurality of control signals at a modulus operation timing;
A main counter (for example, 4 in FIG. 1) that counts the output of the lower counter and outputs the divided signal, and a swallow that outputs the control signal that is set by the output of the main counter and that controls the upper bits of the prescaler. It is characterized by including a counter (for example, 2 in FIG. 1) and a one-shot circuit (for example, 3 in FIG. 1) that outputs the control signal for controlling the lower bit of the prescaler.

The prescaler is p / p + 1 / p.
+ 2 / p + 4 multimodulus operation is performed, or the lower counter is a 2 ^n- ary counter (for example, 30 in FIG. 3), or the lower counter has at least a counter stage for decoding an output. It is characterized in that it is a synchronous counter (for example, 32, 33, 34 in FIG. 3).

The frequency dividing counter and the PLL frequency synthesizer are controlled by the control signal from the one-shot circuit.
The +1 modulus operation timing is characterized by being the p + 1 modulus operation timing according to the control signal from the swallow counter and the same operation timing (for example, FIG. 6) of different operation cycles of the lower counter.

(Operation) A single p / p + 1 dual modulus counter is used to perform modulus control for a desired number of times of control at distributed operation timings with p + 1 control as a basic unit, and p / p + 1 / p + 2 / p + 4 Realize multiple multi-modulus (MultiModulus) control as shown in the following, and the bit setting of the modulus control is 2 ⁿ (n = 0,
A multi-modulus prescaler and a frequency division counter capable of setting bits of 1, 2, ... P
By applying it to the LL frequency synthesizer, increase the number of stages of the prescaler without lowering the comparison frequency, that is, lower the operating frequency of the main counter, which is a noise source, and increase the harmonic order of the operating frequency that affects the transmission / reception system. Enables low noise.

[0030]

1 is a block diagram showing an embodiment of a multi-modulus type prescaler, a frequency dividing counter and a PLL frequency synthesizer according to the present invention.

(Description of Configuration) The PLL frequency synthesizer of the present embodiment is a bipolar transistor capable of performing a high-speed switching frequency dividing operation of a frequency division number [p / p + 1 / p + 2 / p + 4] with respect to an RF input signal RFin. Configuration ECL
(Emitter coupled logic) prescaler (Presc
aler) 1 and the output of the prescaler 1 to set C
A main counter (Main-counter) 4 having a CMOS transistor configuration for generating a phase comparison frequency according to H, a 1-shot (1Shot) circuit 3 for controlling p + 1 / p + 2 operation timing of the prescaler 1, and a p + 4 operation of the prescaler 1. Swallow counter (Sw
allow-counter) 2, a phase comparator / charge pump 5 that detects and outputs a phase difference between the reference signal Fref, a loop filter 6 that converts the charge pump output into a smoothed voltage, and the loop filter Voltage controlled oscillator (VCO) 7 that changes the oscillation frequency according to the input voltage of the
It consists of and.

FIG. 2 is a diagram showing an embodiment of a frequency dividing counter constituting the PLL frequency synthesizer of the present invention. A prescaler (Multi Modulus Prescaler) 1 having a frequency division number p / p + 1 / p + 2 / p + 4 and a main counter (Main-counter) 4 for counting the output of the prescaler 1.
And one shot (1Sho) consisting of AND circuits 8 and 9 for controlling the p + 1 / p + 2 operation timing of the prescaler 1.
t) circuit 3 and a swallow-counter for controlling p + 4 operation timing of the prescaler 1
2, the main counter 4 and the swallow counter 2 and the one-shot circuit 3 can set the frequency division numbers, and the setting BIT [m] and the setting BIT, respectively.
As [s], the binary set bit number M and the set bit number S are set via bus data. Here, in the one-shot circuit 3, the lower 1 BIT of the set BIT number S is assigned to the AND circuit 8 that outputs the control signal p + 1 control to the prescaler 1, and the lower 1 BIT of the set BIT number S is assigned to the AND circuit 9 that outputs the control signal p + 2 control. The next lower 2 BITs of the number S are assigned,
The remaining (S-3) BIT is assigned to the swallow counter 2 which outputs the control signal p + 4control.

FIG. 3 is a diagram showing an embodiment of the prescaler of the present invention. Input signal RFin to the clock terminal
Is applied and the inverted output Q is input to the D terminal via the OR circuit 24, and the input signal RFin is input to the clock terminal and the output Q of the D type flip-flop circuit 21 is input to the D terminal. A D-type flip-flop circuit 22 that is input via the OR circuit 25, and a T-type flip-flop circuit 23 that inputs the inverted output Q of the D-type flip-flop circuit 21 to the trigger terminal and outputs the output Q to the OR circuit 25. 4/5 dual modulus counter 20 and a plurality of T-type flip-flop circuits 3 that sequentially input the inverted output Q of the preceding stage to the trigger terminal.
The first stage T-type flip-flop circuit 31 is composed of 1, 32, 33, and 34, and the 2 ^n- ary counter 30 inputs the inverted output Q of the T-type flip-flop circuit 23 to the trigger terminal.
A plurality of control signals p + 1, p + 2, p + 4co for controlling the frequency division number of the 4/5 dual modulus counter 20.
The control circuit 40 is a logic circuit having a control terminal 46 for inputting control. In the present embodiment, the T-type flip-flop circuits 31, 32, 33,
AND circuits 35, 36, and 37 are provided between 34, and each T-type flip-flop circuit is a T-type flip-flop circuit 23.
The synchronous counter structure is configured so as to operate synchronously with the output of the above, and the later-described malfunction due to delay is prevented.

Further, the control circuit 40 controls the control signal p +
1-control and T-type flip-flop circuit 31,
FF8 inverted outputs Q, FF of 32, 33, 34 respectively
16 inversion output Q, FF32 output Q and FF64 output Q
AND circuit 43 that receives as input, control signal p + 2cont
roll and T-type flip-flop circuits 31, 33, 34
FF8 inverted output Q and FF32 inverted output Q
And an AND circuit 44 having the FF64 output Q as an input, an AND circuit 45 having the control signal p + 4control and the FF64 inverted output Q of the T-type flip-flop circuits 31 and 34 as inputs, and the outputs of the AND circuits 43, 44 and 45. It is composed of a NOR circuit 42 for input.

(Explanation of Operation) FIG. 4 is a timing chart showing the operation of the prescaler circuit. The timing chart of the conventional example is shown for comparison with the prescaler of FIG. First, the operation of the prescaler circuit shown in FIG. 3 will be described in detail.

In the time chart shown in FIG. 4, FF
4/5 is the 4/5 dual modulus counter 20
Is a diagram showing the output timing of the D-type flip-flop circuit 21 of FIG. 4, and FF8 to FF64 are diagrams showing the output timing of the T-type flip-flop circuits 31 to 34 of the 2 ^n- ary counter 30, respectively. The operations of the dual modulus counter 20, the 2 ^n- ary counter 30 and the control circuit 40 are as follows.

When the output of the NOR circuit 42 of the control circuit 40 is "H", the inverted output Q- of the D-type flip-flop circuit 22 is always "L". In this state, the D-type flip-flop circuit 21 operates as a T-type flip-flop circuit because only the inverted output Q-is fed back to the D terminal via the OR circuit 24, and thus the input signal RFin is divided by ½. To do. When the output of the NOR circuit 42 is "L", T
The flip-flop circuit 23 is operated by the inverted output Q of the D-type flip-flop circuit 21 every time the OR circuit 2 is operated.
In order to control the logical state of the D terminal of the D-type flip-flop circuit 22 via
Performs 1/2 or 1/3 division operation of the input signal RFin. Therefore, the dual modulus counter 20 operates as a 1/4 frequency division or a 1/5 frequency division, that is, a 4/5 dual modulus counter, by the 1/2 frequency division function of the T-type flip-flop circuit 23.

Next, the 2 ^n- ary counter 30 counts the output of the T-type flip-flop circuit 23, and each stage 31, 3
2, 33 and 34 are the binary output FF8 shown in FIG.
It outputs FF16, FF32, and FF64. Control circuit 4
The AND circuits 43, 44 and 45 of 0 are the 2 ^n- ary counter 3
Since the output of 0 is input by the above-mentioned combination, the operation timing of black painting shown in FIG. 4 is decoded,
When the "H" level control signal (p + 1, p + 2, p + 4control) is input to any of the AND circuits 43, 44, 45, the output is set to "H" level, and the outputs of the AND circuits 43, 44, 45 are input. The output of the NOR circuit 42 becomes "L" level, and at this time, the 4/5 dual modulus counter 20 executes the 1/5 frequency division operation.

Here, the control signal is p + 1 contro
l, p + 2control, p + 4control 3
1/5 of the above for each "H" level
The frequency division operation is performed at the operation timing shown in FIG.
Is executed one or more times depending on the type of the control signal, and it is possible to perform any modulus control of p + 1 / p + 2 / p + 4 different from the modulus control of only p + 1 shown in the conventional example.

FIG. 5 is a diagram showing a timing chart of the main counter and the swallow counter for controlling the prescaler. The timing chart of the conventional example is shown for comparison with the prescaler of FIG. In the figure, the prescaler output (Prescaler out) is the output (FF64) of the T-type flip-flop 64 shown in FIG.
The scale of the time axis is different from that in FIG. Further, the time chart of FIG. 5 shows an example in which the main counter setting value m = 25 and the swallow counter setting value s = 19 as in the conventional example. The operation of the figure is as follows.

As shown in FIG. 5, the main counter (Main
Counter) 4 outputs a pulse signal having a prescaler output one cycle width every 25 counts of the prescaler output (FF64). During the "H" level period of the main counter 4, the AND circuits 8 and 9 control the control signal p + 1 contro
1 and p + 2control are output, and p + 1 shown in FIG.
Modulus control is performed once and twice p + 1 at the operation timings of Modulus and p + 2 Modulus, respectively. In addition, the swallow counter 2 sets the main counter 4 by setting the count of 4 in the output FF 64 of the prescaler 1.
Is set at the timing of the trailing edge of the output of the control signal (“H” level is output), the prescaler output is counted 4 and the control signal p + 4control for returning to the “L” level is output, and the operation timing of p + 4 Module shown in FIG. 4 during this period. At p + 1, the modulus control is performed four times, and this operation is performed over the four prescaler outputs. That is, the output FF for the swallow counter 2 has four cycles of 64 cycles.
At the H "level output, 4 per cycle of the output FF 64
× 4 times of p + 1 modulus control (p + 4 modulus control) is performed. Therefore, 4/5 dual modulus
The counter will perform a 1/5 frequency division operation at all corresponding operation timings within one cycle of the prescaler operation described above, and the p + 1 modulus control is 1 in the prescaler.
A total of + 2 + 4 × 4 (= 19) will be executed.

By the operation of the control circuit 40 as described above,
The 4/5 dual modulus counter has a control signal p +
AND circuit 4 when 1control is at "H" level
When p + 1 modulus control is executed at 1 decode timing of 3 and the control signal p + 2control is at "H" level, p + 2 at 2 decode timing of the AND circuit 44.
Modulus control is executed and control signal p + 4 contro
When l is at "H" level, p + 4 modulus control is executed at 4 decode timings of the AND circuit 45. As can be seen from FIG. 5, according to the present invention, it is possible to reduce the setting of the setting BIT number [m] of the main counter as compared with the conventional example shown in FIGS.

In this embodiment, the swallow counter 2 is set by the output of the main counter 4 as described above, counts the output of the prescaler 1 and outputs the control signal (p
+ 4control) is output, the 1-shot circuit 3 directly uses the output of the main counter 4 and inputs the result of the set values of the lower 1BIT and the lower 2BIT to the AND circuits 8 and 9 respectively. , The control signal (p + 1control, p + 2control) is output, but even if the pulse width of the main counter output is other than the prescaler output one cycle width, one shot operation (monostable operation) is performed at the rising timing. By using a circuit, it is possible to realize the same operation by converting the prescaler output into a signal having a pulse width of one cycle width, and it is also possible to use a swallow counter that outputs a similar control signal. Is.

From the above description, the prescaler circuit shown in FIG. 3 in which a plurality of frequency divisions can be set can be obtained by individually taking the modulus operation timings of p + 1 / p + 2 / p + 4 as shown in the timing chart of FIG. 1
It is clear that the three control signals including the output from the shot circuit allow the prescaler frequency division setting to be controlled independently from p to p + 7.

In the conventional p / p + 1 frequency division prescaler, the ALL of each FF stage output of the 2 ^n- ary counter is used in order to allow a delay margin of each T-type flip-flop (FF) stage output.
Although only the -Low timing (FIGS. 4 and 9) is operated by the modulus (Swallow), in the prescaler circuit of the present invention, the AND circuits 43 and 44 are arranged so as not to lower the operating frequency determined by the first D-FF stage. , 45, the delay margin is ensured by performing the synchronous operation only in the subsequent T-type FF stage for decoding. Further, there is a concern that the delay margin may be deteriorated even for the swallow signal for performing feedback control from the prescaler output through the swallow counter or the like, but in the present invention, the operating frequency itself of the counter system is lowered as compared with the conventional example, so the swallow signal is reduced. The problem of malfunction such as the output of unnecessary signals from the AND circuits 43, 44, 45 due to the signal delay can be suppressed.

Next, the relationship between the number of stages of the prescaler of this embodiment and the number of BITs set for each counter will be described. In the prescaler circuit of this embodiment, p / p + 1
/ P + 2 / p + 4 / ... and multiple moduli (Modulu
s) ECL prescaler circuit that can be set, and the lower B of the added multimodulus setting
A one-shot circuit for IT control, a swallow counter circuit for higher BIT control, and a main counter circuit are provided.

Here, the number of prescaler stages is determined by the sum of the swallow counter setting BIT number and the multi-modulus setting BIT number, whereas the main counter circuit setting BIT number may be greater than or equal to the swallow counter setting BIT number.
Swallow counter setting BIT number = prescaler stage number [p] -multimodulus setting BIT number <main counter setting BIT number [M] ... Formula (3) holds, and even if the prescaler stage number is increased (counter system frequency is lowered), Minute multi-modulus setting B
By increasing the IT number, it is possible to secure the total set BIT number of the swallow counter and the main counter which is limited by the system. The minimum value Total Bit (min) of the total number of set BITs is as shown in FIG.

The concrete operation is 128/129 /
A prescaler capable of 130/132 multi-modulus setting, a 1-shot circuit for independent control of 129/130, and a set BIT number of 5 [1 to 3 for 132 control]
1] Swallow counter and set BIT number 7 [1-12
8] main counter [setting value 100]: total frequency division number N = 12800 (128 * 100) rear ch = 12801 (129 * 1 + 128 * 99) front ch = 12799 (129 * 1 + 130 * 1 + 132)
* 31 + 128 * 66) can be set, and continuous CH can be set.

(Other Embodiments) In the above embodiments, the configuration example in which the p + 1, p + 2 modulus control and the p + 4 modulus control are performed at different operation timings has been shown, but both controls are as shown in FIG. Since it is possible to control the prescaler to be performed in different cycles of the prescaler operation, it is possible to configure both modulo controls to be performed at the same operation timing in each cycle.

FIG. 6 is a diagram showing an embodiment in which the modulus control is performed at the same operation timing. The timing chart of the conventional example is shown for comparison with the prescaler of FIG. In the present embodiment, p
The +1, p + 2 modulus control and p + 4 modulus control are set to operate at the same operation timing after the latter half of the operation of the lower counter, which allows the swallow signal feedback-controlled from the prescaler output via the swallow counter or the like. Even if it is delayed, the delay margin is improved so as to prevent the AND circuits 43, 44, and 45 from outputting signals during the operation cycle of the prescaler that does not perform the modulus control and causing a malfunction.

[0051]

According to the present invention, p / p + 1 / p + 2 / p is realized by a simple counter structure such as a single dual modulus counter and a lower counter such as a 2 ^n- ary counter.
＋4 ・ ・ ・ Multimodulus (MultiMod
It is possible to configure a prescaler that enables the (.ulus) control and the bit setting of the modulus control to be ²ⁿ (n = 0, 1, 2, ...). In addition, a single dual modulus counter uses p + 1 (modulus) control as a basic unit, and multi-modulus control is realized by the number of times that control is performed, and multi-modulus control with a small amount of jitter generation is realized at distributed operation timing. It

According to the present invention, the PLL frequency synthesizer has a prescaler frequency division setting of p / p + 1 / p + 2 / p.
By setting the multi-modulus PLL control that enables multiple controls such as +4, the prescaler setting bit (BIT) can be used without lowering the comparison frequency.
It is possible to increase the number, that is, by lowering the operating frequency of the swallow counter and the main counter, which are usually configured as a CMOS counter and serve as a noise source, it is possible to increase the harmonic order sneaking into the transmission / reception system. A wireless communication transmission / reception system LSI that incorporates a synthesizer, and a fractional (Fracti) that increases the comparison frequency to obtain high-speed lock characteristics.
ONAL) It is possible to reduce the noise of the PLL frequency synthesizer.

According to the present invention, it is possible to perform counter control of an apparent full program (all integer control) capable of setting all CHs with respect to an RF signal inoperable by CMOS by multi-modulus control, and VCO. It is also possible to narrow the channel selection CH interval of wireless communication without lowering the comparison frequency obtained by dividing the output.

[Brief description of drawings]

FIG. 1 is a diagram showing a prescaler, a frequency dividing counter, and a P of the present invention.
It is a figure which shows one Embodiment of LL frequency synthesizer circuit.

FIG. 2 is a diagram showing an embodiment of a frequency division counter of the present invention.

FIG. 3 is a diagram showing an embodiment of a multi-modulus prescaler of the present invention.

FIG. 4 is a timing chart showing the operation of the prescaler of the present embodiment.

FIG. 5 is a timing chart showing operations of a main counter and a swallow counter of the frequency division counter according to the present embodiment.

FIG. 6 is a diagram showing another embodiment of the prescaler of the present invention.

FIG. 7 is a diagram showing a configuration of a conventional PLL frequency synthesizer.

FIG. 8 is a diagram showing a configuration example of a conventional dual-modulus prescaler.

FIG. 9 is a timing chart showing the operation of a conventional prescaler.

FIG. 10 is a diagram showing a timing chart of a conventional main counter and a swallow counter.

FIG. 11 is a diagram showing a prescaler circuit described in JP-A-5-268080.

FIG. 12: 2 described in Japanese Patent Laid-Open No. 2001-44824
It is a figure which shows the frequency divider structure of one prescaler structure.

[Explanation of symbols]

1 Multi-modulus prescaler 2, 12 Swallow counter 3 1-shot circuit 4, 13 Main counter 5, 14 Phase comparator / charge pump circuit 6, 5 Loop filter 7, 16 Voltage controlled oscillator (VCO) 8, 9, 35, 36 , 37, 43, 44, 45 AND circuit 46 Control terminal 11 Dual-modulus prescaler 20, 50 Dual-modulus counter 21, 22, 51, 52 D-type flip-flop 23, 31-34, 53, 61-64 T-type flip-flop 30, 60 Lower counter (binary counter) 40 Control circuit

Claims (14)

[Claims] 1. A p / p + 1 dual modulus counter, a lower counter for counting the output of the p / p + 1 dual modulus counter, and a control for inputting a plurality of control signals for controlling the p / p + 1 dual modulus counter. A terminal and a control circuit for controlling one or more p + 1 modulus operations according to each of the plurality of control signals at a plurality of p + 1 modulus operation timings generated by decoding the output of the lower counter. A prescaler characterized by performing a modulus operation. 2. The prescaler is p / p + 1 / p + 2.
The prescaler according to claim 1, which performs / p + 4 multi-modulus operation. 3. The prescaler according to claim 1, wherein the lower counter is a 2 ^n- ary counter. 4. The prescaler according to claim 1, wherein the lower counter uses a synchronous counter at least in a counter stage for decoding an output. 5. A p / p + 1 dual modulus counter, a lower counter for counting the output of the p / p + 1 dual modulus counter, and a control for inputting a plurality of control signals for controlling the p / p + 1 dual modulus counter. A prescaler comprising: a terminal; and a control circuit for controlling one and a plurality of p + 1 modulus operations corresponding to each of the plurality of control signals at a plurality of p + 1 modulus operation timings generated by decoding the output of the lower counter, A main counter that counts the output of the lower counter, a swallow counter that is set by the output of the main counter and that outputs the control signal that controls the upper bit of the prescaler, and the control signal that controls the lower bit of the prescaler. And a one-shot circuit for A frequency division counter characterized by the above. 6. The prescaler is p / p + 1 / p + 2.
6. The frequency division counter according to claim 5, which performs / p + 4 multi-modulus operation. 7. The frequency ^dividing counter according to claim 5, wherein the lower counter is a 2 ^n- ary counter. 8. The prescaler according to claim 5, wherein at least a counter stage for decoding the output of the lower counter is a synchronous counter. 9. A p signal generated by a control signal from a one-shot circuit.
9. The +1 modulus operation timing is the p + 1 modulus operation timing according to the control signal from the swallow counter, and the same operation timing in different operation cycles of the lower counters.
The described frequency division counter. 10. A phase error signal is generated by comparing a phase difference between a frequency-divided signal obtained by frequency-dividing an output of a voltage controlled oscillator by a frequency dividing counter and a reference signal, and the voltage is generated by a low frequency component of the phase error signal. P that controls the output frequency of the controlled oscillator
In the LL frequency synthesizer, the frequency division counter includes a p / p + 1 dual modulus counter that counts the output of the voltage controlled oscillator, a lower counter that counts the output of the p / p + 1 dual modulus counter, and the p / p + 1. A control terminal for inputting a plurality of control signals for controlling a dual modulus counter, and a plurality of p + 1 modulus operation timings generated by decoding the output of the lower counter, one and a plurality of times corresponding to each of the plurality of control signals. P +
A prescaler having a control circuit for controlling 1-modulus operation, a main counter for counting the output of the lower counter and outputting the frequency-divided signal, and an upper bit of the prescaler set by the output of the main counter, respectively. A PLL frequency synthesizer comprising: a swallow counter that outputs the control signal; and a one-shot circuit that outputs the control signal that controls a lower bit of a prescaler. 11. The PLL frequency synthesizer according to claim 10, wherein the lower counter is a 2 ^n- ary counter. 12. The lower counter is the p / p + 1.
12. A synchronous counter stage for counting the output of a dual modulus counter, comprising:
A PLL frequency synthesizer as described. 13. The prescaler is p / p + 1 / p +.
The PLL frequency synthesizer according to claim 10, 11 or 12, which performs 2 / p + 4 multi-modulus operation. 14. The p + 1 modulus operation timing according to the control signal from the one-shot circuit is the same operation timing as the p + 1 modulus operation timing according to the control signal from the swallow counter and the different operation cycle of the lower counter. Claims 10, 11, 12
Alternatively, the PLL frequency synthesizer according to item 13.