JP2003124454A - Compound semiconductor epitaxial wafer and element using the same - Google Patents

Compound semiconductor epitaxial wafer and element using the same

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Publication number
JP2003124454A
JP2003124454A JP2001318379A JP2001318379A JP2003124454A JP 2003124454 A JP2003124454 A JP 2003124454A JP 2001318379 A JP2001318379 A JP 2001318379A JP 2001318379 A JP2001318379 A JP 2001318379A JP 2003124454 A JP2003124454 A JP 2003124454A
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JP
Japan
Prior art keywords
layer
crystal
compound semiconductor
epitaxial wafer
semiconductor epitaxial
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2001318379A
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Japanese (ja)
Other versions
JP4150879B2 (en
Inventor
Tatsushi Hashimoto
達志 橋本
Mineo Wajima
峰生 和島
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Hitachi Cable Ltd
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Hitachi Cable Ltd
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Abstract

PROBLEM TO BE SOLVED: To enable reduction of crystal defect of a conventional strain- relaxation buffer layer and a burden on a growing device in III-V compound semiconductor epitaxial wafer having an operative region where a substrate crystal and a grating constant are different equal to or greater than 0.15%. SOLUTION: In the III-V compound semiconductor epitaxial wafer having the operative region where the substrate crystal and the grating constant are different equal to or greater than 0.15%, the buffer layer 20 or 200 between the substrate and the operative region is provided with a crystal layer containing Al, Ga, In which has grown through MOVPE technique (ex. InAlGaAs quaternary mixed crystal 111, 121, 131, 141, 151 or 113, 123, 133, 143, 153) and a crystal layer containing Al, In from which difference in the grating constant is within 30% (ex. a layer of InAlAs ternary mixed crystal 112, 122, 132, 142, 152 or 114, 124, 134, 144, 154) in a pair or plural pairs, or in a state that the number of one layer is larger than that of the other.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【発明の属する技術分野】本発明は化合物半導体エピタ
キシャルウェハ及びそれを用いた素子に関するものであ
る。
TECHNICAL FIELD The present invention relates to a compound semiconductor epitaxial wafer and a device using the same.

【0002】[0002]

【従来の技術】III−V族化合物半導体はその材料によ
り、バンドギャップが異なり、その選択や組み合わせに
より現れるヘテロ物性を用いたデバイスの利用が進んで
いる。このヘテロ接合形成に液相エピタキシャル(LP
E)法、分子線エピタキシャル(MBE)法や有機金属
気相エピタキシャル(MOVPE)法等が知られてい
る。
2. Description of the Related Art III-V group compound semiconductors have different band gaps depending on their materials, and devices utilizing hetero-physical properties which appear depending on their selection and combination are being utilized. Liquid phase epitaxial (LP
E) method, molecular beam epitaxy (MBE) method, metal organic vapor phase epitaxy (MOVPE) method and the like are known.

【0003】ここで、材料の個々の化合物の結晶の格子
定数が異なり、エピタキシャル層を成長させると、格子
不整合による応力が発生し、反りや結晶格子の歪みが発
生して諸特性が低下することが良く知られている。唯
一、GaAs/AlGaAsのへテロ系は格子定数差
(△a/a)が0.14%と非常に小さく、混晶比の全
域にわたって利用が進んでいるが、それ以外は2元以上
の混晶にして、GaAsもしくはInP等、基板結晶に
格子整合する混晶組成でのみ、エピタキシャル成長させ
たものが用いられている。従って用いることが出来るヘ
テロ物性が機能的、コスト的に非常に限定されている。
Here, the crystal lattice constants of the individual compounds of the materials are different, and when the epitaxial layer is grown, stress is generated due to lattice mismatch, warpage and distortion of the crystal lattice are generated, and various characteristics are deteriorated. Is well known. Only in the hetero system of GaAs / AlGaAs, the lattice constant difference (Δa / a) is as small as 0.14%, and the utilization is progressing over the entire range of the mixed crystal ratio. As a crystal, a crystal that is epitaxially grown only with a mixed crystal composition such as GaAs or InP that lattice-matches the substrate crystal is used. Therefore, the hetero-physical properties that can be used are very limited in terms of functionality and cost.

【0004】そこで、混晶組み合わせの適用範囲を広げ
るために、格子歪みを含んだ材料系に対して色々な試み
がなされている。
Therefore, in order to expand the range of application of the mixed crystal combination, various attempts have been made on material systems containing lattice distortion.

【0005】第1例として実用化されているものとし
て、FET、HEMTに代表されるユニポーラ型の電子
デバイスがある。この動作層(チャネル層)に電子輸送
特性の優れたInGaAs混晶を用いるため、GaAs
/InGaAs/AlGaAsのヘテロ系でInの組成
を0.2以下で15nm程度以下としてInGaAs層
の格子が格子緩和を起こさない歪んだ状態、いわゆるシ
ュードモフィック構造とする方法が実用化されている。
As a first example, a unipolar type electronic device represented by FET and HEMT is put into practical use. Since an InGaAs mixed crystal with excellent electron transport characteristics is used for this operating layer (channel layer),
A method of making a so-called pseudomorphic structure in which the lattice of the InGaAs layer is in a distorted state where lattice relaxation does not occur by making the In composition 0.2 or less and about 15 nm or less in a hetero system of / InGaAs / AlGaAs is put into practical use.

【0006】第2例には、大きく基板結晶と能動層の格
子定数が違う系、すなわち基板結晶と格子定数が0.1
5%以上異なる動作領域を持つIII−V族化合物半導体
エピタキシャルウェハにおいて、その基板結晶と能動層
(チャネル層)の間に格子緩和を起こさせた後、結晶性
を回復させたバッファ層を介する結晶成長方法がある。
このバッファ層は、メタモルフイックバッファ層(メタ
モルバッファ層)と呼ばれている。メタモルバッファ層
の構造は、結晶基板と能動層(チャネル層)の間のバッ
ファ層で組成を徐々に変える方法や、階段状に変えて行
くなどの方法により、動作層が格子定数差に基づく歪み
の影響を受けにくくする技術が報告されている。
The second example is a system in which the lattice constants of the substrate crystal and the active layer are largely different, that is, the lattice constant of the substrate crystal is 0.1.
In a III-V group compound semiconductor epitaxial wafer having an operation region different by 5% or more, after the lattice relaxation is caused between the substrate crystal and the active layer (channel layer), the crystal through the buffer layer whose crystallinity is restored There is a growth method.
This buffer layer is called a metamorphic buffer layer (metamorphic buffer layer). The structure of the metamorphic buffer layer is such that the composition of the buffer layer between the crystal substrate and the active layer (channel layer) is gradually changed, or the composition is changed in a stepwise manner. Have been reported to reduce the effect of the.

【0007】上記第2例のメタモルバッファ層の結晶成
長方法としては、分子線エピタキシャル(MBE)法が
中心的に行われてきた。その理由として、格子歪みを緩
和させたとき、緩和点を中心として、結晶成長の配向性
や表面平坦性を損なわせないためには低温で成長する必
要があり、特に表面マイグレーションがし易いIII族元
素のIn、Gaを多く含む結晶成長が必要な場合、高温
で成長したとすると3次元成長が起こり平坦な薄い結晶
層が得られにくいため、低温で成長する必要があったた
めである。
A molecular beam epitaxial (MBE) method has been mainly used as a crystal growth method of the metamol buffer layer of the second example. The reason for this is that when the lattice strain is relaxed, it is necessary to grow at a low temperature centering on the relaxation point so as not to impair the orientation of crystal growth and surface flatness. This is because it is necessary to grow at a low temperature because it is difficult to obtain a flat thin crystal layer when three-dimensional growth occurs at a high temperature when crystal growth containing a large amount of the elements In and Ga is required.

【0008】また純度的にも、低温成長で、高純度の化
合物半導体結晶を得るには、原料が高純度単元素金属で
あり、雰囲気が超高真空で、低温で結晶成長可能なMB
E法が用いられてきた。
Also in terms of purity, in order to obtain a high-purity compound semiconductor crystal by low-temperature growth, MB is a raw material of high-purity single-element metal, the atmosphere is ultra-high vacuum, and the crystal can be grown at a low temperature.
Method E has been used.

【0009】[0009]

【発明が解決しようとする課題】しかしながら、上記M
BE法は、作業者に対する安全性は高いものの、生産装
置としては大きな欠点がある。それは、結晶成長に必要
な超高真空を得るためのメンテナンスに要する時間が長
い、トラブルに対する装置の安定性に欠ける等である。
さらにV族原料が実用的にはAsのみに限られること、
大面積の成長装置の実現に対して極端に装置コストが上
がってしまうこと等である。
However, the above-mentioned M
The BE method is highly safe for workers, but has a serious drawback as a production apparatus. That is, it takes a long time to perform maintenance for obtaining the ultra-high vacuum necessary for crystal growth, lack of stability of the apparatus against troubles, and the like.
Further, the group V raw material is practically limited to only As,
For example, the cost of the device will be extremely high for the realization of a large-area growth device.

【0010】一方、生産に関して、最近は、有機金属気
相エピタキシャル(MOVPE:metal organic vapor
phase epitaxy)法が多く用いられるようになってき
た。ただし、歪を含む結晶成長に関して、MOVPE法
は原料の有機物、水素化物の分解反応が伴うため、MB
E法に比して成長温度が高くなってしまい、メタモルバ
ッファ層の成長に向かないと考えられていた。
On the other hand, regarding production, recently, metal-organic vapor phase epitaxial (MOVPE)
The phase epitaxy method has come into wide use. However, with respect to crystal growth including strain, the MOVPE method involves decomposition reaction of raw material organic substances and hydrides.
It was thought that the growth temperature was higher than that of the E method, and it was not suitable for the growth of the metamol buffer layer.

【0011】これに対し、本発明者等はバッファ層に関
してInAlAsを採用し、成長条件によっては、逆に
成長温度が高いほうが、良好な表面を得られることを見
出し、良好な表面状態が得られるようにしてきた。
On the other hand, the present inventors have adopted InAlAs for the buffer layer, and found that a higher growth temperature gives a better surface depending on the growth conditions, and a good surface condition can be obtained. I've been doing so.

【0012】しかしながら、このInAlAsの3元混
晶バッファ層は、例えばInの組成が0.1と低い場
合、残ったAlの組成が0.9と非常に高くなってしま
い、プロセスに対する耐久性がなくなったり、デバイス
の信頼性が低下する恐れが生じている。またその成長条
件がMO成長装置に対しては非常につらく、前後の成長
層の成長にも悪影響を与えていた。
However, in the InAlAs ternary mixed crystal buffer layer, when the In composition is as low as 0.1, the remaining Al composition becomes as high as 0.9, and the durability to the process is high. There is a risk that the device will be lost or the reliability of the device will be reduced. Further, the growth conditions are very difficult for the MO growth apparatus, and the growth of the front and rear growth layers is also adversely affected.

【0013】そこで、本発明の目的は、基板結晶と格子
定数が0.15%以上異なる動作領域を持つIII−V族
化合物半導体エピタキシャルウェハにおいて、上記した
従来の歪緩和バッファ層の結晶の欠点と、成長装置の負
担を低減すること、そのために、表面の平坦度が良好で
かつ低温成長することのできる歪緩和バッファ層とする
ことにある。
Therefore, an object of the present invention is to solve the above-mentioned drawback of the conventional crystal of the strain relaxation buffer layer in the III-V group compound semiconductor epitaxial wafer having an operation region having a lattice constant different from that of the substrate crystal by 0.15% or more. The purpose is to reduce the load on the growth apparatus, and for that reason, to provide a strain relaxation buffer layer having good surface flatness and capable of low temperature growth.

【0014】[0014]

【課題を解決するための手段】上記目的を達成するた
め、本発明は、次のように構成したものである。
In order to achieve the above object, the present invention is configured as follows.

【0015】請求項1の発明に係る化合物半導体エピタ
キシャルウェハは、基板結晶と格子定数が0.15%以
上異なる動作領域を持つIII−V族化合物半導体エピタ
キシャルウェハにおいて、基板と動作領域の間のバッフ
ァ層にMOVPE法により成長したAl、Ga、Inを
有する結晶層とその層と格子定数差が30%以内のA
l、Inを有する結晶層を一組もしくは複数組又はどち
らかの層が多い状態で設けたことを特徴とする。
A compound semiconductor epitaxial wafer according to a first aspect of the present invention is a III-V compound semiconductor epitaxial wafer having an operation region having a lattice constant different from that of a substrate crystal by 0.15% or more, and a buffer between the substrate and the operation region. A layer having a crystal constant difference of 30% or less between the crystal layer containing Al, Ga and In grown by the MOVPE method and the layer.
It is characterized in that one set or a plurality of sets of crystal layers containing l and In are provided in a state where there are many layers.

【0016】本発明は、例えば、基板結晶と格子定数が
0.15%以上異なる動作領域を持つIII−V族化合物
半導体エピタキシャルウェハにおいて、バッファ層全部
もしくは一部にInAlGaAs4元混晶とInAlA
s3元混晶を1組もしくはそれ以上交互に設け、これに
より、表面の平坦度が良好で、且つ低温成長することの
できる歪緩和バッファ層を備えた構造とするものであ
る。従って、電解効果トランジスタ(FET、HEMT
等)又はバイポーラトランジスタ(HBT等)用の化合
物半導体エピタキシャルウェハにおいて、上記した従来
の歪緩和バッファ層の結晶の欠点と、成長装置の負担を
低減することができる。
According to the present invention, for example, in a III-V group compound semiconductor epitaxial wafer having an operating region having a lattice constant different from that of a substrate crystal by 0.15% or more, InAlGaAs quaternary mixed crystal and InAlA are used in all or part of the buffer layer.
One set or more sets of s3 ternary mixed crystals are alternately provided, whereby a structure having a strain relaxation buffer layer having good surface flatness and capable of low temperature growth is provided. Therefore, the field effect transistor (FET, HEMT
Etc.) or a compound semiconductor epitaxial wafer for a bipolar transistor (HBT etc.), it is possible to reduce the above-mentioned defects of the crystal of the strain relaxation buffer layer and the burden on the growth apparatus.

【0017】請求項2の発明は、請求項1記載の化合物
半導体エピタキシャルウェハにおいて、動作領域の構造
が電解効果トランジスタ又はバイポーラトランジスタの
構造であることを特徴とする。
According to a second aspect of the invention, in the compound semiconductor epitaxial wafer according to the first aspect, the structure of the operation region is a structure of a field effect transistor or a bipolar transistor.

【0018】請求項3の発明に係る化合物半導体素子
は、請求項2記載の化合物半導体エピタキシャルウェハ
を用い、これにフォトリソグラフィやエッチング等を施
した後、電極を設けて、電解効果トランジスタ又はバイ
ポーラトランジスタとして構成したことを特徴とする。
A compound semiconductor device according to a third aspect of the present invention uses the compound semiconductor epitaxial wafer according to the second aspect, and after subjecting the compound semiconductor epitaxial wafer to photolithography, etching, etc., an electrode is provided to the field effect transistor or the bipolar transistor. It is characterized by being configured as.

【0019】[0019]

【発明の実施の形態】以下、本発明の実施形態を図示の
実施例に基づいて説明する。
BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to illustrated examples.

【0020】(実施例1)本発明の第1の実施例とし
て、InGaAsチャンネル層のIn組成が0.4のI
nAlAs/InGaAs/InAlAsヘテロ構造を
もつHEMT用エピタキシャルウェハの結晶成長につい
て示す。
(Embodiment 1) As a first embodiment of the present invention, the In composition of the InGaAs channel layer is 0.4 I.
The crystal growth of an HEMT epitaxial wafer having an nAlAs / InGaAs / InAlAs heterostructure is shown.

【0021】図1はHEMT構造の半導体エピタキシャ
ルウェハの断面概略図である。MOVPE装置により、
半絶縁性GaAs基板1に基板温度550℃でアンドー
プGaAsバッファ層2を20nm成長し、In
0.15(Ga0.5Al0.50.85Asバッファ層111を5
0nm、続けてIn0.15Al0.85Asバッファ層112
を50nm、続けてIn0.23(Ga0.3Al0.70.77
sアンドープ層121を50nm、続けてIn0.23Al
0.77Asアンドープ層122を50nm、In0.30(G
0.15Al0.850.70Asアンドープ層131を50n
m、In0.30Al0.70Asアンドープ層132を50n
m、In0.35(Ga0.15Al0.850.65Asアンドープ
層141を50nm、In0.35Al0.65Asアンドープ
層142を50nm、In0.40(Ga0.15Al0.85
0.60Asアンドープ層151を50nm、In0.40Al
0.60Asアンドープクラッド層152を100nm、S
iドープ(ドーピング濃度5×1018の/cm3)In
0.40Al0.60Asキャリア供給層21を5nm、In
0.40Al0.60Asスペーサ層22を2nm、In0.41
0.59Asチャネル層23を30nm、In0.40Al
0.60Asスペーサ層24を2nm、Siドープ(ドーピ
ング濃度5×1018/cm3)In0.40Al0.60Asキャ
リア供給層25を12nm、In0.40Al0.60Asアン
ドープショットキー層26を30nm、Siドープ(ド
ーピング濃度5×1018/cm3)In0.41Ga0.59As
からIn0.50Ga0.50Asにリニアに組成を変化させた
コンタクト層31を50nm、そしてSiドープ(ドー
ピング濃度5×1018/cm3)In0.50Ga0.50As
コンタクト層32を50nm、MOVPE法で順次、エ
ピタキシャル成長した。
FIG. 1 is a schematic sectional view of a semiconductor epitaxial wafer having a HEMT structure. With the MOVPE device,
An undoped GaAs buffer layer 2 was grown to a thickness of 20 nm on a semi-insulating GaAs substrate 1 at a substrate temperature of 550 ° C.
0.15 (Ga 0.5 Al 0.5 ) 0.85 As buffer layer 111 5
0 nm, followed by In 0.15 Al 0.85 As buffer layer 112
Of 50 nm, followed by In 0.23 (Ga 0.3 Al 0.7 ) 0.77 A
s undoped layer 121 to 50 nm, followed by In 0.23 Al
0.77 As undoped layer 122 with 50 nm, In 0.30 (G
a 0.15 Al 0.85 ) 0.70 As undoped layer 131
m, In 0.30 Al 0.70 As undoped layer 132 to 50 n
m, In 0.35 (Ga 0.15 Al 0.85 ) 0.65 As undoped layer 141 at 50 nm, In 0.35 Al 0.65 As undoped layer 142 at 50 nm, In 0.40 (Ga 0.15 Al 0.85 ).
0.60 As undoped layer 151 with 50 nm, In 0.40 Al
0.60 As undoped cladding layer 152 with 100 nm, S
i-doped (doping concentration 5 × 10 18 / cm 3 ) In
0.40 Al 0.60 As carrier supply layer 21 with 5 nm, In
0.40 Al 0.60 As spacer layer 22 of 2 nm, In 0.41 G
a 0.59 As channel layer 23 of 30 nm, In 0.40 Al
0.60 As spacer layer 24 is 2 nm, Si-doped (doping concentration 5 × 10 18 / cm 3 ) In 0.40 Al 0.60 As carrier supply layer 25 is 12 nm, In 0.40 Al 0.60 As undoped Schottky layer 26 is 30 nm, Si-doped (doping) Concentration 5 × 10 18 / cm 3 ) In 0.41 Ga 0.59 As
To In 0.50 Ga 0.50 As with a contact layer 31 having a linear composition change of 50 nm, and Si-doped (doping concentration 5 × 10 18 / cm 3 ) In 0.50 Ga 0.50 As
The contact layer 32 was epitaxially grown in order of 50 nm by MOVPE method.

【0022】上記したIn0.15(Ga0.5Al0.50.85
Asバッファ層111、In0.15Al0.85Asバッファ
層112、In0.23(Ga0.3Al0.70.77Asアンド
ープ層121、In0.23Al0.77Asアンドープ層12
2、In0.30(Ga0.15Al 0.850.70Asアンドープ
層131、In0.30Al0.70Asアンドープ層132、
In0.35(Ga0.15Al0.850.65Asアンドープ層1
41、In0.35Al0. 65Asアンドープ層142、In
0.40(Ga0.15Al0.850.60Asアンドープ層15
1、In0.40Al0.60Asアンドープクラッド層152
は、格子不整合系の歪緩和バッファ層20を構成してい
る。この歪緩和バッファ層20は、格子定数のほぼ同じ
InAlGaAs層とInAlAs層を一組とし、これ
を5組設け、その各組のIn混晶比を半絶縁性GaAs
基板1の側から0.15、0.23、0.30、0.3
5、0.40と、徐々に上げたものから成る。膜厚は、
SiドープIn0.40Al0.60Asキャリア供給層21の
直下のIn0.40Al0.60Asアンドープ層152が10
0nmである点を除き、他のInAlGaAs層11
1、121、131、141、151及びInAlAs
層112、122、132、142は同じ50nmであ
る。
In described above0.15(Ga0.5Al0.5)0.85
As buffer layer 111, In0.15Al0.85As buffer
Layer 112, In0.23(Ga0.3Al0.7)0.77As and
Layer 121, In0.23Al0.77As undoped layer 12
2, In0.30(Ga0.15Al 0.85)0.70As undoped
Layer 131, In0.30Al0.70As undoped layer 132,
In0.35(Ga0.15Al0.85)0.65As undoped layer 1
41, In0.35Al0. 65As undoped layer 142, In
0.40(Ga0.15Al0.85)0.60As undoped layer 15
1, In0.40Al0.60As undoped cladding layer 152
Constitute the lattice-mismatched strain relaxation buffer layer 20.
It The strain relaxation buffer layer 20 has almost the same lattice constant.
A pair of InAlGaAs layer and InAlAs layer,
5 sets, and the In mixed crystal ratio of each set is set to semi-insulating GaAs.
0.15, 0.23, 0.30, 0.3 from the substrate 1 side
It is composed of gradually increased values of 5, 0.40. The film thickness is
Si-doped In0.40Al0.60As carrier supply layer 21
Immediately below In0.40Al0.60As undoped layer 152 is 10
Other InAlGaAs layers 11 except that the thickness is 0 nm
1, 121, 131, 141, 151 and InAlAs
The layers 112, 122, 132, 142 have the same 50 nm
It

【0023】このようにして形成した格子不整合系の化
合物半導体多層薄膜から成る歪緩和バッファ層20を具
備する化合物半導体エピタキシャルウェハについて、そ
のHEMT構造の半導体結晶の電気的特性をホール効果
測定法により求めた。その結果、電子移動度は8.90
0cm2/V・sと下地層のn−GaAs層の影響を受け
てやや小さくなったが、シートキャリア濃度については
4.8×1012/cm2と大幅に増加させることができ
た。
With respect to the compound semiconductor epitaxial wafer having the strain relaxation buffer layer 20 composed of the lattice mismatched compound semiconductor multilayer thin film thus formed, the electrical characteristics of the semiconductor crystal having the HEMT structure are measured by the Hall effect measuring method. I asked. As a result, the electron mobility was 8.90.
The sheet carrier concentration was 0 cm 2 / Vs, which was slightly smaller due to the influence of the n-GaAs layer as the underlayer, but the sheet carrier concentration could be significantly increased to 4.8 × 10 12 / cm 2 .

【0024】上記の実施例では、格子定数のほぼ同じI
nAlGaAs層とInAlAs層を一組として計5組
設けたものを説明したが、複数同士を一組とするものを
複数組設けても良く、どちらかの層が多くても構わな
い。またスペーサ層直下の層はバンドギャップの大きい
3元のInAlAs層の方が良いが、InGaAlAs
層であっても構わない。
In the above embodiment, I having almost the same lattice constant is used.
Although a total of five nAlGaAs layers and InAlAs layers have been described, a plurality of groups each having a plurality of nAlGaAs layers may be provided, and either of the layers may be large. The layer immediately below the spacer layer is preferably a ternary InAlAs layer having a large band gap, but InGaAlAs
It may be a layer.

【0025】(実施例2)次に、第2の実施例として、
InGaAsチャンネル層のIn組成が0.4のInG
aAs/InGaAs/InGaPへテロ構造をもつH
BT用エピタキシャルウェハの結晶成長について示す。
(Embodiment 2) Next, as a second embodiment,
InG in which the In composition of the InGaAs channel layer is 0.4
aAs / InGaAs / InGaP H with heterostructure
The crystal growth of the BT epitaxial wafer will be described.

【0026】図2はこの第2の実施例に係るHBT構造
のエピタキシャルウェハの断面図である。
FIG. 2 is a sectional view of an epitaxial wafer having an HBT structure according to the second embodiment.

【0027】MOVPE装置により、半絶縁性GaAs
基板1に基板温度550℃でアンドープGaAsバッフ
ァ層2を20nm成長し、In0.15(Ga0.5Al0.5
0.85As層113を100nm、続けてIn0.15Al
0.85As層114を100nm、続けてIn0.23(Ga
0.3Al0.70.77Asアンドープ層123を100n
m、続けてIn0.23Al0.77Asアンドープ層124を
100nm、In0.30(Ga0.15Al0.850.70Asア
ンドープ層133を100nm、In0.30Al0.70As
アンドープ層134を100nm、In0.35(Ga0.15
Al0.850.65Asアンドープ層143を100nm、
In0.35Al0.65Asアンドープ層144を100n
m、In0.40(Ga0.15Al0.850.60Asアンドープ
層153を50nm、In0.40Al0.60Asアンドープ
層154を100nm、キャリア濃度5×l018/cm3
のIn0.40Ga0.60Asサブコレクタ層212を500
nm、キャリア濃度3×l016/cm3 のIn0.40Ga
0.60Asコレクタ層222を800nm、キャリア濃度
4×l019/cm3のp型In0.40Ga0.60Asベース
層223を150nm、キャリア濃度5×l017/cm
3 のIn0.40Al0.60Asエミッタ層231を80n
m、キャリア濃度2×l018/cm3 のInAlAsキ
ャップ層232を100nm、ドービング濃度5×l0
18/cm3 のIn0.41Ga0.59AsからIn0.50Ga
0.50Asにリニアに組成を変化させたコンタクト層24
1を50nm、ドーピング濃度5×l018/cm3 のI
0.50Ga0.50Asコンタクト層242を50nmを成
長した。
Semi-insulating GaAs by MOVPE device
An undoped GaAs buffer layer 2 was grown to a thickness of 20 nm on the substrate 1 at a substrate temperature of 550 ° C., and In 0.15 (Ga 0.5 Al 0.5 )
0.85 As layer 113 of 100 nm, followed by In 0.15 Al
0.85 As layer 114 of 100 nm, followed by In 0.23 (Ga
0.3 Al 0.7 ) 0.77 As Undoped layer 123 100 n
m, followed by In 0.23 Al 0.77 As undoped layer 124 of 100 nm, In 0.30 (Ga 0.15 Al 0.85 ) 0.70 As undoped layer 133 of 100 nm, In 0.30 Al 0.70 As
The undoped layer 134 is formed with 100 nm, In 0.35 (Ga 0.15
Al 0.85 ) 0.65 As undoped layer 143 of 100 nm,
In 0.35 Al 0.65 As undoped layer 144 of 100 n
m, In 0.40 (Ga 0.15 Al 0.85 ) 0.60 As undoped layer 153 of 50 nm, In 0.40 Al 0.60 As undoped layer 154 of 100 nm, carrier concentration 5 × 10 18 / cm 3
Of In 0.40 Ga 0.60 As subcollector layer 212 of
nm, carrier concentration 3 × 10 16 / cm 3 In 0.40 Ga
0.60 As collector layer 222 is 800 nm, p-type In 0.40 Ga 0.60 As base layer 223 having a carrier concentration of 4 × 10 19 / cm 3 is 150 nm, carrier concentration is 5 × 10 17 / cm 3.
3 of In 0.40 Al 0.60 As emitter layer 231 80n
m, carrier concentration 2 × 10 18 / cm 3 of InAlAs cap layer 232 of 100 nm, doving concentration 5 × 10
18 / cm 3 of In 0.41 Ga 0.59 As to In 0.50 Ga
Contact layer 24 with composition changed linearly to 0.50 As
1 with 50 nm and a doping concentration of 5 × 10 18 / cm 3
An n 0.50 Ga 0.50 As contact layer 242 was grown to a thickness of 50 nm.

【0028】上記したIn0.15(Ga0.5Al0.50.85
As層113、In0.15Al0.85As層114、In
0.23(Ga0.3Al0.70.77Asアンドープ層123、
In0. 23Al0.77Asアンドープ層124、In
0.30(Ga0.15Al0.850.70Asアンドープ層13
3、In0.30Al0.70Asアンドープ層134、In
0.35(Ga 0.15Al0.850.65Asアンドープ層14
3、In0.35Al0.65Asアンドープ層144、In
0.40(Ga0.15Al0.850.60Asアンドープ層15
3、及びIn0.40Al0.60Asアンドープ層154は、
格子不整合系の歪緩和バッファ層200を構成してい
る。この歪緩和バッファ層200は、格子定数のほぼ同
じInGaAlAs層とInAlAs層を一組とし、こ
れを5組設け、その各組のIn混晶比を半絶縁性GaA
s基板1の側から0.15、0.23、0.30、0.
35、0.40と、徐々に上げたものから成る。膜厚
は、In0.04Al0.60Asアンドープ層154の直下の
In0.40(Ga0.15Al0.85)0.60Asアンドープ層153が
100nmである点を除き、他のInAlGaAs層1
13、123、133、143、及びInAlAs層1
14、124、134、144、154は同じ100n
mである。
In described above0.15(Ga0.5Al0.5)0.85
As layer 113, In0.15Al0.85As layer 114, In
0.23(Ga0.3Al0.7)0.77As undoped layer 123,
In0. twenty threeAl0.77As undoped layer 124, In
0.30(Ga0.15Al0.85)0.70As undoped layer 13
3, In0.30Al0.70As undoped layer 134, In
0.35(Ga 0.15Al0.85)0.65As undoped layer 14
3, In0.35Al0.65As undoped layer 144, In
0.40(Ga0.15Al0.85)0.60As undoped layer 15
3, and In0.40Al0.60The As undoped layer 154 is
The strain mitigating buffer layer 200 of the lattice mismatch system is formed.
It The strain relaxation buffer layer 200 has almost the same lattice constant.
The same InGaAlAs layer and InAlAs layer are combined as
Five sets of these are provided, and the In mixed crystal ratio of each set is set to semi-insulating GaA.
0.15, 0.23, 0.30, 0.
35, 0.40 and gradually increased. Film thickness
Is In0.04Al0.60Immediately below the As undoped layer 154
In0.40 (Ga0.15Al0.85) 0.60As undoped layer 153
Other InAlGaAs layers 1 except 100 nm
13, 123, 133, 143, and InAlAs layer 1
14,124,134,144,154 are the same 100n
m.

【0029】この実施例のヘテロバイポーラトランジス
タのnpn界面のIn組成は0.40で設計したが、い
かなるIn組成であっても、本発明の効果があった。
The In composition of the npn interface of the hetero-bipolar transistor of this embodiment was designed to be 0.40, but any In composition provided the effect of the present invention.

【0030】次に、上記第1及び第2の実施形態に係る
化合物半導体エピタキシャルウェハを用い、これにフォ
トリソグラフィやエッチング等を施した後、電極を設け
て製作されたHEMT、HBTデバイスは、増幅率、最
大動作周波数fmaxを大幅に増加でき、特にHBTに関
してはターンオン電圧を下げることが出来、大幅に性能
を向上することができた。
Next, the HEMT and HBT devices manufactured by using the compound semiconductor epitaxial wafers according to the first and second embodiments and subjecting the compound semiconductor epitaxial wafers to photolithography, etching, etc., and then providing the electrodes are amplified. The rate and the maximum operating frequency fmax could be greatly increased, and especially for the HBT, the turn-on voltage could be lowered and the performance could be greatly improved.

【0031】[0031]

【発明の効果】以上説明したように本発明によれば、次
のような優れた効果が得られる。
As described above, according to the present invention, the following excellent effects can be obtained.

【0032】本発明は、基板結晶と格子定数が0.15
%以上異なる動作領域を持つIII−V族化合物半導体エ
ピタキシャルウェハにおいて、基板と動作領域の間のバ
ッファ層にMOVPE法により成長したAl、Ga、I
nを有する結晶層とその層と格子定数差が30%以内の
Al、Inを有する結晶層を一組もしくは複数組又はど
ちらかの層が多い状態で設けた構成であり、例えば、バ
ッファ層全部もしくは一部にInAlGaAs4元混晶
とInAlAs3元混晶を1組もしくはそれ以上交互に
積層したものである。
The present invention has a lattice constant of 0.15 with the substrate crystal.
% Of Al, Ga, I grown on the buffer layer between the substrate and the operating region by the MOVPE method in the III-V group compound semiconductor epitaxial wafer having the operating region different by more than 1%.
The crystal layer having n and the crystal layer having Al and In having a lattice constant difference of 30% or less from the crystal layer having n are provided in one set or a plurality of sets or in a state in which either of the layers is large. Alternatively, one set or more of InAlGaAs quaternary mixed crystal and InAlAs ternary mixed crystal are alternately laminated in part.

【0033】かかる構成とすることによって、表面の平
坦度が良好な歪緩和バッファ層をMOVPE法により低
温で成長することができ、電解効果トランジスタ(FE
T、HEMT等)又はバイポーラトランジスタ(HBT
等)用の化合物半導体エピタキシャルウェハを容易に得
ることができる。従って、本発明によれば、従来の格子
不整合系における歪緩和バッファ層の結晶の欠点と、成
長装置の負担を低減することができる。
With this structure, the strain relaxation buffer layer having a good surface flatness can be grown at a low temperature by the MOVPE method, and the field effect transistor (FE) can be formed.
T, HEMT, etc.) or bipolar transistor (HBT)
And the like) can be easily obtained. Therefore, according to the present invention, it is possible to reduce the defect of the crystal of the strain relaxation buffer layer in the conventional lattice mismatch system and the burden on the growth apparatus.

【0034】また、本発明の化合物半導体エピタキシャ
ルウェハを用いて製作されたHEMT、HBTデバイス
は、増幅率、最大動作周波数fmaxを大幅に増加するこ
とができ、特にHBTに関してはターンオン電圧を下げ
ることができ、大幅に性能を向上することができる。
Further, in the HEMT and HBT devices manufactured by using the compound semiconductor epitaxial wafer of the present invention, the amplification factor and the maximum operating frequency fmax can be greatly increased, and especially for HBT, the turn-on voltage can be lowered. The performance can be improved significantly.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の一実施例に係るHEMTの層構造を持
つ化合物半導体エピタキシャルウェハの断面図である。
FIG. 1 is a cross-sectional view of a compound semiconductor epitaxial wafer having a HEMT layer structure according to an embodiment of the present invention.

【図2】本発明の一実施例に係るHBTの層構造を持つ
化合物半導体エピタキシャルウェハの断面図である。
FIG. 2 is a cross-sectional view of a compound semiconductor epitaxial wafer having an HBT layer structure according to an embodiment of the present invention.

【符号の説明】[Explanation of symbols]

1 半絶縁性GaAs基板 2 GaAsバッファ層 20 歪緩和バッファ層 21 SiドープIn0.40Al0.60Asキャリア供給層 22 In0.40Al0.60Asスペーサ層 23 In0.41Ga0.59Asチャネル層 24 In0.40Al0.60Asスペーサ層 25 SiドープIn0.40Al0.60Asキャリア供給層 26 In0.40Al0.60Asアンドープショットキー層 31 SiドープIn0.41Ga0.59AsからIn0.50
0.50Asにリニアに組成を変化させたコンタクト層 32 In0.50Ga0.50As0.85コンタクト層 111 In0.15(Ga0.5Al0.50.85Asバッファ
層 112 In0.15Al0.85Asバッファ層 113 In0.15(Ga0.5Al0.50.85Asバッファ
層 114 In0.15Al0.85Asバッファ層 121 In0.23(Ga0.3Al0.7)0.77Asアン
ドープ層 122 In0.23Al0.77Asアンドープ層 123 In0.23(Ga0.3Al0.7)0.77Asアン
ドープ層 124 In0.23Al0.77Asアンドープ層 131 In0.30(Ga0.15Al0.850.70Asア
ンドープ層 132 In0.30Al0.70Asアンドープ層 133 In0.30(Ga0.15Al0.850.70Asア
ンドープ層 134 In0.30Al0.70Asアンドープ層 141 In0.35(Ga0.15Al0.850.65Asアンド
ープ層 142 In0.35Al0.65Asアンドープ層 143 In0.35(Ga0.15Al0.850.65Asアンド
ープ層 144 In0.35Al0.65Asアンドープ層 151 In0.40(Ga0.15Al0.850.60Asアンド
ープ層 152 In0.40Al0.60Asアンドープ層 153 In0.40(Ga0.15Al0.850.60Asアンド
ープ層 154 In0.40Al0.60Asアンドープ層 200 歪緩和バッファ層 212 In0.40Ga0.60Asサブコレクタ層 222 In0.40Ga0.60Asコレクタ層 223 p型In0.40Ga0.60Asベース層 231 In0.40Al0.60Asエミッタ層 232 InAlAsキャップ層 241 In0.41Ga0.59AsからIn0.50Ga0.50
sにリニアに組成を変化させたコンタクト層 242 In0.50Ga0.50Asコンタクト層
1 semi-insulating GaAs substrate 2 GaAs buffer layer 20 strain relaxation buffer layer 21 Si-doped In 0.40 Al 0.60 As carrier supply layer 22 In 0.40 Al 0.60 As spacer layer 23 In 0.41 Ga 0.59 As channel layer 24 In 0.40 Al 0.60 As spacer layer 25 Si-doped In 0.40 Al 0.60 As carrier supply layer 26 In 0.40 Al 0.60 As undoped Schottky layer 31 Si-doped In 0.41 Ga 0.59 As to In 0.50 G
a 0.50 As linear contact layer 32 In 0.50 Ga 0.50 As 0.85 contact layer 111 In 0.15 (Ga 0.5 Al 0.5 ) 0.85 As buffer layer 112 In 0.15 Al 0.85 As buffer layer 113 In 0.15 (Ga 0.5 Al) 0.5 ) 0.85 As buffer layer 114 In 0.15 Al 0.85 As buffer layer 121 In 0.23 (Ga 0.3 Al 0.7 ) 0.77 As undoped layer 122 In 0.23 Al 0.77 As undoped layer 123 In 0.23 (Ga 0.3 Al 0.7 ) 0.77 As undoped layer 124 In 0.23 Al 0.77 As undoped layer 131 In0.30 (Ga 0.15 Al 0.85 ) 0.70 As undoped layer 132 In0.30 Al 0.70 As undoped layer 133 In0.30 (Ga 0.15 Al 0.85 ) 0.70 As undoped layer 134 In0.30 Al 0.70 As Undoped layer 141 In 0.35 (Ga 0.15 Al 0.85 ) 0.65 As undoped layer 142 In 0.35 Al 0.65 As undoped layer 143 In 0.35 (Ga 0.15 Al 0.85 ) 0.65 As undoped layer 144 In 0.35 Al 0.65 As undoped layer 151 In 0.40 (Ga 0.15 Al 0.85 ) 0.60 As undoped layer 152 In 0.40 Al 0.60 As undoped layer 153 In 0.40 (Ga 0.15 Al 0.85 ) 0.60 As undoped layer 154 In 0.40 Al 0.60 As undoped layer 200 Strain relaxation buffer layer 212 In 0.40 Ga 0.60 As subcollector layer 222 In 0.40 Ga 0.60 As collector layer 223 p-type In 0.40 Ga 0.60 As base layer 231 In 0.40 Al 0.60 As emitter layer 232 InAlAs cap layer 241 In 0.41 Ga 0.59 As to In 0.50 Ga 0.50 A
Contact layer 242 In 0.50 Ga 0.50 As contact layer whose composition is changed linearly to s

───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.7 識別記号 FI テーマコート゛(参考) H01L 29/778 29/812 Fターム(参考) 5F003 BF06 BM03 BP32 5F045 AA04 AB10 AB17 AB18 AD09 AF04 BB07 BB16 CA01 CA07 DA52 DA53 5F102 GB01 GC01 GD01 GJ05 GK05 GK06 GK08 GL04 GM04 GM08 GQ03 HC01 ─────────────────────────────────────────────────── ─── Continuation of front page (51) Int.Cl. 7 Identification code FI theme code (reference) H01L 29/778 29/812 F term (reference) 5F003 BF06 BM03 BP32 5F045 AA04 AB10 AB17 AB18 AD09 AF04 BB07 BB16 CA01 CA07 DA52 DA53 5F102 GB01 GC01 GD01 GJ05 GK05 GK06 GK08 GL04 GM04 GM08 GQ03 HC01

Claims (3)

【特許請求の範囲】[Claims] 【請求項1】基板結晶と格子定数が0.15%以上異な
る動作領域を持つIII−V族化合物半導体エピタキシャ
ルウェハにおいて、基板と動作領域の間のバッファ層に
MOVPE法により成長したAl、Ga、Inを有する
結晶層とその層と格子定数差が30%以内のAl、In
を有する結晶層を一組もしくは複数組又はどちらかの層
が多い状態で設けたことを特徴とする化合物半導体エピ
タキシャルウェハ。
1. A III-V group compound semiconductor epitaxial wafer having an operating region having a lattice constant different from that of a substrate crystal by 0.15% or more. Al, Ga grown by a MOVPE method in a buffer layer between the substrate and the operating region. Crystal layer having In and Al, In having a lattice constant difference of 30% or less between the crystal layer and In layer
A compound semiconductor epitaxial wafer, characterized in that one or a plurality of sets of crystal layers having the above are provided in a state in which there are many layers.
【請求項2】請求項1記載の化合物半導体エピタキシャ
ルウェハにおいて、動作領域の構造が電解効果トランジ
スタ又はバイポーラトランジスタの構造であることを特
徴とする化合物半導体エピタキシャルウェハ。
2. The compound semiconductor epitaxial wafer according to claim 1, wherein the structure of the operation region is a structure of a field effect transistor or a bipolar transistor.
【請求項3】請求項2記載の化合物半導体エピタキシャ
ルウェハを用い、これにフォトリソグラフィやエッチン
グ等を施した後、電極を設けて、電解効果トランジスタ
又はバイポーラトランジスタとして構成したことを特徴
とする化合物半導体素子。
3. A compound semiconductor, comprising the compound semiconductor epitaxial wafer according to claim 2, wherein the compound semiconductor epitaxial wafer is subjected to photolithography, etching, etc., and then provided with electrodes to form a field effect transistor or a bipolar transistor. element.
JP2001318379A 2001-10-16 2001-10-16 Compound semiconductor epitaxial wafer Expired - Fee Related JP4150879B2 (en)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006303474A (en) * 2005-03-23 2006-11-02 Sony Corp Hetero junction bipolar transistor
US7575946B2 (en) 2004-03-19 2009-08-18 Sony Corporation Method for making compound semiconductor and method for making semiconductor device

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7575946B2 (en) 2004-03-19 2009-08-18 Sony Corporation Method for making compound semiconductor and method for making semiconductor device
KR101096331B1 (en) * 2004-03-19 2011-12-20 소니 주식회사 Method for making compound semiconductor and method for making semiconductor device
JP2006303474A (en) * 2005-03-23 2006-11-02 Sony Corp Hetero junction bipolar transistor

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