JP2003124359A - Method of manufacturing non-volatile semiconductor memory and cell structure of non-volatile semiconductor memory - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method of manufacturing a reliable non-volatile semiconductor memory which has a more pointed end part of a floating gate which is beneficial for electric charge emission in a split gate-type flash memory cell and enables to increase the number of rewriting. SOLUTION: As shown in the figure (a), a gate oxide film (tunnel oxide film) 11, a polysilicon layer 12, and a nitride film 13 are stacked in layers on a silicon substrate 10 which is well conditioned by implantation of impurity ions. Then, the nitride film 13 is patterned as a mask for forming a floating gate. Next, an exposed part of the polysilicon layer 12 is wet-oxidized at a high temperature higher than 850 deg.C but not exceeding 1,000 deg.C to form a selectively oxidized part 14. Then, as shown in the figure (b), the polysilicon layer 12 is etched with the selectively oxidized part 14 as a mask, to form a floating gate FG with a pointed end part 121.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a non-volatile semiconductor memory device and a non-volatile semiconductor memory, which is particularly focused on an improvement accompanied by an improvement in the rewritable count (endurance) of a split gate type flash memory (Flash EEPROM) cell. It relates to the cell structure of the device.

[0002]

2. Description of the Related Art Non-volatile semiconductor memory devices have been increasingly integrated and reduced in size, and low power supply voltage-boosted voltage operation has been generalized. In the split-gate type flash memory, charge injection / release operations are performed through different gate insulating films due to the structure of the cell.
This has the advantage that the quality of the oxide film involved in the charge injection / release operation is unlikely to deteriorate.

FIG. 7 is a sectional view showing an example of a cell structure in a general split gate type flash memory. The floating gate FG on the gate oxide film (tunnel oxide film) 71 is patterned by using the selective oxidation portion 74 obtained by selectively oxidizing the polysilicon layer 72 as a mask. This allows the floating gate end 72
1 has a pointed morphology.

The control gate CG is patterned through a part of the floating gate FG through the gate oxide film 75 to the vicinity of one side of the floating gate FG. Generally, the formation of the control gate CG and the formation of the gate electrode in another MOS transistor (not shown) are performed in the same step.

To write data to the memory cell having the above structure, a high voltage is applied to the control gate CG and the source S. As a result, thermoelectrons are injected into the floating gate FG via the gate oxide film 71 (data “0”).
Status). To erase data, the source S and the drain D are released and a high voltage is applied to the control gate CG. As a result, electrons are extracted from the floating gate end 721 to the control gate CG side by the tunnel effect (data “1” state).

A tunnel current at the time of erasing can be easily generated from the sharp floating gate end 721.
Therefore, the gate oxide film 75 is also thick (about 20 nm).
Can be set to. Further, the high voltage applied to the control gate CG can be set relatively low.

In this way, the charge injection / discharge operations are accomplished by different paths through the gate oxide film 71 / gate oxide film 75, respectively. Therefore, the lifetime of the oxide film (71, 75) related to the charge injection / release operation is extended, which contributes to the improvement of the number of data rewrites (endurance).

[0008]

A tunnel current at the time of erasing flows from the sharp floating gate end 721 to the control gate CG side. The structure in which the sharpness of the floating gate end portion 721 is excellent is more advantageous for the emission of electrons (extracting charges), and the erase characteristic is improved.

FIGS. 8 (a) and 8 (b) are respectively shown in FIG.
FIG. 6C is a cross-sectional view showing the method of manufacturing a part of the cell structure in, and showing the manufacturing process of floating gate FG. A polysilicon layer 72 is deposited on a gate oxide film (tunnel oxide film) 71 on a silicon substrate 70. Next, a nitride film 73 is deposited, and a mask of the nitride film 73 is formed on the polysilicon layer 72 by using the photolithography technique.

Thereafter, the polysilicon layer 72 not covered with the mask of the nitride film 73 is oxidized. The condition is 85
This is thermal oxidation for several tens of minutes in a steam atmosphere at 0 ° C. and about 95%, whereby the selective oxidation part 74 is formed (FIG. 8).
(A)).

Next, after removing the nitride film 73, the polysilicon layer 72 is etched using the selective oxidation portion 74 as a mask. As a result, the floating gate FG having a sharp end (721) is formed (FIG. 8B).

What should be noted here is the degree of sharpness of the floating gate end portion 721. The etching of the polysilicon layer 72 in FIG.
Is used as a mask to achieve anisotropic etching by, for example, RIE (Reactive Ion Etching) using a Cl-based etching gas. However, the etching selectivity of polysilicon with respect to the oxide film is moderate and cannot be said to be sufficiently large.

FIG. 9 is an enlarged sectional view of one of the gate end portions 721 of the floating gate FG as shown in FIG. 8B. When the etching of the polysilicon layer 72 using the selective oxidation portion 74 as a mask progresses, the thin portion of the end portion 741 of the selective oxidation portion is also etched to some extent. As a result, the top of the floating gate end 721 collapses and the sharpening is not sufficient. To that extent, the advantage of charge extraction is impaired, which hinders further improvement in erasing characteristics.

The present invention has been made in consideration of the above circumstances, and has a sharpened floating gate end portion which is advantageous for discharging charges in a split gate type flash memory cell, and has a higher rewritable number. An object of the present invention is to provide a method of manufacturing a non-volatile semiconductor memory device with improved high reliability and a cell structure of the non-volatile semiconductor memory device.

[0015]

A method of manufacturing a nonvolatile semiconductor memory device according to the present invention relates to a split gate type flash memory cell, and a polysilicon layer and a nitride film are formed on a first gate oxide film on a semiconductor substrate. And a step of selectively patterning the nitride film as a mask for forming a floating gate, and wet-oxidizing the exposed polysilicon layer at a temperature higher than 850 ° C. not exceeding 1000 ° C. A step of forming a selective oxidation portion that does not reach the bottom of the layer; a step of etching the polysilicon layer using the selective oxidation portion as a mask to form a floating gate with sharpened edges; and a step of sharpening the floating gate. Forming a control gate on at least one end portion via at least a second gate oxide film; Characterized in that Bei was.

According to the method for manufacturing a nonvolatile semiconductor memory device of the present invention, the polysilicon layer is selectively wet-oxidized at a temperature higher than 850 ° C., which does not exceed 1000 ° C.,
Longitudinal oxidization with a large oxidization rate and a dense selective oxidization part are revealed. Since the selective oxidation portion is dense, the etching selection ratio with respect to the polysilicon layer becomes large, and it becomes difficult to etch even a thin end portion. This allows
The top of the floating gate edge is hard to collapse, and the sharpened floating gate edge tends to remain.

A resist is used for patterning the nitride film, and the resist serves as an ion implantation mask for controlling the conductivity of the floating gate. As a result, the other circuit region not related to the memory cell is covered with the resist, and the ions can be implanted only in the floating gate portion to be ion-implanted.

When the polysilicon layer is etched using the selective oxidation portion as a mask, reactive ion etching using HBr as a main etching gas is used. Etching with excellent verticality is performed using relatively heavy atoms such as Br.

Further, the present invention relates to a cell structure of a split gate type non-volatile semiconductor memory device in which charge injection / release operations are carried out by paths through different gate insulating films, and a first structure formed on a semiconductor substrate. A gate insulating film and a floating gate on the gate insulating film, and a control gate formed on at least a second gate insulating film from a portion above the floating gate to a semiconductor substrate in the vicinity of a side portion thereof, The end of the floating gate is sharpened to improve the number of rewritable times associated with the charge discharging operation.

By improving sharpness at the end of the floating gate, the advantage of charge extraction becomes remarkable, and further improvement in erase characteristics can be expected as a cell structure. As a result, the number of rewritable times can be increased to 100,000 or more as a specification.

[0021]

1 (a) and 1 (b) are main parts of a method for manufacturing a nonvolatile semiconductor memory device according to a basic embodiment of the present invention, showing a split gate type flash memory. It is sectional drawing which shows the characteristic part of the formation method of the floating gate in a cell structure.

As shown in FIG. 1A, a gate oxide film (tunnel oxide film) 11 is formed on a silicon substrate 10 prepared by impurity ion implantation. A polysilicon layer 12 for the floating gate and a nitride film 13 for the mask are stacked on top of this. Then, the nitride film 13 is selectively patterned as a mask for forming a floating gate. Impurities have already been introduced into the polysilicon layer 12 using a resist (not shown) used when patterning the nitride film 13.

Next, the polysilicon layer 12 exposed from the pattern of the nitride film 13 does not exceed 850 ° C. 850.
Wet oxidation is performed at a temperature higher than 0 ° C., for example, 900 ° C., to form a selective oxidation portion 14 controlled so as not to reach the bottom of the polysilicon layer 12.

Next, as shown in FIG. 1B, the polysilicon layer 12 is etched using the selective oxidation portion 14 as a mask,
A floating gate FG having a sharpened end 121 is formed. Thereafter, although not shown here, a control gate (CG) is formed on at least one sharpened end 121 of the floating gate FG via at least a gate oxide film.

According to the method of the above embodiment, the polysilicon layer 12 is selectively wet-oxidized at a temperature higher than 850 ° C., which does not exceed 1000 ° C., so that the polysilicon layer 12 is oxidized vertically and becomes dense with a high oxidation rate. The selective oxidation part 14 is exposed. The selective oxidation portion 14 is a dense oxide film, and the etching selection ratio with respect to the polysilicon layer 12 becomes larger than that in the conventional case. Further, the end portion 141, which tends to be thin, is thicker than the conventional one.

As a result, when the polysilicon layer 12 is etched, the masking function of the selective oxidation portion 14 is superior to the conventional one, the top of the floating gate FG end 121 is less likely to collapse, and the sharpened end 121 remains. It's easy to do.

As described above, the sharpening of the end portion 121 of the floating gate FG is improved, so that the advantage of the charge extraction becomes remarkable, and further improvement of the erase characteristic can be expected. As a result, a highly reliable cell structure that further improves the number of rewritable times can be realized.

2 to 6 are main parts of a method of manufacturing a semiconductor memory device according to an embodiment of the present invention, and are cross-sectional views showing a method of manufacturing a split gate type flash memory cell in the order of steps. The same parts as those in FIG. 1 are designated by the same reference numerals for description.

As shown in FIG. 2, a gate oxide film (tunnel oxide film) 11, a polysilicon layer 12, and a nitride film 13 each having a thickness of 8 nm are formed on a silicon substrate 10 prepared by P-type impurity (for example, boron) ion implantation. About 120 nm and about 80 nm. After that, a resist PR is formed on the nitride film 13 and the pattern for forming the floating gate is removed.

The nitride film 13 is removed by reactive ion etching using CHF ₃ as a main etching gas according to the pattern of the resist PR. Further, using the pattern of the resist PR as a mask, ion implantation for controlling the conductivity of the floating gate is performed. This ion implantation uses, for example, P (phosphorus) with an acceleration voltage of 20 keV and a dose of 2 ×.
It is about 10 ¹⁴ cm ^-2 .

Next, as shown in FIG. 3, the resist PR is removed, and the polysilicon layer 12 exposed from the pattern of the nitride film 13 is exposed to a steam atmosphere of, for example, 900 ° C. and about 95% for several tens of minutes. Thermal oxidation is performed, maximum 140nm
The selective oxidation portion 14 having a film thickness of approximately the same is formed. This allows
A selective oxidation portion 14 having a strong tendency to oxidize in the vertical direction and not reaching the bottom of the polysilicon layer 12 is obtained.

Next, as shown in FIG. 4, after the nitride film 13 is removed by etching with hot phosphoric acid, the polysilicon layer 12 is etched using the selective oxidation portion 14 as a mask. This etching is, for example, reactive ion etching (anisotropic etching) using HBr as a main etching gas. Particularly, when relatively heavy atoms such as Br are used to accelerate the ions, the vertical etching property is excellent and selective etching removal can be achieved. Alternatively, a Cl-based etching gas may be used. As a result, the floating gate FG having the sharpened end 121 is formed (see FIG. 1).

Next, as shown in FIG. 5, a gate oxide film 15 is formed so as to have a predetermined thickness (about 20 nm) at least on the sharpened one end 121 of the floating gate FG. Next, the floating gate FG including the deposition of the polysilicon layer and the refractory metal (such as W) is included.
A control gate CG forming a silicide layer is formed by patterning on the sharpened one end portion 121 to the substrate.

Next, as shown in FIG. 6, a protective film (oxide film or the like; sometimes including a nitride film) 16 is formed on the entire cell structure, and ion implantation of source lines and ions of drain regions are performed. The injection is done. As a result, the structure of the split gate type flash memory cell can be realized.

To write data to the memory cell having the structure shown in FIG. 6, a high voltage is applied to the control gate CG and the source S. As a result, hot electrons are injected into the floating gate FG via the gate oxide film 11 (data “0” state). Data is erased by source S and drain D
Is released and a high voltage is applied to the control gate CG.
As a result, electrons are extracted from the floating gate end 121 to the control gate CG side by the tunnel effect (data “1” state).

According to the method of the above-described embodiment, the polysilicon layer 12 obtains a high oxidation rate (oxidation tendency in the vertical direction) at a high temperature of about 900 ° C. to expose the dense selective oxidation portion 14. As a result, when the polysilicon layer 12 is etched, the masking function of the selective oxidation portion 14 is improved, the top of the floating gate FG end 121 is less likely to collapse, and a sharpened end 121 can be obtained.

By improving sharpening of the end portion 121 of the floating gate FG, the advantage of charge extraction becomes remarkable, and further improvement of erasing characteristics can be expected.
As a result, a highly reliable cell structure capable of improving the number of rewritable times to 100,000 or more as a specification is realized.

[0038]

As described above, according to the method of the present invention, the polysilicon layer does not exceed 1000 ° C. and 850 ° C.
It is selectively wet-oxidized at a higher temperature to expose vertical oxidation and a dense selective oxidation portion with a high oxidation rate. As a result, the etching selectivity with respect to the polysilicon layer is increased, and the sharpened floating gate end portion is likely to remain. As a result, a method for manufacturing a nonvolatile semiconductor memory device having a sharpened floating gate end portion that is advantageous for discharging charges in a split gate type flash memory cell and having high reliability that further improves the number of rewritable times Also, a cell structure of a nonvolatile semiconductor memory device can be provided.

[Brief description of drawings]

1A and 1B are each a main part of a method for manufacturing a nonvolatile semiconductor memory device according to a basic embodiment of the present invention, in which a floating gate in a cell structure of a split gate type flash memory is used. FIG. 6 is a cross-sectional view showing a characteristic part of the forming method of FIG.

FIG. 2 is a first cross-sectional view showing an essential part of the method for manufacturing the semiconductor memory device according to the embodiment of the present invention, and showing the method for manufacturing the split gate type flash memory cell in the order of steps.

FIG. 3 is a second cross-sectional view subsequent to FIG.

FIG. 4 is a third cross-sectional view subsequent to FIG.

FIG. 5 is a fourth cross-sectional view following FIG.

FIG. 6 is a fifth cross-sectional view following FIG.

FIG. 7 is a cross-sectional view showing an example of a cell structure in a general split gate type flash memory.

8A and 8B are cross-sectional views showing a method of manufacturing a part of the cell structure in FIG. 7, showing a manufacturing process of the floating gate FG.

FIG. 9 is a floating gate F in FIG.
It is sectional drawing which expanded the gate edge part 13 of G.

[Explanation of symbols]

10, 70 ... Silicon substrate 11, 15, 71, 75 ... Gate oxide film, 12, 72 ... Polysilicon layer 121 ... Edge (Sharpened edge of polysilicon) 13, 73 ... Nitride film 14,74 ... Selective oxidation part 141, 741 ... End of selective oxidation part 16 ... Protective film 721 ... End of floating gate FG ... floating gate CG ... control gate PR ... resist

Continued front page    F term (reference) 5F083 EP03 EP13 EP25 EP52 EP57                       ER02 ER17 ER22 GA21 JA39                       JA56 PR03 PR05 PR07 PR33                       PR36                 5F101 BA07 BA15 BA24 BA36 BB04                       BC01 BC11 BD02 BD22 BE05                       BE07 BF03 BH03 BH09 BH14                       BH19

Claims (4)

[Claims] 1. A split gate type flash memory cell, comprising: stacking a polysilicon layer and a nitride film on a first gate oxide film on a semiconductor substrate; and selecting the nitride film as a mask for forming a floating gate. Patterning, the exposed polysilicon layer is wet-oxidized at a temperature higher than 850 ° C., which does not exceed 1000 ° C., to form a selective oxidation portion that does not reach the bottom of the polysilicon layer, and the selective oxidation portion. Etching the polysilicon layer with the mask as a mask to form a floating gate having sharpened ends, and forming a control gate on at least one sharpened end of the floating gate through at least a second gate oxide film. A method of manufacturing a non-volatile semiconductor memory device, comprising: a forming step. 2. The non-volatile according to claim 1, wherein a resist is used for patterning the nitride film, and the resist serves as an ion implantation mask for controlling conductivity of the floating gate. Manufacturing method of semiconductor memory device. 3. The non-volatile according to claim 1, wherein when the polysilicon layer is etched by using the selective oxidation portion as a mask, reactive ion etching using HBr as a main etching gas is used. Manufacturing method of semiconductor memory device. 4. A cell structure of a split gate type non-volatile semiconductor memory device in which charge injection / release operations are performed through different gate insulating film paths, and a first gate insulating film formed on a semiconductor substrate. And a floating gate on the floating gate, and a control gate formed on at least a second gate insulating film from a portion above the floating gate to a semiconductor substrate in the vicinity of a side portion adjacent to the floating gate, and an end of the floating gate. The cell structure of the nonvolatile semiconductor memory device is characterized in that the portion is sharpened to improve the number of rewritable times associated with the charge discharging operation.