JP2003116071A - Digital tv receiving set - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce processing load on a CPU at image data transfer in data broadcast by a DMA controller. SOLUTION: CS broadcast wave received with an antenna 1 is sent through a tuner 2 to a decoder 3. The CS broadcast wave is separated to the data of television broadcast and the data of data broadcast with the decoder 3. The data of the data broadcast is processed to image data by a CPU 4 and stored in a DRAM 7a. The image data stored in the DRAM 7a is transferred to a DRAM 7b by a DMA controller 5. A graphic device 6 composites the image data stored in the DRAM 7b and the data of the television broadcast sent from the decoder 3, and outputs to an image output circuit 8 and a CRT 10.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital television receiver having an expansion bus, and more particularly to a digital television receiver for transferring image data via the expansion bus.

[0002]

2. Description of the Related Art A digital television receiver receives and displays not only television broadcasts such as dramas and movies but also data broadcasts providing information such as electronic program guides and weather forecasts. The images of the television broadcast and the data broadcast are simultaneously displayed on the display screen of the digital television receiver. Users can get information on programs and weather forecasts while watching TV.

A microcomputer is mounted on the digital television receiver. The CS broadcast wave using the communication satellite is separated into television broadcast data and data broadcast data by the decoder of the digital television receiver,
The data of the data broadcast is processed and displayed by the microcomputer. FIG. 4 is a block diagram showing a hardware configuration of a conventional digital television receiver. As shown in the figure, the conventional digital television receiver has a decoder 21
, CPU 22, graphic device 23, DR
AM 24a, 24b, video output circuit 25, PCI
(Peripheral Component Interconnect) bus 26.

The decoder 21 separates the CS broadcast waves sent from the communication satellites into television broadcast data such as dramas and movies, and data broadcast data such as electronic program guides and weather forecasts. The data of the data broadcast is sent to the CPU 22 via the PCI bus 26. The television broadcast data is sent to the graphic device 23.

The CPU 22 processes the data of the data broadcast transmitted via the PCI bus 26 into image data displayed on the display screen according to a program stored in a ROM (not shown) or the like, and via the PCI bus 26. And sends it to the graphic device 23.

The graphic device 23 is a CPU 22.
The image data of the data broadcast transmitted from the device via the PCI bus 26 is stored in the plane of the DRAM 24b (plane: area corresponding to the display screen). Further, the graphic device 23 synthesizes the television broadcast data sent from the decoder 21 and the image data of the data broadcast stored in the plane of the DRAM 24b, and sends it to the video output circuit 25.

The DRAM 24a is a work area used when the CPU 22 processes data of data broadcasting into image data according to a program. DRAM2
4b stores the image data of the data broadcast processed by the CPU 22 in the plane.

The video output circuit 25 converts the data of the television broadcast and the image data of the data broadcast synthesized by the graphic device 23 into a signal which can be displayed on a display device such as a CRT.

The PCI bus 26 is an expansion bus used when the CPU 22 and the graphic device 23 exchange data. The operation of the digital television receiver shown in FIG. 4 will be described below.

The CS broadcast wave sent from the communication satellite is
The decoder 21 separates the data for television broadcasting from the data for data broadcasting such as an electronic program guide. The data of the data broadcast is sent to the CPU 22 via the PCI bus 26. The CPU 22 processes the data of the data broadcast into image data using a graphic library or the like. C
The PU 22 sends the processed image data to the graphic device 23 via the PCI bus 26. The graphic device 23 stores the sent image data in the DRAM 24b.
Stored in the plane.

The graphic device 23 is the DRAM 2
The image data of the data broadcast stored in the plane of 4b and the data of the television broadcast sent from the decoder 21 are combined and sent to the video output circuit 25. Video output circuit 2
5 converts the combined data into data that can be displayed by a display device such as a CRT and sends the data to the display device.

[0012]

As described above, in the conventional digital television receiver, the CPU sends the image data of the data broadcast to the D of the graphic device via the PCI bus.
Write to the RAM plane. Generally, the data transfer speed in an expansion bus such as a PCI bus is lower than the execution speed of a CPU. For this reason, there is a problem in that the CPU occupies the processing for the data transfer and the processing capability is lowered.

The present invention has been made in view of the above points, and an object of the present invention is to provide a digital television receiver which reduces the processing load of the CPU for transferring image data.

[0014]

According to the present invention, in a digital television receiver having an expansion bus, a central processing unit for processing data of data broadcasting into image data,
A main memory connected to the expansion bus for storing the image data, a display image memory connected to the expansion bus, and the image data stored in the main memory are transferred to the display image memory. A direct memory access controller is provided, and a digital television receiver is provided.

According to the above configuration, the central processing unit is
The processed image data is stored in the main memory, and the image data stored in the main memory is transferred to the display image memory by the direct memory access controller. This reduces the processing load on the central processing unit in the transfer of image data.

[0016]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing a hardware configuration of a digital television receiver of the present invention.

As shown in FIG. 1, the digital television receiver includes an antenna 1, a tuner 2, a decoder 3 and a CP.
U4, DMA controller 5, graphic device 6, DRAMs 7a and 7b, video output circuit 8, and P
It is composed of a CI bus 9 and a CRT 10.

The antenna 1 receives CS broadcast waves sent from communication satellites. The antenna 1 sends the received CS broadcast wave to the tuner 2. The tuner 2 high-frequency processes and demodulates the CS broadcast wave sent from the antenna 1. The tuner 2 sends the CS broadcast wave that has undergone high frequency processing and demodulation to the decoder 3.

The decoder 3 separates the CS broadcast wave sent from the tuner 2 into television broadcast data such as dramas and movies and data broadcast data such as electronic program guides and weather forecasts. The data of the data broadcast is sent to the CPU 4 via the PCI bus 9. The data of the television broadcast is sent to the graphic device 6.

The CPU 4 operates according to a program,
The data of the data broadcast received from the decoder 3 is processed into image data using a graphic library for drawing figures such as characters, lines and curves, and stored in the plane of the DRAM 7a. The above-mentioned program and graphic library are stored in a hard disk or a ROM (not shown).

The DMA controller 5 transfers the image data of the data broadcast stored in the plane of the DRAM 7a to the PC.
Transfer to the plane of the DRAM 7b via the I bus 9.
The start of transfer and the amount of image data to be transferred depend on the CPU
4 to execute.

The graphic device 6 is a DRAM 7b.
The image data of the data broadcast stored in the plane and the data of the television broadcast sent from the decoder 3 are combined and sent to the video output circuit 8.

The DRAM 7a has a plane which is an area corresponding to the display screen of the CRT 10. The image data of the broadcast data processed by the CPU 4 is the DRAM 7a.
Stored in the plane. In addition, the DRAM 7a is a CP
The programs executed by U4 are expanded, and the CP
It has a work area when the U4 program is executed.

The DRAM 7b has a plane which is an area corresponding to the display screen of the CRT 10. The image data transferred from the DRAM 7a by the DMA controller 5 is stored in the plane of the DRAM 7b.

The video output circuit 8 converts the data sent from the graphic device 6 into a signal which can be displayed by the CRT 10. The PCI bus 9 includes a decoder 3 and a CPU
4, DMA controller 5, graphic device 6,
It is an expansion bus that connects the DRAMs 7a and 7b to each other and exchanges data.

Next, the operation of the above digital television receiver will be described with reference to the flow chart showing the flow of the CS broadcast wave in FIG. The CS broadcast waves transmitted from the communication satellites include television broadcasts such as dramas and movies, and data broadcasts such as electronic program guides and weather forecasts. This CS broadcast wave is transmitted to the antenna 1
(S1).

The antenna 1 sends the received CS broadcast wave to the tuner 2. The tuner 2 high-frequency processes and demodulates the sent CS broadcast wave (S2), and sends it to the decoder 3. The decoder 3 separates the CS broadcast wave sent from the tuner 2 into television broadcast data and data broadcast data (S3).

The television broadcast data is sent to the graphic device 6 (S4). Data for data broadcasting is P
It is sent to the CPU 4 via the CI bus 9. CPU4
According to the data of the data broadcast, the patterns such as menu screens and buttons to be displayed are processed into image data by the graphic library (S5) and stored in the plane of the DRAM 7a (S6). After storing the image data, the CPU 4 instructs the DMA controller 5 to start transferring the plane data. The DMA controller 5 is a DRAM 7a
Plane data to DRAM via PCI bus 9
Transfer to the 4b plane (S7). The CPU 4 can perform other processing during the transfer of the plane data.

By the way, the transfer is performed for each image portion of the data broadcast displayed on the display screen of the CRT 10. For example, when displaying a plurality of buttons on the display screen of the CRT 10, the CPU 4 sends a transfer start instruction to the DMA controller 5 when the image data processing for one button is completed.

The CPU 4 also includes a DMA controller 5
And the amount of plane data to be transferred. The DMA controller 5 is the CPU 4
The transfer is started by and the data is transferred by the instructed transfer amount.

The graphic device 6 is a DRAM 7b.
The image data of the data broadcast stored in the plane and the data of the television broadcast sent from the decoder 3 are combined (S8) and sent to the video output circuit 8, and the video output circuit 8 is combined with the CRT 10. The data is converted into a displayable signal (S9) and sent to the CRT 10 (S10).

That is, the CPU 4 does not directly store the image data of the data broadcast in the plane of the DRAM 7b via the PCI bus 9 but in the plane provided in the DRAM 7a. Then, the DMA controller 5 causes the DRA
The plane data of M7a is transferred to the plane of DRAM 7b. As a result, the CPU 4 causes the DMA controller 5 to transfer the planes while the planes are being transferred.
Other processing can be executed, and the execution capability of the CPU 4 does not decrease.

In some cases, a plurality of planes are required. For example, it is a case where a plurality of data broadcasts are displayed at the same time. In this case, since data transfer is performed for each image part, only one plane needs to be prepared in the DRAM 7a. That is, it is not necessary to increase the storage capacity of the DRAM 7a. In particular, HD (High Defin
It is useful when dealing with resolution.

By the way, the CPU 4 described in FIG.
A CPU having the function of the MA controller 5 may be used. In the above description, the case where the CS broadcast wave is received has been described as an example, but of course, it can be applied to the case where another digital broadcast wave is received.

Next, the hierarchical structure of software used in the digital television receiver will be described. FIG. 3 is a diagram showing a hierarchical structure of software used in the digital television receiver.

As shown in FIG. 3, the software used in the digital television receiver has a graphic library in the lowermost layer and a GUI (Graphical User I) in the upper layer.
terface) toolkits A1 to A3, and applications B1 to B4 above them.

The graphic library is a componentized program for displaying lines, curves or colors on the display screen of a digital television. In addition, the DMA controller 5
Describes a program for instructing the start of plane data transfer and the transfer amount.

The GUI tool kits A1 to A3 are software for displaying buttons and icons displayed on the display screen of the digital television. For example, it is displayed by using a graphic library such as a frame composing buttons and colors.

The applications B1 to B4 are software for displaying electronic program guides, weather forecast information, etc. on the display screen of the digital television. For example, the application B1 may specify the buttons and icons that make up the electronic program guide by
It is displayed using the GUI tool kit A1. In application B2, GUI toolkit A2, and
Display by directly using the graphic library. For application B3, GUI toolkits A2 and A3
Use to display. In application B4, GU
It is displayed using the I tool kit A3.

The hierarchical structure of the software of FIG. 3 will be described below with reference to the block diagram of FIG. The antenna 1 receives the CS broadcast wave from the communication satellite. C received
The S broadcast wave is sent to the tuner 2, the CS broadcast wave is subjected to high frequency processing and demodulation, and then sent to the decoder 3. The decoder 3
Separated into data of TV broadcasting and data of data broadcasting,
The data of the data broadcast is sent to the CPU 4 via the PCI bus 9.
Send to.

The data broadcast of the received CS broadcast wave is an electronic program guide. The application B1 shown in FIG. 3 is an application for displaying an electronic program guide.

The CPU 4 selects and executes the application B1 from the data of the electronic program guide sent from the decoder 3. It is assumed that the application B1 contains, for example, a program for instructing to display a button for selecting a program to watch. Application B1
GUI Tool Kit A to display this button
Call 1.

The GUI tool kit A1 describes a program for displaying the frame and color of buttons. G
The UI tool kit A1 calls a graphic library to display the frame and the color of the button. The graphic library describes a program for displaying the lines and colors of the frame of the button.

As described above, the CPU 4 executes the application B1, the GUI tool kit A1, and the graphic library to generate image data for displaying the button, and stores the image data in the plane of the DRAM 7a.

Upon completion of storing the button image data in the plane, the CPU 4 further executes the graphic library to calculate the transfer amount of the button image data,
Start of plane data transfer to the DMA controller 5,
Also, the transfer amount is instructed. The DMA controller 5
The data of the plane of the DRAM 7a is transferred to the plane of the DRAM 7b by the transfer amount instructed by the CPU 4, and the transfer is completed.

The graphic device 6 is a DRAM 7b.
The image data of the button stored in the plane and the data of the television broadcast sent from the decoder 3 are combined and sent to the video output circuit 8, and the video output circuit 8 sends the sent composite data to It is converted into a signal that can be displayed on the display screen of the CRT 10 and sent to the CRT 10.

As described above, when the processing procedure for transferring the plane to the DMA controller 5 is stored in the graphic library, the upper application and the GUI tool kit can be used without modification. That is, the conventional application and the GUI tool kit can be used as they are.

In the above description, the case where the CS broadcast wave is received has been described as an example, but of course, it can be applied to the case where another digital broadcast wave is received.

[0049]

As described above, in the present invention, the central processing unit stores the processed image data in the main memory, and the image data stored in the main memory is stored in the display image memory by the direct memory access controller. Since the image data is transferred, the processing load on the central processing unit in transferring the image data can be reduced.

[Brief description of drawings]

FIG. 1 is a block diagram showing a hardware configuration of a digital television receiver of the present invention.

FIG. 2 is a flowchart showing the flow of CS broadcast waves.

FIG. 3 is a diagram showing a hierarchical structure of software used in a digital television receiver.

FIG. 4 is a block diagram showing a hardware configuration of a conventional digital television receiver.

[Explanation of symbols]

1 ... Antenna, 2 ... Tuner, 3 ... Decoder, 4
... CPU, 5 ... DMA controller, 6 ... graphic device, 7a, 7b ... DRAM, 8 ... video output circuit, 9 ... PCI bus, 10 ... CRT.

Claims (2)

[Claims] 1. A digital television receiver having an expansion bus, a central processing unit for processing data of data broadcasting into image data, a main memory connected to the expansion bus for storing the image data, and the expansion. A digital television receiver comprising: a display image memory connected to a bus; and a direct memory access controller that transfers the image data stored in the main memory to the display image memory. 2. The digital television receiver according to claim 1, wherein the graphic library has a procedure for instructing the transfer to the direct memory access controller executed by the central processing unit.