JP2003115819A - Filtering device, spread modulation device, filtering method, spread modulation method, program and information recording medium - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a filtering device or the like suitable for executing spread modulation by using the spreading code of high separation performance in radio communication technology. SOLUTION: An input receiving part 102 of a filtering device 101 receives the input of streams of complex numbers, a real processing part 103 receives the stream of a real number part as input in the relevant streams of complex numbers and outputting a filtered stream, an imaginary processing part 104 receives a stream of imaginary numbers as input in the relevant streams of the complex numbers and outputs a filtered stream, and an output part 105 outputs the stream of complex numbers with the stream outputted by the real processing part 103 as a real number part and with the stream outputted by the imaginary processing part 104 as an imaginary number part. Each of real processing part 103 and imaginary processing part 104 outputs a plurality of streams delaying the inputted streams, amplifies a plurality of relevant streams and outputs the total sum of the relevant amplified streams, the delay time of a plurality of relevant streams forms an arithmetical progression and an amplification factor to these respective streams forms a geometrical progression.

Description

Detailed Description of the Invention

[0001]

TECHNICAL FIELD The present invention relates to a filter device, a spread modulator, a filter method, a spread modulation method, a program, and an information recording medium.

[0002]

2. Description of the Related Art Conventionally, IMT 2000 W-CD
MA system, lCDMA2000 system, wireless LA
Wireless communication technology based on systems such as IEEE 802.11b has been proposed. In such wireless communication, in order to use the same frequency band for multiple communication connections,
CDMA (Code Division Multiple Access) is used.

In CDMA, a plurality of communication connections can be put in the same frequency band and desired communication connections can be separated from the same frequency band by spreading-modulating communication information by using different spreading codes.

On the other hand, in these wireless communications, it is common to convert the information to be transmitted into a complex number sequence for processing.

[0005]

Therefore, in such a radio communication technique, there is a demand for a simple technique for performing spread modulation using a spread code having good separation performance.

It is an object of the present invention to provide a filter device, a spread modulator, a filter method, a spread modulation method, a program, and an information recording medium suitable for performing such spread modulation.

[0007]

In order to achieve the above object, the following invention is disclosed according to the principle of the present invention.

A filter device according to a first aspect of the present invention provides a predetermined real impulse constant r (-1≤r≤1), a predetermined real number constant x (x ≠ 0), and a predetermined delay time constant D. Using a sequence of complex numbers, using an input reception unit, a real delay unit, a real amplification unit, a real addition unit, an imaginary delay unit, an imaginary amplification unit, an imaginary addition unit, an output unit, And is configured as follows.

Here, the input receiving unit receives an input of a complex number series.

On the other hand, the real delay unit converts the real part sequence of the complex number sequence received by the input reception unit into 0, D, 2D, 3D, ..., (N-1) D (N Is a predetermined positive integer) and outputs a plurality of sequences delayed.

Further, the real amplifier unit multiplies each of the plurality of sequences delayed by the real delay unit and output, when the delay time is T, by multiplying by x (-r) ^{NT / D} and amplifying. Output a series of.

Then, the real adder outputs the total sum of the plurality of sequences amplified and output by the real amplifier.

On the other hand, the imaginary delay unit delays the sequence of the imaginary part of the complex number sequence received by the input reception unit by 0, D, 2D, 3D, ..., (N-1) D, respectively. Output the selected series.

Further, the imaginary amplification unit amplifies each of the plurality of real number sequences delayed and output by the imaginary delay unit by multiplying x (-r) ^{NT / D} when the delay time is T. Output multiple streams.

The imaginary addition unit outputs the total sum of the plurality of sequences amplified and output by the imaginary amplification unit.

On the other hand, the output unit outputs a complex number sequence in which the sequence output by the real addition unit is the real number part and the sequence output by the imaginary addition unit is the imaginary number part.

Further, in the filter device of the present invention, the real delay part and the imaginary delay part are "0, D, 2D, 3D, respectively.
..., (N-1) D delay "instead of D, 2 respectively
D, 3D, ..., (N-1) D, ND are delayed, and the real and imaginary amplifying units display “x (-r) when the delay time is T”.
If the delay time is T instead of “ ^{NT / D} times amplification”, it can be configured to multiply by x (−r) ^{N− (T−1) / D.}

In addition, in the filter device of the present invention, the real amplifying section and the imaginary amplifying section are replaced by "when the delay time is T, amplifying by multiplying x (-r) ^{NT / D} ". When the delay time is T, it can be configured to multiply by x (−r) ^{1 + T / D} and amplify.

Further, in the filter device of the present invention, the real delay part and the imaginary delay part are "0, D, 2D, 3D, respectively.
..., (N-1) D delay "instead of D, 2 respectively
D, 3D, ..., (N-1) D, ND are delayed, and the real and imaginary amplifying units display “x (-r) when the delay time is T”.
If the delay time is T instead of “ ^{NT / D} multiplication and amplification”, x (−r) ^{T / D} multiplication can be performed.

A filter device according to another aspect of the present invention is
A predetermined impulse constant r (-1 ≤ r ≤ 1) and a predetermined delay time constant D are used to filter a sequence of complex numbers, and an input reception unit, an actual processing unit, an imaginary processing unit, and an output unit And, and is configured as follows.

Here, the input receiving unit receives an input of a complex number series.

On the other hand, the real processing section receives the sequence of the real number part as an input among the complex number series of which the input is received by the input receiving section, and outputs the filtered series.

Further, the imaginary processing unit receives a sequence of the imaginary number part as an input among the complex number sequences of which the input is received by the input reception unit, and outputs the filtered sequence.

The output unit outputs a complex number sequence in which the sequence output by the real processing unit is the real number part and the sequence output by the imaginary processing unit is the imaginary number part.

On the other hand, the real processing part and the imaginary processing part are
Outputs a plurality of sequences that are delayed from the input sequence, amplifies each of the plurality of sequences, outputs the sum of the amplified sequences, and the delay time of the plurality of sequences is an arithmetic sequence of the tolerance D. The amplification factor for each of these is
-r or common ratio -1 / r forms a geometric progression.

The predetermined real impulse constant r can be configured to be equal to 2-3 ^1/2 in fixed-point number representation with a predetermined precision.

In the filter device of the present invention, the real delay section, the real amplification section, the real addition section, the imaginary delay section, the imaginary amplification section, and the imaginary addition section are ASIC (Application Specific I
integrated circuit), DSP (Digital Signal Proces)
sor) or FPGA (Field Programmable Gate)
Array).

A spread modulator according to another aspect of the present invention is
The above filter device is used, and a scrambler and a modulator are provided, and the configuration is as follows.

Here, the scramble part calculates the real part and the imaginary part of the input digital complex number by the chip rate 1 /
A complex number scrambled by a predetermined spreading code of D is output.

On the other hand, the modulator applies the complex number output by the scrambler as an input to the filter device to perform spread modulation.

In the spread modulator of the present invention, scrambling by the scrambling unit is performed by the IMT 200
0 W-CDMA system standard, CDMA2000 system standard, or wireless LAN IEEE802.1
It can be configured to comply with the 1b standard.

Further, in the spreading modulator of the present invention, the scrambling unit may be configured to scramble any one of a Gold code, a Baker sequence or a Walsh-Hadamard code as a spreading code.

Further, in the spread modulator of the present invention, the spread code of the scramble section can be configured to be given at each point of the trajectory of the mapping dynamical system having the ergodic property.

Further, in the spread modulator of the present invention, the mapping dynamical system having the ergodic property of the scramble section can be configured to be a mapping dynamical system having Chebyshev polynomials of second or higher degree as the mapping.

A filter method according to another aspect of the present invention is
Using a predetermined impulse constant r (-1 ≤ r ≤ 1) and a predetermined delay time constant D, a complex number sequence is filtered, and an input receiving step, an actual processing step, an imaginary processing step, and an output step. And, and is configured as follows.

Here, in the input receiving step, the input of the complex number series is received.

On the other hand, in the actual processing step, the series of the real part is received as an input among the series of complex numbers received in the input receiving step, and the filtered series is output.

Further, in the imaginary processing step, the series of the imaginary number part is received as an input among the series of complex numbers received in the input receiving step, and the filtered series is output.

Then, in the output step, a series of complex numbers in which the series output in the actual processing step is the real number part and the series output in the imaginary processing step is the imaginary part is output.

On the other hand, in the actual processing step and the imaginary processing step, a plurality of series obtained by delaying the input series is output, each of the plurality of series is amplified, and the sum of the amplified series is output. However, the delay times of the plurality of sequences form a geometric progression of the common tolerance D, and the amplification factor for each of these forms a common progression of the common ratio -r or the common ratio -1 / r.

Further, in the filter method of the present invention, the predetermined actual impulse constant r can be configured to be equal to 2-3 ^1/2 in the fixed-point number representation with the predetermined accuracy.

In the filter method of the present invention, the real delay step, the real amplification step, the real addition step, the imaginary delay step, the imaginary amplification step, and the imaginary addition step are executed in ASIC, DSP, or FPGA. Can be configured as.

A spread modulation method according to another aspect of the present invention is
Using the above-mentioned filter method, the scrambling step and the modulation step are provided and configured as follows.

Here, in the scrambling step, the real number and the imaginary number of the input digital complex number are scrambled by a predetermined spreading code with a chip rate of 1 / D, and a complex number is output.

On the other hand, in the modulation step, the complex number output in the scramble step is given as an input to the filter method to perform spread modulation.

Further, in the spreading modulation method of the present invention, scrambling in the scrambling step is performed by IMT 2
000 W-CDMA system standard, CDMA2000
System standard or wireless LAN IEEE80
It can be configured to comply with the 2.1 1b standard.

Further, in the spreading modulation method of the present invention, in the scrambling step, any one of Gold code, Baker sequence, or Walsh = Hadamard code can be scrambled as a spreading code.

Further, in the spreading modulation method of the present invention, the spreading code in the scrambling step can be configured to be given at each point of the trajectory of the mapping dynamical system having the ergodic property.

Further, in the spread modulation method of the present invention, the mapping dynamical system having the ergodic property in the scrambling step can be configured to be a mapping dynamical system having Chebyshev polynomials of second or higher degree as the mapping.

A program according to another aspect of the present invention is a computer (including ASIC, DSP, FPGA).
To function as the above filter device or spread spectrum modulation device, or to cause a computer to execute the above filter method or spread spectrum modulation method.

Further, the program of the present invention is a computer-readable information recording medium (compact disc, flexible disc, hard disc, magneto-optical disc,
It includes a digital video disk, magnetic tape, or semiconductor memory. ) Can be recorded in.

The program of the present invention is stored in a general-purpose computer including a storage device, a computing device, an output device, a communication device, a mobile phone, and a PHS (Personal Handyphone Syste).
m) A device, a mobile terminal such as a game device, an information processing device such as a parallel computer, an ASIC, a DSP, an FPGA, and the like to realize the above filter device, spread modulator, filter method, and spread modulation method. can do.

Independently of these devices, the information recording medium of the present invention can be distributed and sold in stores or the program itself of the present invention can be distributed and sold via a computer communication network. it can.

[0054]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below. It should be noted that the embodiments described below are for the purpose of explanation, and do not limit the scope of the present invention. Therefore, a person skilled in the art can adopt an embodiment in which each of these elements or all the elements are replaced by equivalents thereof, but these embodiments are also included in the scope of the present invention. .

(First Embodiment) FIG. 1 is a schematic diagram showing a schematic configuration of a filter device according to a first embodiment of the present invention.

The filter device 101 according to this embodiment has a predetermined impulse constant r (-1≤r≤1) and a predetermined delay time constant D.
Is used to filter a complex number sequence, and an input reception unit 102, an actual processing unit 103, an imaginary processing unit 104, and an output unit 105 are provided.

First, the input receiving unit 102 receives an input of a complex number series.

Next, the actual processing section 103 has the input receiving section 10
Among the complex number sequences of which the input is accepted by 2, the sequence of the real part is accepted as an input and the filtered sequence is output.

On the other hand, the imaginary processing unit 104 includes the input receiving unit 10
Among the complex number series of which the input is accepted by 2, the series of the imaginary part is accepted as an input and the filtered series is output.

The processing performed by the real processing section 103 and the imaginary processing section 104 can be executed in parallel.

The output unit 105 is the actual processing unit 103.
The complex number sequence having the sequence output as the real number part and the sequence output by the imaginary processing part 104 as the imaginary number part is output.

Here, the real processing section 103 and the imaginary processing section 104 output a plurality of sequences obtained by delaying the input sequence, amplify each of the plurality of sequences, and output the amplified sequences. The total sum is output, and the delay times of the plurality of sequences form an arithmetic progression of the tolerance D, and the amplification factor for each of them is the geometric progression of the common ratio r or the common ratio -1 / r.

FIG. 2 shows an FIR (Finite Impulse Responsions) constituting the real processing section 103 and the imaginary processing section 104.
e) It is a schematic diagram which shows the schematic structure of a filter. Hereinafter, description will be given with reference to this figure.

The FIR filter 201 includes a plurality of delay units 2
02, a plurality of amplification units 203, and an addition unit 204.

The input sequence is composed of a plurality of delay units 202.
In each case, the input sequence is delayed by a predetermined delay time D and then output. Therefore, in this embodiment, 0, D, 2D, and
A sequence delayed by 3D, ..., (N-1) D is input. Here, N is the number of delay sequences.

Further, another delay device may be arranged before the plurality of delay units 202. In this case, the delay time of the delayed sequence given to the plurality of amplification units 203 is
The respective delay times of different delay devices are added. In particular, when the delay time of this other delay device is also D, the sequence delayed by D, 2D, 3D, 4D, ..., (N-1) D is input to each of the plurality of amplification units.

On the other hand, the amplification factors of the plurality of amplifying sections 203 are x, x (-r), x (-r) ² , x (-r) ³ , ..., x (-r) ^N , respectively. There is. Where x (x ≠ 0) is a predetermined real constant, -r (-1 ≤ r
≦ 1) is a predetermined impulse constant, and it is desirable that r = 2−3 ^1/2 .

The adder 204 adds the outputs of the plurality of amplifiers 203.

Therefore, the inputted sequences are sequentially ...
When s _-2 , s _-1 , s ₀ , s ₁ , s ₂ , ..., the output of the FIR filter 201 is as follows (for easy understanding, the delay time of the output with respect to the input is Ignore it and assume there is an infinite length of input).

..., x (s _-N-1 (-r) ^N-1 + ... + s _-4 (-r) ² + s _-3 (-r) ¹ + s _-2 ), x (s _-N (-r) ^N-1 +… + s _-3 (-r) ² + s _-2 (-r) ¹ + s _-1 ), x (s _{-N + 1} (-r) ^N-1 +… + s _-2 (-r) ² + s _-1 (-r) ¹ + s ₀ ), x (s _{-N + 2} (-r) ^N-1 +… + s _-1 (-r) ² + s ₀ (-r) ¹ + s ₁ ), x (s _{-N + 3} (-r) ^N-1 +… + s ₀ (-r) ² + s ₁ (-r) ¹ + s ₂ ),…

The amplification factors of the plurality of amplifying units 203 are x (-r) ^N-1 , x (-r) ^N-2 , ..., x (-r) ² , x (-r) ¹ ，
…, X may be used.

With this configuration, the delay times of the plurality of delay sequences output from the plurality of delay units 202 form an arithmetic progression of the tolerance D, and the amplification factor for each of them is the common ratio (- r) or the geometric ratio sequence of the common ratio (-1 / r).

The inventors have disclosed the theoretical background of the FIR filter 201 in Japanese Patent Application No. 2001-8740. For example, it has been found that the use of the FIR filter 201 in a CDMA communication system can increase the number of users by 15% as compared with the conventional case.

In this embodiment, this FIR filter 201 is used.
The two parts are used to filter the real part and the imaginary part of the complex number sequence, respectively.

The delay section 202 and the amplification section 20 are provided.
3 and the addition unit 204 can be configured by simple arithmetic circuits. Therefore, a computer may be used to perform the operation based on software, and
The dedicated hardware may be configured using C, DSP, FPGA, etc. to perform the calculation.

(Second Embodiment) In the second embodiment of the present invention, the filter device 101 is applied to a W-CDMA standard mobile phone. FIG. 3 is a schematic diagram showing a schematic configuration of a spread spectrum modulation device that performs spread spectrum modulation processing for W-CDMA using the above filter device.

The spread modulator 301 includes a scrambler 3
02 and a modulation unit 303.

Here, the scramble unit 302 outputs a complex number obtained by scrambling the input real number part and imaginary number part of the digital complex number with a predetermined spreading code of chip rate 1 / D.

Since this embodiment is for W-CDMA, the IMT2000 W-CD is used for scrambling.
Although the one according to the MA system standard is applied, when another wireless communication system (CDMA2000 system standard, wireless LAN IEEE802.11b, etc.) is used, scrambling adapted to the system is performed.

FIG. 3 shows an example of scrambling by combining the real number part and the imaginary number part. In the embodiment shown in FIG. 3, a Gold code having a length of 2 ²⁵ -1 is scrambled as a scrambling code. This Gold code is generated by taking the exclusive OR for each bit of the M sequence generated from the generator polynomial on the finite field GF (2) of two kinds of 25th order.

Incidentally, H. Holma and A. Toskala, "W-CDMA f
or UTMS "(John Wiley and Son, 2001) or 3rd Gener
ation Partnership Project (3GPP); Technical Specif
ication Group Radio Access Network; Spreading and
Module (FDD) (3GTS 25.213), as disclosed in W
-In the CDMA standard, the scrambling code is generated at 3.84 M chips / sec.

The scrambled multi-bit information is converted by a sign mapper (SM) into a “bit string” or “a string of“ bit strings ”, and these are input as a complex number sequence to the filter device in the modulator 303. Given to 101. The output of the filter device 101 in the modulator 303 becomes the output of the spread modulator 301.

The scrambling unit of this spreading code can be configured to scramble any one of a Gold code, a Baker sequence, and a Walsh = Hadamard code as a spreading code.

In addition, the spread code of the scramble part may be given at each point of the trajectory of the mapping dynamical system having the ergodic property. As a mapping dynamical system having an ergodic property, there is a system that uses a Chebyshev polynomial F _a (·) of degree 2 or higher as a map.

The Chebyshev polynomial can be defined by the addition theorem of the cosine function, such as F _a (a, cos θ) = cos (a θ). On the other hand, it can be directly expressed by a rational polynomial as follows. F ₀ (x) = 1; F ₁ (x) = x; F ₂ (x) = 2x ² -1; F ₃ (x) = 4x ³ -3x;

The Chebyshev polynomial y = F _a (x) is a rational mapping that maps the open interval -1 <x <1 to the open interval -1 <y <1.

Chebyshev polynomials of quadratic or higher F _a (·) (a
Generated by the recurrence formula x _{i + 1} = F _n (x _i ) (i ≧ 1) when given an appropriate initial value x ₀ (-1 <x ₀ <1) for ≧ 2) The random numbers included in the random number sequence x ₀ , x ₁ , x ₂ , ... Can be used as the spreading code.

On the other hand, the modulation section 303 has a scrambling section 3
02 to the complex number output by the filter device 10
1 is applied as an input to perform spread modulation. As described above, the chip length of the input digital signal and the delay time of the delay unit 202 in the FIR filter 201 used by the modulator 303 are both equal to the predetermined delay time D.

(Experimental Results) The results of experiments conducted on the characteristics of the filter device 101 used in the above embodiment and the characteristics of the transmitted signal will be described below.

FIG. 4 is a graph showing frequency characteristics of the filter device 101 (horizontal axis represents frequency 0 MHz to 5 MH).
z, the vertical axis represents intensity −90 db to 10 db). FIG. 5 is a graph showing the spectrum distribution of the signal transmitted by the spread modulator 301 (the horizontal axis represents frequency 0 Hz to
0.5 Hz, the vertical axis is -120 db to 10 db).

As shown in FIG. 4, the frequency spectrum of the filter device 101 has an intensity of about -2 db to 2 db for a frequency of 0 MHz to 5 MHz. As shown in FIG. 5, in the frequency spectrum after the spread modulation, the intensity becomes a mountain-bottom shape at the frequencies 0 to 0.1 Hz and 0.4 to 0.5 Hz and becomes low, but 0.15 Hz to 0.35 Hz.
In the range of Hz, the spectrum has a flat intensity.

Looking at these, the frequency characteristic of the filter device 101 shows that the filter (all pa
It can be seen that the filter device 101 does not affect the spectrum distribution of the transmitted signal.

Also, assuming that the transmission rate is 60 kbps, the number of users is 15, and the WWGN channel E ₀ / N ₀ is 10 db, W
-A CDMA system was constructed and a simulated experiment was conducted. Then, according to the conventional method, the bit error rate is 0.00
However, according to the present embodiment, it is 0.000.
It became 75. Therefore, the bit error rate is reduced by about 60%, which shows the effectiveness of the present invention.

Therefore, when the present invention is applied to radio communication, even if a plurality of transmitters and a plurality of receivers communicate in the same frequency band, confidentiality is maintained and the number of communicating parties used. It is possible to communicate with each other while guaranteeing the quality according to.

[0095]

As described above, according to the present invention,
It is possible to provide a filter device, a spread modulation device, a filter method, a spread modulation method, a program, and an information recording medium which are suitable for performing spread modulation using a spread code having good separation performance in wireless communication technology.

[Brief description of drawings]

FIG. 1 is a schematic diagram showing a schematic configuration of a filter device according to a first embodiment of the present invention.

FIG. 2 is a schematic diagram showing a schematic configuration of an FIR filter used in the filter device according to the first embodiment of the present invention.

FIG. 3 is a schematic diagram showing a schematic configuration of a spread spectrum modulator according to a second embodiment of the present invention.

FIG. 4 is a graph showing the results of a simulated experiment of the frequency response of the filter device of the present technique.

FIG. 5 is a graph showing the result of a bit error rate simulation experiment of this method.

[Explanation of symbols]

101 Filter device 102 Input reception section 103 Real processing part 104 Imagination processing unit 105 Output section 201 FIR filter 202 Delay unit 203 amplifier 204 adder 301 Spread modulator 302 Scrambler 303 Modulator

   ─────────────────────────────────────────────────── ─── Continued front page    (72) Inventor Yoshihiro Ishi             Sanshin Building 4 1-20-1 Shibuya, Shibuya-ku, Tokyo             Science and Technology Promotion Agency F term (reference) 5K022 EE01 EE21

Claims (25)

[Claims] 1. A filter for filtering a sequence of complex numbers using a predetermined real impulse constant r (-1 ≦ r ≦ 1), a predetermined real number constant x (x ≠ 0), and a predetermined delay time constant D. In the device, an input reception unit that receives an input of a complex number sequence, and a sequence of a real number part of the complex number sequence that has been input by the input reception unit are 0, D, 2D, 3D,
, (N-1) D (where N is a predetermined positive integer), outputs a plurality of sequences delayed by the real delay unit, and outputs a plurality of sequences delayed by the real delay unit. X (-r) ^{NT / D} if the delay time is T
An actual amplification unit that outputs a plurality of sequences that are multiplied and amplified, a real addition unit that outputs a sum of the plurality of sequences that are amplified and output by the actual amplification unit, and an input is accepted by the input acceptance unit. Of the sequence of complex numbers, the sequence of the imaginary part is 0, D, 2D, 3D,
If the delay time is T for each of the imaginary delay unit that outputs a plurality of sequences delayed by (N-1) D and the plurality of real number sequences delayed and output by the imaginary delay unit , X (-r)
An imaginary amplification unit that outputs a plurality of sequences amplified by ^{NT / D} multiplication, an imaginary addition unit that outputs the sum of the plurality of sequences that are amplified and output by the imaginary amplification unit, and an output by the real addition unit. An output unit that outputs a complex number sequence having the sequence as a real part and the sequence output by the imaginary addition unit as an imaginary part. 2. The filter device according to claim 1, wherein the real delay unit and the imaginary delay unit are “0, D, and 2 respectively.
Delay by D, 3D, ..., (N-1) D ", instead of delaying by D, 2D, 3D, ..., (N-1) D, ND respectively, and the real amplification section and the imaginary amplification section. When the delay time is T, instead of performing “(x (-r) ^{NT / D} times the amplification when the delay time is T”), x (-r) ^{N- (T-1 ) / D} times and amplifies. 3. The filter device according to claim 1, wherein the real amplifying section and the imaginary amplifying section have “the delay time T
If the delay time is T, instead of multiplying by x (-r) ^{NT / D} , then amplifying by x (-r) ^{1 + T / D.} What to do. 4. The filter device according to claim 1, wherein the real delay unit and the imaginary delay unit are “0, D, 2 respectively.
Delay by D, 3D, ..., (N-1) D ", instead of delaying by D, 2D, 3D, ..., (N-1) D, ND respectively, and the real amplification section and the imaginary amplification section. If the delay time is T, instead of "amplify by multiplying x (-r) ^{NT / D} when the delay time is T", multiply by x (-r) ^{T / D} if the delay time is T. Characterized by amplification. 5. A filter device for filtering a sequence of complex numbers using a predetermined impulse constant r (−1 ≦ r ≦ 1) and a predetermined delay time constant D, which accepts an input of a sequence of complex numbers. An input receiving unit, a real processing unit that receives a sequence of a real number part as an input and outputs a filtered sequence of the complex number sequence received by the input receiving unit, and receives an input by the input receiving unit Of the sequence of complex numbers obtained, an imaginary processing unit that receives a sequence of an imaginary number part as an input and outputs a sequence that is filtered, and a sequence output by the actual processing unit is a real number part, and is output by the imaginary processing unit. An output unit that outputs a complex number sequence having the sequence as an imaginary part, and the real processing unit and the imaginary processing unit output a plurality of sequences obtained by delaying the input sequence, Each of the plurality of series is amplified, the sum of the amplified series is output, the delay time of the plurality of series forms an arithmetic progression of the tolerance D, and the amplification factor for each of these is the common ratio -r or Characterized by forming a geometric progression of ratio -1 / r. 6. The filter device according to claim 1, wherein the predetermined actual impulse constant r is equal to 2-3 ^1/2 in a fixed-point number representation with a predetermined precision. Characterized by. 7. The filter device according to claim 1, wherein the real delay unit, the real amplification unit, the real addition unit, the imaginary delay unit, the imaginary amplification unit, and , The imaginary addition unit is ASI
C (Application Specific Integrated Circuit), D
SP (Digital Signal Processor) or FPG
It is characterized by being composed of A (Field Programmable Gate Array). 8. A spread modulator using the filter device according to claim 1, wherein a real number part and an imaginary number part of an input digital complex number are determined at a chip rate of 1 / D. A scramble unit that outputs a complex number scrambled by the spread code of, and a modulator that applies the complex number output by the scramble unit as an input to the filter device to perform spread modulation. 9. The spread modulator according to claim 8, wherein the scrambling by the scrambling unit is IMT.
2000 W-CDMA system standard, CDMA200
0 system standard or wireless LAN IEEE80
Characterized by complying with the 2.11b standard. 10. The spread modulator according to claim 8, wherein the scrambler is a Gold code, a Baker sequence,
Alternatively, one of the Walsh-Hadamard codes is scrambled as a spreading code. 11. The spread modulator according to claim 10, wherein the spread code of the scramble section is given at each point of a trajectory of a mapping dynamical system having an ergodic property. 12. The spread modulator according to claim 11, wherein the mapping dynamical system having an ergodic property of the scramble section is a mapping dynamical system having a Chebyshev polynomial of second order or higher as a mapping. What to do. 13. A filtering method for filtering a sequence of complex numbers using a predetermined impulse constant r (−1 ≦ r ≦ 1) and a predetermined delay time constant D, which accepts an input of a sequence of complex numbers. An input receiving step, an actual processing step of receiving a sequence of a real number part as an input and outputting a filtered sequence of the complex number sequence received in the input receiving step, and inputting in the input receiving step Of the complex number sequence received, the imaginary processing step of receiving the sequence of the imaginary part as an input and outputting the filtered sequence, and the sequence output in the actual processing step as the real part, and the imaginary processing step An output step of outputting a sequence of complex numbers having the sequence output as the imaginary part, and the actual processing step and the imaginary processing step are a plurality of systems in which the input series is delayed. Is output, each of the plurality of sequences is amplified, the sum of the amplified sequences is output, the delay time of the plurality of sequences forms an arithmetic progression of the tolerance D, and the amplification factor for each of these is A method characterized by forming a geometric progression of ratio -r or common ratio -1 / r. 14. The filtering method according to claim 13, wherein the predetermined real impulse constant r is equal to 2-3 ^1/2 in a fixed-point number representation with a predetermined precision. 15. The filtering method according to claim 13, wherein the real delay step, the real amplification step, the real addition step, the imaginary delay step, the imaginary amplification step, and the imaginary addition step. Is an ASIC (Application Specific Integrated Ci
rcuit), DSP (Digital Signal Processor), or FPGA (Field Programmable Gate Array). 16. A spread modulation method using the filter method according to claim 13, wherein a real part and an imaginary part of an input digital complex number are predetermined at a chip rate of 1 / D. A scrambling step of outputting a complex number scrambled by the spreading code of, and a modulation step of performing spread modulation by applying the complex number output in the scrambling step as an input to the filter method. 17. The spreading modulation method according to claim 16, wherein the scrambling in the scrambling step is performed by IM.
T 2000 W-CDMA system standard, CDMA2
000 system standard or wireless LAN IEEE8
A method characterized by complying with the 02.11b standard. 18. The spreading modulation method according to claim 16, wherein, in the scrambling step, any one of a Gold code, a Baker sequence, or a Walsh-Hadamard code is scrambled as a spreading code. And how to. 19. The spreading modulation method according to claim 18, wherein the spreading code in the scrambling step is given at each point of a trajectory of a mapping dynamical system having an ergodic property. 20. The spread modulation method according to claim 19, wherein the mapping dynamical system having an ergodic property in the scrambling step is a mapping dynamical system having a Chebyshev polynomial of second or higher degree as a mapping. how to. 21. A program for causing a computer to function as the filter device according to any one of claims 1 to 7. 22. A program for causing a computer to function as the spread modulator according to any one of claims 8 to 12. 23. A program for causing a computer to execute the filtering method according to claim 13. 24. A program for causing a computer to execute the spread modulation method according to any one of claims 16 to 20. 25. A computer-readable information recording medium (compact disk, flexible disk, hard disk, magneto-optical disk, characterized in that the program according to any one of claims 21 to 24 is recorded.
It includes a digital video disk, magnetic tape, or semiconductor memory. ).