JP2003115562A - Compound semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To solve the problem that a package size cannot be further miniaturized in a package structure where a compound semiconductor chip sticks to the island of a punching frame and is subjected to resin molding. SOLUTION: A ship is stuck onto an insulating substrate, and CSP is achieved. The CSP has a radiation shape where a conductive pattern is extended from the lower portion of the chip to an external connection electrode. In this case, the distance from the chip to a post can be shortened, thus decreasing an inductance constituent, improving insertion loss characteristics, and reducing costs. If it is a switch circuit device, a structure for breaking an RF content by a lead connected to the GND can be achieved, thus improving the isolation and high-frequency characteristics.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a compound semiconductor device, and more particularly, to a compound semiconductor device capable of cost reduction by improving a conductive pattern in a leadless package structure, improving high frequency characteristics, and improving versatility. Regarding

[0002]

2. Description of the Related Art In mobile communication devices such as mobile phones, G
In many cases, microwaves in the Hz band are used, and switching elements for switching these high-frequency signals are often used in antenna switching circuits, transmission / reception switching circuits, and the like (for example, Japanese Patent Laid-Open No. 9-181642). issue). As its element, since it handles high frequencies, a field effect transistor (hereinafter referred to as FE) using gallium arsenide (GaAs) is used.
In most cases, a monolithic microwave integrated circuit (MMIC) in which the switch circuit itself is integrated is being developed.

Conventionally, as a compound semiconductor package, a structure in which an island made of the same material as the leads is die-bonded and resin-molded is generally used. The semiconductor device will be described below by taking a GaAs switching circuit device as an example.

FIG. 9 is a circuit diagram showing a compound semiconductor switch circuit device of the present invention. 1st FET1 and 2nd F
The source electrode (or drain electrode) of ET2 is connected to the common input terminal IN, and the gate electrodes of FET1 and FET2 are connected to the first and second control terminals Ctl-1 and Ctl-2 via resistors R1 and R2, respectively. And F
The drain electrodes (or source electrodes) of ET1 and FET2 are connected to the first and second output terminals OUT1 and OUT2. First and second control terminals Ctl-
1, the control signal applied to Ctl-2 is a complementary signal, the FET on the side to which the H level signal is applied is turned on, and the input signal applied to the common input terminal IN is output to either output terminal. It is designed to be transmitted to. Resistance R
1, R2 are control terminals Ctl-1 and Ct that are AC grounded
It is arranged for the purpose of preventing the high-frequency signal from leaking through the gate electrode with respect to the DC potential of 1-2.

FIG. 10 shows an example of a compound semiconductor chip in which such a compound semiconductor switch circuit device is integrated.

FET1 and FET2 for switching are arranged in the center of a GaAs substrate, and resistors R1 and R2 are connected to the gate electrodes of each FET. Further, the common input terminal IN, the output terminals OUT1 and OUT2, the control terminal Ctl-
Pads corresponding to 1 and Ctl-2 are provided around the substrate. In addition, the wiring of the second layer shown by the dotted line is for each FE.
The gate metal layer (Ti / Pt / Au) 20 is formed at the same time when the gate electrode of T is formed. The wiring of the third layer shown by the solid line is a pad metal layer (Ti) for connecting each element and forming a pad. / Pt / Au) 40. An ohmic metal layer (AuG) that is in ohmic contact with the first substrate.
e / Ni / Au) 10 forms the source electrode and drain electrode of each FET and the extraction electrodes at both ends of each resistor, and is not shown in FIG. 2 because it overlaps with the pad metal layer.

FIG. 11 shows a structure in which the above switch circuit device is mounted. FIG. 11A is a top view and a cross-sectional view is shown in FIG.

The compound semiconductor chip 63 on which the switch element is formed is fixedly mounted on the island 62e of the lead frame by the brazing material 70 such as solder, and each electrode pad of the compound semiconductor chip 63 and the lead 62 are connected by the bonding wire 64. To be done. The control terminal Ctrl-2 is the lead 62a, the input terminal IN is the lead 62b, and the control terminal Ct.
rl-1 is the lead 62c, and the output terminal OUT1 is the lead 6
2d and OUT2 are connected to the lead 62f, respectively. The island 62e to which the semiconductor chip 63 is fixed is GND
It becomes a terminal. The peripheral portion of the semiconductor chip 63 is covered with a resin 75 matching the shape of the molding die, and the tip portion of the lead 62 is led out of the resin 75.

[0009]

In the conventional package structure of a compound semiconductor switch circuit device, a lead frame adapted to a large chip size is used because it is necessary to be used for semiconductor chips of various sizes for general use. It was Therefore, firstly, in a small chip, there is a problem that the distance to the lead is long and the gold wire of the wire bond becomes long. A long gold wire not only increases the inductance component but also increases the dielectric loss (loss due to the generation of overcurrent in the molding resin) and increases the insertion loss. It was. Furthermore, high-frequency leakage through the resin becomes large, which is a cause of deterioration of isolation characteristics.

Further, if the lead frame adapted to the individual size is adopted, the cost is increased accordingly. At present, the performance of silicon semiconductor chips has been remarkably improved, and the possibility of use in the high frequency band is increasing. For example, a local oscillation circuit using a silicon semiconductor transistor having an f _T (cutoff frequency) of 25 GHz or more can achieve performance close to that of a local oscillation circuit using a GaAs FET by devising an application circuit. In the past, silicon chips were difficult to use in the high frequency band, and expensive compound semiconductor chips were used.However, if the performance of silicon semiconductor chips is improved and it is possible to use them, the wafer itself will naturally be an expensive compound semiconductor. Chips lose in price competition. Further, even if the compound semiconductor chip is downsized and the cost is reduced, the advantage of the downsized chip will not be exhibited at all even if the package outer shape is large. Therefore, downsizing of the package is strongly desired.

[0011]

The present invention has been made in view of the above-mentioned circumstances, and an insulating substrate serving as a supporting substrate and a surface of the insulating substrate are fixed with an insulating resin, and a plurality of insulating substrates are provided on the surface. A compound semiconductor chip having electrodes, a through hole provided corresponding to a plurality of electrodes, penetrating the insulating substrate, and a surface of the insulating substrate, individually corresponding to the plurality of electrodes,
A conductive pattern radially extending from the compound semiconductor chip fixing portion to the through hole, a connecting means for connecting a plurality of electrodes and the conductive pattern, and an external connection electrode corresponding to the through hole and provided on the back surface of the insulating substrate. It is characterized by having. As a result, the compound semiconductor device is packaged in a chip size package (CSP).
By adopting e), a miniaturization of the package can be realized, and further, a compound semiconductor device which can improve high frequency characteristics can be realized.

[0012]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described in detail below.

The compound semiconductor device of the present invention comprises an insulating substrate 1.
, The conductive pattern 2, the semiconductor chip 3, and the connecting means 4
, Through hole 5 and external connection electrode 6.

As shown in FIG. 1, a plurality of (for example, 100) package regions 10 corresponding to one semiconductor chip are arranged vertically and horizontally on the substrate 1. The substrate 1 is a large-sized insulating substrate made of ceramic, glass epoxy, or the like, and one or several of them are stacked to have a total plate thickness of 180 to 250 μm and a plate thickness capable of maintaining mechanical strength in the manufacturing process. have.

FIG. 2 shows a conductive pattern according to the first embodiment of the present invention.

The conductive pattern 2 is composed of six leads provided on the insulating substrate 1 by gold plating, corresponds to the electrode pads arranged on the outer periphery of the semiconductor chip, and further has a through hole 5 provided with an external connection electrode. And correspond individually. The portion indicated by the alternate long and short dash line is the region 10 for packaging the individual semiconductor chips. Each lead 2 corresponds to an electrode pad, and there is no one corresponding to the conventional island portion (FIG. 2 (A)). The semiconductor chip is fixed to the dotted area 11 by an insulating adhesive, each lead 2 may have any shape under the chip, and the semiconductor chip may be fixed over a plurality of leads (FIG. 2 ( B)).

FIG. 3 shows a second embodiment of the present invention. The conductive pattern 2 is composed of six leads 2 provided on the insulating substrate 1, and is provided corresponding to the electrode pads arranged on the outer periphery of the semiconductor chip. The conductive pattern 2 formed by gold plating extends radially from the semiconductor chip fixing region 11 shown by the dotted line to the through hole 5 penetrating the insulating substrate 1. There is nothing corresponding to the conventional island portion in the fixing region 11 of the semiconductor chip, and the semiconductor chip is fixed by the insulating resin on the leads 2 focused at the substantially center of the fixing region 11. These conductive patterns 2 have the same shape for each package region 10 and are continuously provided by the connecting portion 12. Each package area 10 has, for example, a long side ×
The short side has a rectangular shape of 1.2 mm × 0.8 mm, and the fixed region 11 has, for example, 0.30 mm × 0.37 m.
The fixed area 11 is different depending on the size of the semiconductor chip. The conductive patterns 2 in each package region 10 are arranged vertically and horizontally with a space of 100 μm therebetween. The spacing serves as a dicing line in the assembly process. Here, each pattern 2 is provided by gold plating, but electroless plating may be used. In this case, since it is not necessary to connect, each conductive pattern is provided individually.

FIG. 4 shows the semiconductor chip 3. The semiconductor chip 3 is a compound semiconductor switch circuit device, and the back surface is a semi-insulating GaAs substrate. In this switch circuit device, FET1 and FET2 for switching are arranged in the central portion on a GaAs substrate, and resistors R1 and R2 are connected to a gate electrode 17 of each FET. Further, the common input terminal IN, the output terminals OUT1 and OUT2, the control terminal Ct
Pads corresponding to 1-1 and Ctl-2 are provided around the substrate. The second-layer wiring shown by the dotted line is for each F
The gate metal layer (Ti / Pt / Au) 20 is formed at the same time when the gate electrode 17 forming the Schottky junction is formed with the channel region 14 of the ET, and the third layer wiring shown by the solid line is the connection of each element. And a pad metal layer (Ti / Pt / Au) 40 for forming a pad. An ohmic metal layer (AuG) that is in ohmic contact with the first substrate.
e / Ni / Au) 10 forms the source electrode 13 and the drain electrode 15 of each FET and the extraction electrodes at both ends of each resistor, and is not shown in FIG. 4 because it overlaps with the pad metal layer. The circuit diagram in the embodiment of the present invention is the same as that in FIG.

The semiconductor chip 3 is mounted on the insulating substrate 1 with reference to FIG.
The following shows an example of fixing to. The semiconductor chip 3 is fixed to each pattern of the substrate 1 on which the leads 2 of the gold plating layer are formed.

Since this semiconductor chip 3 is a switch circuit device, an input terminal IN and a control terminal C are provided on the surface of the chip.
trl-1, Ctrl-2, output terminals OUT1, OUT
Five electrode pads connected to 2 are arranged so as to surround the outer periphery of the chip. Since the back surface is semi-insulating, it is fixed with an insulating adhesive across all of the focused leads 2, and the electrode pads and leads 2 are connected by bonding wires 4, respectively.

The bonding wire 4 is used for the semiconductor chip 3
The respective electrode pads and the lead 2 are connected. Control terminal Ct
rl-1 is connected to the lead 2c, the input terminal IN is connected to the lead 2b, the control terminal Ctrl-2 is connected to the lead 2a, the output terminal OUT1 is connected to the lead 2d, and the output terminal OUT2 is connected to the lead 2f. The back surface of the semiconductor chip 3 is a semi-insulating substrate, and the lead 2e has the GND potential. Since the lead 2 is provided at a position corresponding to the electrode pad and extends to the bottom of the semiconductor chip 3, the wire bond post is used as the semiconductor chip 3.
Can be closer to. That is, the bonding wire 4 has the minimum required length, and all the leads 2
It has almost the same length.

Further, since the leads 2 are provided so as to extend radially from the semiconductor chip fixing region, the distance from each electrode pad to the corresponding lead 2 can be set to a substantially constant value even when the chip size is different. That is, the bonding wire 4 may have a substantially constant minimum length,
The inductance component, which is an important parameter of high frequency characteristics, can be reduced. In addition, various chip sizes can be universally supported without recreating a pattern according to the chip size (Fig. 5).
(B)).

Since the conductive pattern 2 uses thick film printing for forming the plating pattern, the minimum distance between the patterns (leads) can be set to 75 μm. This is because when a conventional frame is adopted, the limit of punching the frame by stamping is the plate thickness of the frame (150
.mu.m) .times.0.8, and the distance between leads can be greatly reduced compared to the fact that this minimum interval was 120 .mu.m.
This will greatly contribute to the miniaturization of the package.

FIG. 6 is a sectional view showing a compound semiconductor switch circuit device formed by incorporating the compound semiconductor chip 3 into a package.

Through holes 5 corresponding to the leads 2 are provided in the substrate 1. The through hole 5 penetrates the substrate 1, and the inside is filled with a conductive material such as tungsten. The external connection electrode 6 corresponding to each through hole 5 is provided on the back surface.

The compound semiconductor chip 3 has an insulating adhesive 50.
The electrode pads of the chip 3 are electrically connected to the external connection electrodes 6 at the positions corresponding to the respective positions via the wires 4, the leads 2 and the through holes 5, respectively. Has been done.

That is, the six external connection electrodes 6 are arranged in a pattern that is symmetrical with respect to the center line of the package outer shape (up and down). Specifically, the control terminal Ctrl-1, the input terminal IN, the control terminal Ctrl-2 are provided along one side of the package side surface, and the output terminal OUT1, the GND terminal, and the output terminal OUT2 are provided along the other side of the package side surface. They are arranged in order.

The four sides of the periphery of the package are formed by the cut surface of the resin layer 15 and the insulating substrate 1, the upper surface of the package is formed by the flattened surface of the resin layer 15, and the lower surface of the package is the rear surface side of the insulating substrate 1. Is formed by.

In this compound semiconductor switch circuit device, the compound semiconductor chip 3 is sealed by covering the insulating substrate 1 with a resin layer 15 of about 0.3 mm. The compound semiconductor chip 3 has a thickness of about 130 μm. The bonding wire 4 can have a wire bonding post at a position closer to the semiconductor chip 3, and thus the bonding wire 4 has a necessary minimum length.

The front surface side of the package is the entire resin layer 15, and the external connection electrodes 6 of the insulating substrate 1 on the back surface side are arranged in a left-right (upper and lower) symmetrical pattern, which makes it difficult to determine the polarity of the electrodes. Therefore, it is preferable to form a recess on the surface side of the resin layer 15 or to print it to form a mark for indicating the polarity.

Here, FIG. 7 shows a third embodiment of the present invention. FIG. 7 is a cross-sectional view, and the plan view is the second view shown in FIG.
Since it is the same as that of the embodiment, the description thereof will be omitted. This is a multi-chip module of the CSP of the second embodiment, and has a structure in which a conductive pattern is embedded in an insulating resin that serves as a support substrate.

The insulating resin 21 serving as a support substrate completely covers the semiconductor chip 23 and the plurality of conductive patterns (leads) 22, and the isolation groove 31 between the leads 22 is filled with the insulating resin 21 to form the leads 22. It is fitted with a curved structure of the side surface (the lead side surface is curved, although not shown), and is firmly coupled. The leads 22 are supported by the insulating resin 21. The semiconductor chips 23 fixed to the leads 22 are also collectively covered and commonly molded. As the resin material, a thermosetting resin such as an epoxy resin can be realized by transfer molding, and a thermoplastic resin such as a polyimide resin or polyphenylene sulfide can be realized by injection molding.

The thickness of the insulating resin 21 is equal to the semiconductor chip 2
About 50 μm from the top of the bonding wire 24 of No. 3
The degree is adjusted to be covered. This thickness is
It can be made thicker or thinner in consideration of strength. Further, the surface of the insulating resin 21 is flattened by annealing. This is because, particularly when the insulating resin 21 is formed to have a large area, the coefficient of thermal expansion between the conductive foil 30 which is the material of the lead 22 and the molding resin which forms the insulating resin 21 and after the reflow process. The conductive foil 30 is warped due to the difference in molding shrinkage ratio when the temperature decreases. That is, the surface of the insulating resin 21 is flattened by annealing in order to suppress the occurrence of warpage.

The bonding wire 24 connects each electrode pad of the semiconductor chip 23 and each lead 22. Wire bonding is performed collectively by ball bonding by thermocompression bonding and wedge bonding by ultrasonic waves, and control terminal Ctrl-1, input terminals IN, Ctrl-
2. Connect the output terminals OUT1 and OUT2 to the leads 22. One of the leads connects to the back of the semiconductor chip,
It becomes a GND terminal. Since the lead 22 is provided at a position corresponding to the electrode pad and the wire bond post can be located near the chip, the bonding wire 24 should have a minimum required length and be substantially the same length for all the leads 22. You can

The conductive pattern 22 is embedded in the insulating resin 21 and is provided radially from the semiconductor chip fixing region so as to correspond to the electrode pads arranged on the outer periphery of the semiconductor chip 23. There is nothing that corresponds to the conventional island portion in the fixing region, and the semiconductor chip 23 is fixed by the insulating adhesive 50 on the leads 22 that are converged at approximately the center of the fixing region.

As will be described later, as shown in FIG. 7B, the conductive pattern 22 is a conductive foil 30. The conductive foil 30 provided with the separation groove 31 is separated as the conductive pattern 22 by chemically and / or physically removing the back surface by polishing, grinding, etching, metal evaporation of a laser, or the like. As a result, the back surface of the conductive pattern 22 is exposed on the insulating resin 21.

The semiconductor chip 23 is the same as that of the second embodiment, so its details will be omitted. Here, it is a compound semiconductor switch circuit device, and the back surface is semi-insulating GaA.
s substrate. Since it is a switch circuit device, the chip surface has an input terminal IN, control terminals Ctrl-1, C
5 connected to trl-2 and output terminals OUT1 and OUT2
The individual electrode pads are arranged so as to surround the outer periphery of the chip. Since the back surface is semi-insulating, it is fixed to the focused leads 22 with an insulating adhesive across all the leads 22, and the electrode pads and the leads 22 are connected by the bonding wires 24, respectively.

The external connection electrode 26 is provided by covering each lead 22 which is a conductive pattern with a resist 27 and opening a desired position to supply solder. As a result, it has a feature that it can be moved horizontally by the surface tension of solder or the like during mounting and can be self-aligned.

FIG. 8 shows a conductive foil 30 on which a conductive pattern is formed. The thickness of the conductive foil 30 is preferably about 10 μm to 300 μm in consideration of later etching, and here, 70 μm (2 ounces) of copper foil was used. But 30
It suffices if the separation groove 31 having a thickness of 0 μm or more or 10 μm or less can be formed that is shallower than the thickness of the conductive foil 30. As a result, a plurality of (here, 4 to 5) blocks 32 in which a large number of fixing regions are formed are arranged on the strip-shaped conductive foil 30 while being spaced apart from each other (FIG. 8A).

FIG. 8B shows a concrete conductive pattern 22. This figure is an enlargement of one of the blocks 32 shown in FIG. A portion indicated by a dotted line is one package region 10, and a large number of conductive patterns 22 are arranged in a matrix in one block 32. For the conductive pattern 22, at least the region other than where the conductive pattern 22 is formed is etched to form the separation groove 31 to form the conductive pattern 22. The material of the conductive foil 30 is selected in consideration of the adhesiveness, the bonding property, and the plating property of the brazing material, and the material is a conductive foil mainly composed of Cu, a conductive foil mainly composed of Al or Fe. -Ni
A conductive foil or the like made of an alloy such as is used.

Further, since the conductive pattern 22 can be formed by etching, the inter-pattern distance is significantly increased as compared with the conventional punching frame in which the frame thickness (150 μm) × 0.8 is the limit of the inter-pattern distance. The feature of the second embodiment that can be reduced in size and greatly contributes to the miniaturization of the package is that the conductive foil 30 serving as the conductive pattern 22 serves as a support substrate until the insulating resin 21 is covered. The conductive foil 30 serving as a supporting substrate is a material required as an electrode material. Therefore, there is a merit that the constituent materials can be omitted as much as possible, and the cost can be reduced.

Further, since the separation groove 31 is formed to be shallower than the thickness of the conductive foil 30, the conductive foil 30 is not individually separated as the conductive pattern 22. Therefore, the sheet-shaped conductive foil 30 can be handled as a unit, and the insulating resin 21
In this embodiment, the conductive foil 30 has been described in the present embodiment, but the substrate is a silicon wafer or a ceramic substrate. The same applies to the case of using a material such as a copper frame.

The elements that can be mounted are not limited to compound semiconductor switch circuit devices, other integrated circuits, semiconductor chips such as transistors and diodes, but passive elements such as chip capacitors, chip resistors, and chip inductors, and thicker. However, surface mount devices such as face-down semiconductor devices such as CSP and BGA are all possible.

The feature of the present invention resides in the CSP in which the chips are fixed on the radial leads.

As a result, the package of the compound semiconductor chip can be miniaturized, and the length of the bonding wire can be greatly shortened as compared with the conventional one, so that the high frequency characteristics can be greatly improved. Further, this effect becomes more remarkable in the high frequency band of 10 GHz or higher.

[0046]

According to the present invention, the radial lead extending from the semiconductor chip fixing region to the external connection electrode is provided, and the semiconductor chip is fixed by the insulating adhesive, so that the package size is greatly reduced. It is a thing.

As a result, first, all the bonding wires used for connection can be made to have substantially the same length with the minimum required length. As a result, the inductance component of the gold wire and the dielectric loss (loss due to the generation of overcurrent in the resin) can be reduced, so that the Insertion Loss
The characteristics are improved. This is because the leads are all provided below the semiconductor chip at positions corresponding to the electrode pads, and the wire bond posts can be located close to the chip. Further, if the bonding wire is short, the high frequency leakage through the resin is reduced and the isolation characteristic is improved.

Secondly, since the minimum interval between patterns can be reduced, the miniaturization of the package can be realized also by this. Conventionally, a punching frame has been adopted, and the limit when punching by stamping is the plate thickness x 0.8.
This is because the pattern can be formed by thick film printing by plating or etching of the conductive foil in the present invention. Specifically, in the case of the frame 120μ
The minimum distance, which was m, can be reduced to 75 μm, which can greatly contribute to miniaturization of the package.

Third, even if the size of the semiconductor chip to be mounted is changed, the same conductive pattern can be used, and the bonding wires used for connection can always be made to have substantially the same length with the minimum required length. . This is because the pattern is formed radially and extends under the chip, so that the distance from each pad electrode to the lead can be made substantially constant regardless of the chip size. This allows
Since it is not necessary to prepare a pattern for each chip size and the bonding wire is not wastefully used, it also contributes to cost reduction.

Fourthly, particularly when the semiconductor chip is a compound semiconductor switch circuit device, the control terminals Ctrl-1 and Ctrl-2 and the GND terminal which become the GND potential in the high frequency become the RF line, the input terminal IN and the output terminal. OUT
By arranging it between 1 and OUT2, it becomes a structure that blocks a high frequency signal, so that there is an advantage that the isolation characteristic is improved.

[Brief description of drawings]

FIG. 1 is a perspective view for explaining the present invention.

FIG. 2 is a plan view for explaining the present invention.

FIG. 3 is a plan view for explaining the present invention.

FIG. 4 is a plan view for explaining the present invention.

FIG. 5 is a plan view for explaining the present invention.

FIG. 6 is a cross-sectional view for explaining the present invention.

FIG. 7 is a sectional view for explaining the present invention.

FIG. 8 is a plan view for explaining the present invention.

FIG. 9 is a circuit diagram for explaining a conventional technique.

FIG. 10 is a plan view for explaining a conventional technique.

FIG. 11 is a plan view (A) and a sectional view (B) for explaining a conventional technique.

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁷ Identification code FI theme code (reference) H01L 27/095 29/812 (72) Inventor Hideyuki Inokume 2-5-5 Keihanhondori, Moriguchi-shi, Osaka Sanyo Electric Co., Ltd. (72) Inventor Haruhiko Sakai 2-5-5 Keihan Hondori, Moriguchi-shi, Osaka Sanyo Electric Co., Ltd. (72) Inventor Shigeo Kimura Company 2-chome, Keihanhondori, Moriguchi-shi, Osaka No. 5 No. 5 Sanyo Electric Co., Ltd. F term (reference) 5F038 AZ06 CA02 CA09 DF02 EZ02 EZ07 EZ20 5F102 FA10 GA01 GA17 GB01 GC01 GD01 GS02 GS09 GT03 GV03

Claims (9)

[Claims] 1. An insulating substrate serving as a supporting substrate, a compound semiconductor chip fixed to the surface of the insulating substrate with an insulating resin and having a plurality of electrodes on the surface, and a plurality of electrodes provided on the surface of the insulating substrate. A conductive pattern individually corresponding to each other, connecting means for connecting the plurality of electrodes to the conductive pattern, a through hole corresponding to the conductive pattern and penetrating the insulating substrate, and a corresponding insulating layer corresponding to the through hole. A compound semiconductor device, comprising: an external connection electrode provided on the back surface of the substrate. 2. The compound semiconductor device according to claim 1, wherein the compound semiconductor chip is fixed on the plurality of conductive patterns. 3. The compound semiconductor device according to claim 1, wherein the back surface of the compound semiconductor chip is a semi-insulating substrate. 4. An insulating substrate serving as a supporting substrate, a compound semiconductor chip fixed to the surface of the insulating substrate with an insulating resin and having a plurality of electrodes on the surface thereof, provided in correspondence with the plurality of electrodes, A through hole penetrating the insulating substrate, and corresponding to the plurality of electrodes individually on the surface of the insulating substrate,
A conductive pattern that radially extends from the compound semiconductor chip fixing portion to the through hole, a connecting means that connects the plurality of electrodes and the conductive pattern, and a back surface of the insulating substrate corresponding to the through hole. And an external connection electrode. 5. An insulating resin serving as a support substrate, a compound semiconductor chip embedded in the insulating resin and having a plurality of electrodes on the surface thereof, embedded in the insulating resin and individually corresponding to the plurality of electrodes. A conductive pattern that is provided radially around the compound semiconductor chip, a connecting means that connects the plurality of electrodes to the conductive pattern, and an external connection electrode corresponding to the conductive pattern exposed from the back surface of the insulating resin. A compound semiconductor device comprising: 6. The compound semiconductor device according to claim 4, wherein the compound semiconductor chip is fixed on the plurality of conductive patterns. 7. The back surface of the compound semiconductor chip is a semi-insulating substrate, wherein the back surface is a semi-insulating substrate.
The compound semiconductor device according to item 1. 8. The compound semiconductor device according to claim 4, wherein the connecting means are bonding wires having substantially the same length. 9. The compound semiconductor device according to claim 4, wherein the compound semiconductor chip is a switch circuit device.