JP2003115189A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve yield of system LSI in a semiconductor device constituting a system LSI having a semiconductor memory circuit section and a logic circuit section. SOLUTION: An internal clock 109 for self-refresh and a refresh-enable signal 110 are transferred to a memory control circuit 107 of a logic circuit section 1 from a refresh-circuit section 108 of a DRAM core section 2. In the memory control circuit 107, a refresh-period is decided based on these internal clock 109 and the enable-signal 110. The logic circuit section 1 adjusts automatically a occurrence period of a refresh-command in accordance with the decided refresh-period.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having a large-scale memory core (memory IP) mounted together with a logic circuit and an analog circuit, that is, an LS in a so-called system LSI
The present invention relates to simultaneous production of various types of I, improvement in yield, and ease of IP implementation of the memory core itself.

[0002]

2. Description of the Related Art In recent years, a large-scale integrated circuit in which a logic circuit or an analog circuit (hereinafter referred to as a logic circuit or the like) and a semiconductor memory circuit are mounted together is called a system LS.
It has been developed and put into practical use as I. Nowadays, with the progress of miniaturization of processes and the sub-quarter micron generation, a logic circuit having a larger number of gates and a semiconductor memory circuit having a larger capacity are being mixedly mounted. In particular, a large-capacity dynamic random access memory core (IP) of several Mbit to several 100 Mbit is used as the semiconductor memory circuit for applications such as image processing and data buffer.

As a configuration example of a semiconductor memory circuit which is conventionally mounted on a system LSI, particularly a dynamic random access memory core (DRAM core), for example, IS
SCC Digest of Technical Pap
ers, pp. 72-73, Feb. , 1998. Including this configuration example, FIG. 18 shows a block configuration diagram of this conventional system LSI.

In FIG. 18, A is a system LSI having a logic circuit section 1 and a DRAM core section 2. Reference numerals 3, 4 and 5 are control signal lines for controlling reading and writing from the logic circuit unit 1 to the DRAM core unit 2, address signal lines for designating memory cells, and the logic circuit unit 1 to the DRAM core unit 2 at the time of writing data. It is an input data line for write data output to. Reference numeral 6 is an output data line through which the data read from the DRAM core unit 2 at the time of reading data is output to the logic circuit unit 1, 7
Is a memory control circuit provided in the logic circuit unit 1.

The conventional system L configured as described above
In SI, a read or write control signal and an address signal are output from the memory control circuit 7 of the logic circuit unit 1 to the DRAM core unit 2 on the control signal line 3 and the address signal line 4, and further data is written at the time of data writing. The data is output to the input data line 5, and the DRAM core unit 2
Is input to. At the time of data reading, the data read from the DRAM core unit 2 is transferred to the logic circuit unit 1 via the output data line 6.

[0006]

By the way, the system L
When the SI is manufactured by the manufacturing process of the general-purpose DRAM, the necessary process for manufacturing the DRAM is added to the process specification, which is caused by the large amount of heat treatment peculiar to the general-purpose DRAM process. However, there is a problem in that the performance of the system LSI itself cannot be achieved because the performance of the logic circuit and the like deteriorates. Further, when the memory cell of the DRAM is a stack type memory cell, the distance between the device such as a transistor and the wiring layer becomes large, the aspect ratio of the via (contact) becomes large, and the yield and the like increase as the size decreases. There is a problem that serious impact will occur.

Therefore, conventionally, the manufacturing process when the DRAM and the logic circuit and the like are mounted together is such that the logic circuit part including the wiring part is easily manufactured and the performance of the logic circuit is maximized. In many cases, the specifications will be adversely affected, but this specification may adversely affect the performance of the DRAM, especially the performance related to refreshing. On the other hand, the performance of the DRAM from the system side is as follows.
There is a case where performance equivalent to that of a general-purpose DRAM or higher performance is required for system differentiation.

However, in the conventional structure in which only the control signal, the address and the input / output data are exchanged between the DRAM core 2 and the logic circuit section 1 as described with reference to FIG. When the required DRAM performance is close to the performance near the process limit, the DRAM side may not be able to meet the timing of the control signal issued from the logic circuit unit 1 due to variations in the manufacturing process, and it may not function as a system LSI. Therefore, the yield of the system LSI is reduced.

Further, it is very difficult to satisfy the various system requirements with the same DRAM core, and the range of applicable system LSIs is limited only by the characteristic improvement by the improvement of the DRAM circuit and the operation margin expansion. I will end up. Therefore, it is necessary to have a lineup of a plurality of DRAM cores (IP).

Further, with this DRAM core as an IP, various processes, for example, processes with different specifications developed by a plurality of semiconductor manufacturing companies, and even with the same semiconductor manufacturing company, specifications such as process variations and versions are provided. When manufacturing in different processes, there is a technical problem that basically one design can correspond to only one process because the core design is single.

In order to actually manufacture the core, conventionally, by using device parameters such as a transistor, a resistance and a capacitance in an applied process, a partial circuit design change or a complete redesign is performed in circuit tuning. Although it had to be done, there is a drawback that a large number of design man-hours must be added at the time of process improvement and deployment.

In view of the above points, the present invention has an object to provide a system LSI in which a large-scale memory IP is mounted together.
In addition to increasing the system LSI yield, memory I
An object of the present invention is to provide a semiconductor device capable of expanding the application range of P.

[0013]

In order to achieve the above object, according to the present invention, in a semiconductor device as a system LSI having a memory IP and a logic circuit portion, characteristic variations due to process variations of the memory IP are caused in the logic circuit. The logic circuit section is optimized by feeding back to the section.

That is, a semiconductor device according to a first aspect of the present invention is a semiconductor device having a semiconductor memory circuit section having a memory cell array and a logic circuit section for realizing a system function, wherein the logic circuit section has Change means is provided for receiving an internal control signal of the semiconductor memory circuit section and changing the function or operation timing of its own logic circuit section according to the internal control signal.

According to a second aspect of the present invention, in the semiconductor device according to the first aspect, the semiconductor memory circuit section is a dynamic random access memory, and the internal control signal is an internal refresh control signal. .

According to a third aspect of the present invention, in the semiconductor device according to the second aspect, the internal refresh control signal is a clock that determines a refresh cycle in a self refresh mode, and the changing means of the logic circuit section includes: It is characterized in that the cycle of the clock is measured and the function or operation timing of its own logic circuit section is changed according to the measurement result.

According to a fourth aspect of the present invention, in the semiconductor device according to the third aspect, the changing means of the logic circuit section operates a clock for determining a refresh cycle of the self-refresh mode and the logic circuit section. A master clock is input, and the refresh cycle of the semiconductor memory circuit unit is measured based on the both clocks.

According to a fifth aspect of the present invention, in the semiconductor device according to the third aspect, the function of the logic circuit section changed by the changing means is in the order or timing of refresh control to the semiconductor memory circuit section. It is characterized by being.

A semiconductor device according to a sixth aspect of the present invention is a semiconductor device having a semiconductor memory circuit section having a memory cell array and a logic circuit section for realizing a system function, wherein the semiconductor memory circuit section is the memory. Information output means for outputting information based on the function and characteristics of the cell array is provided, and the logic circuit section receives the information from the information output means, and the function or operation timing of its own logic circuit section according to the information. It is characterized in that a changing means for changing is provided.

According to a seventh aspect of the present invention, in the semiconductor device according to the sixth aspect, the information output means of the semiconductor memory circuit section includes a plurality of fuse elements made of metal and polycide or polysilicon wiring material. Have,
Information based on a function or a characteristic of the memory cell array is set by laserly or electrically cutting one of the fuse elements.

According to an eighth aspect of the present invention, in the semiconductor device according to the sixth aspect, the information output means of the semiconductor memory circuit section has a plurality of anti-electrodes formed by arranging a thin insulating film between two electrodes. It is characterized by having a fuse element, and electrically connecting any of the plurality of anti-fuse elements by applying an electric field to set information based on the function or characteristic of the memory cell array.

A semiconductor device according to a ninth aspect of the present invention is a semiconductor device having a semiconductor memory circuit section having a memory cell array and a logic circuit section for realizing a system function, wherein the semiconductor memory circuit section is the memory. A self-test circuit for self-testing the cell array, wherein the logic circuit section receives a self-test result of the self-test circuit, and changes the function or operation timing of the self-logic circuit section according to the self-test result. Means are provided.

The invention according to claim 10 is the same as claim 1,
The semiconductor device according to 6 or 9 is characterized in that the function of the logic circuit unit changed by the changing unit is an order or timing of access control to the semiconductor memory circuit unit.

[0024] The invention according to claim 11 is the above-mentioned claim 10.
In the semiconductor device described above, the operation timing of the logic circuit unit changed by the changing unit is a setup timing of a control signal, an address and write data output to the semiconductor memory circuit unit.

The invention according to claim 12 is the same as claim 1,
In the semiconductor device according to 6 or 9, the operation timing of the logic circuit unit changed by the changing unit is
It is characterized in that the timing is a timing at which data output from the semiconductor memory circuit unit is fetched.

The invention according to claim 13 is the same as claim 1,
The semiconductor device according to 6 or 9 is characterized in that an analog circuit unit is also provided together with the semiconductor memory circuit unit and the logic circuit unit.

The invention of claim 14 is the same as claim 1,
The semiconductor device according to 6 or 9 is characterized in that the semiconductor memory circuit unit is a dynamic random access memory.

The invention according to claim 15 is the same as claim 1,
The semiconductor device according to 6 or 9 is characterized in that the semiconductor memory circuit unit is a static random access memory.

As described above, according to the present invention, in the semiconductor device as the system LSI including the semiconductor memory circuit section and the logic circuit section for realizing the system function,
The internal control signal of the semiconductor memory circuit unit, information such as the function and characteristics of the semiconductor memory circuit unit, or the self-test result of the semiconductor memory circuit unit is transferred to the logic circuit unit, and the function of the logic circuit unit or Since the operation timing is changed, a desired system LSI can be obtained in a short time as compared with the case where the manufacturing process is improved, and a decrease in the yield of the system LSI can be suppressed. In addition, various system requirements can be realized with the same semiconductor memory circuit unit. Further, the same semiconductor memory circuit unit can be used as a common IP for processes having different specifications. In addition, it becomes possible to manufacture products with different specifications on the same wafer, which can be expected to improve manufacturing efficiency.

[0030]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Semiconductor devices according to embodiments of the present invention will be described below with reference to the drawings.

(First Embodiment) FIG. 1 shows a first embodiment of the present invention.
2 shows a block configuration of an entire system LSI as a semiconductor device of the embodiment.

In the figure, 1 is a logic circuit section, 2 is a DRAM core section (semiconductor memory circuit section) which is a core section of a dynamic random access memory having a memory cell array inside, and both are logic circuit section 1 From the DRAM core unit 2 to the logic circuit unit 1 while being connected by the control signal line 3, the address signal line 4, and the input data line 5 output from the DRAM core unit 2 to the logic circuit unit 1. Connected.

Reference numeral 107 is a memory control circuit arranged in the logic circuit section 1, and 108 is a refresh circuit section arranged in the DRAM core 2. 109 and 11
0 is an internal clock for self-refresh and a refresh activation signal generated in the refresh circuit section 108, and both are output to the memory control circuit 107 of the logic circuit section 1. The internal clock 109 for self-refresh is a clock CLKREF that determines the refresh cycle in the self-refresh mode as shown in FIG. 6 described later, and is an internal control signal (internal refresh control) generated inside the DRAM core unit 2. Signal).

The internal configuration of the memory control circuit 107 of the logic circuit section 1 is shown in FIG. In the figure,
170 receives the signal 11 related to memory access and receives D
A command generation circuit that generates a command for the RAM core unit 2 and a refresh command generation circuit 171 that generates a refresh command for the DRAM core unit 2 can automatically change the command generation period. Further, 172 is a read / write command timing circuit for receiving the command generated by the command generating circuit 170 and controlling the generation timing of the read / write command, and 173 is a DRAM similarly receiving the command generated by the command generating circuit 170. An active / precharge command timing circuit for controlling the generation timing of the active / precharge command of the core unit 17,
Reference numeral 4 is a data input / latch circuit which is connected to the DRAM core section 2 by an output data line 6 and takes in data from the DRAM core section 2. Further, a command generation order arbitration circuit 175 arbitrates the output order of the refresh command from the refresh command generation circuit 171 and the read / write command and the active / precharge command from the two command timing circuits 172 and 173. To do. 176 is a multiplexer,
The command output from the arbitration circuit 175 is appropriately output to the control signal line 3, the address signal line 4, and the input data line 5.

In FIG. 2, a refresh cycle measuring circuit 177 is arranged in the memory control circuit 107 as a feature of the present invention. This measuring circuit 177
Is a refresh circuit unit 108 of the DRAM core unit 2.
The internal clock (CLKREF) 109 for determining the self-refresh cycle and the refresh activation signal (REFen) 110 are input, and the master clock (CLK) 111 such as a system clock is input to refresh the DRAM core unit 2. Measure the period. Details of a circuit example of the measuring circuit 177 will be described later.

Information on the refresh cycle of the DRAM core section 2 measured by the refresh cycle measuring circuit 177 is input to the refresh command generating circuit 171 as a performance rank determination signal 12 of the DRAM core section 2. The command generation circuit 171 automatically adjusts the generation cycle of the refresh command based on the performance rank determination signal 12 output from the refresh cycle measurement circuit 177.

Therefore, the refresh cycle measuring circuit 1
77 and the refresh command generation circuit 171
As a function of the logic circuit unit 1 of the DRAM core unit 2 in accordance with the self-refresh cycle of the DRAM core unit 2, a changing unit 180 for changing the order and timing of refresh control is configured.

The refresh command generating circuit 1
71, the refresh command generation cycle can be automatically changed based on the performance rank determination signal 12.
As shown in, the command generation circuit 171a for the normal cycle
And a command generating circuit 171b for a shortened cycle which is shorter than the normal cycle, and a selector 178 which selects outputs from both circuits.

FIG. 4 shows the memory control circuit 10.
7 shows the internal structure of the refresh cycle measuring circuit 177 in FIG. In the figure, reference numeral 121 denotes a measurement circuit activation signal generation circuit, which is the refresh activation signal (REFe).
n) 110 and internal clock for self refresh (CL
KREF) 109 outputs the measurement circuit activation signal 124 in the H or L level state for a predetermined fixed time. Reference numeral 122 denotes a counter for counting the number of clocks, which receives the self-refreshing internal clock 109 output from the refresh circuit unit 108, and is a master during the period (cycle) from the rising of the internal clock 109 to the next rising. The number of clocks (CLK) 111 is counted. Reference numeral 123 denotes a count number determination circuit that determines the count number of the counter 122, and a specific one determination signal close to the count number of the counter 122 is activated among a plurality of determination signals.

Next, the operation of the system LSI of this embodiment will be described. First, the logic circuit unit 1 issues a self-refresh command for automatically refreshing all memory cells within a specific time, and inputs this command to the DRAM core unit 2 via the control line 3. The DRAM core section 2 receives the self-refresh command and generates the self-refresh internal clock 109 to refresh a large number of memory cells provided at predetermined time intervals. This internal clock for self-refresh 1
The period of 09 is set (programmed) at the same time as the redundant fuse trimming for relieving the defective memory cell, based on the data retention characteristic of the memory cell obtained by the inspection of the DRAM core unit 2 in advance.

On the other hand, in the refresh cycle measuring circuit 177 in the memory control circuit 107 of the logic circuit 1, the measuring circuit activation signal generating circuit 121 is activated by the self-refresh command as a trigger, and the refresh activation signal ( The counter 122 is activated by the REFen) 110 for a predetermined fixed period.
In the activated counter 122, the self-refreshing internal clock 109 is input from the DRAM core unit 2 and counts the number of master clocks (CLK) 111 input in the predetermined constant period, and the count number is judged by this count number. The circuit 123 determines the rank of the refresh cycle and transfers it to the logic circuit unit 1 as the refresh cycle determination signal 12.

FIG. 5 shows the refresh cycle measuring circuit 1
An example of the counter 122 of 77 is shown. FIG. 6 shows a timing chart of the operation of the measurement circuit 177.

In FIG. 5, reference numeral 124 is a measurement circuit activation signal, 111 is a master clock signal CLK such as a system clock, 109 is an internal self-refresh clock CLKREF, and 112 is a reset signal RST.
Reference numeral 141 denotes an AND circuit, which includes the refresh activation signal (REFen) 110 and the master clock (CL
K) 111 and internal clock for self refresh (C
LKREF) 109. Reference numeral 142 denotes a plurality of clock cycle measuring counters.

Hereinafter, this refresh cycle measuring circuit 17 will be described.
The operation of No. 7 will be described based on the timing chart of FIG. First, after the power is turned on, the reset signal (RST) 112
Occurs, which resets all counters 142. After that, the self refresh command signal 3 is issued in the test mode, and the refresh circuit 108 of the DRAM core 2 causes the refresh activation signal (REFe
n) 110 is generated, and this signal 110 is input to the main refresh cycle measuring circuit 177 of the logic circuit section 1.
Further, in the refresh circuit section 108 of the DRAM core section 2, the refresh activation signal (REFen) 110
Immediately after the occurrence of the
REF) 109 is generated and output to the logic circuit unit 1.

In the refresh cycle measuring circuit 177, the measuring circuit activating signal generating circuit 121 sets the measuring circuit activating signal 124 by the refresh activating signal (REFen) 110, and the AND circuit 141 sets the measuring circuit activating signal 124. , The self-refresh internal clock (CLKREF) 109 and the master clock (CLK) 111 are input, and the AND circuit 141
As can be seen from FIG. 6, the passing clock signal CLKCMP is provided between the first shot pulse and the second shot pulse of the self-refreshing internal clock (CLKREF) 109.
131 is generated, and the clock period measuring counter 142 is counted up. Then, in the measurement circuit activation signal generation circuit 121, the measurement circuit activation signal 124 is reset by the second shot pulse of the internal clock (CLKREF) 109 for self-refreshing, whereby the count-up is completed and the output count Number BO-
Hold Bn. The self-refresh cycle is determined by taking the logic of several bits from the upper digit of the count number BO-Bn and used as the performance rank determination signal 12.

In this embodiment, the refresh cycle measuring circuit 177 is provided in the logic circuit section 1, but the measuring circuit 177 is provided in the DRAM core section 2 side so that only the upper digits of the count number BO-Bn are provided. Of course may be returned to the logic circuit unit 1. Further, in order to reduce the number of counters 142 of the refresh cycle measuring circuit 177, the master clock (CLK) may be divided and a clock whose frequency is delayed may be input to the AND circuit 141.

FIG. 7 shows a refresh cycle measuring circuit 177.
7 shows another exemplary configuration of the period measuring unit of FIG. FIG. 8 shows a timing chart of the operation of the measuring circuit 177. In this configuration example, the input signal is the same as that in FIG.

In FIG. 7, 161 is the AND of FIG.
It is a NAND circuit that replaces the circuit 141. A charge circuit 162 has a capacitor 162a that is charged based on the passing clock signal (CLKCMP) output from the NAND circuit 161. 181 to 18n are RS inside
A plurality of level determination circuits having flip-flop circuits for determining the charge level of the capacitor 162a of the charge circuit 162. The determination levels (threshold voltage of the RS flip-flop circuit) of the level determination circuits 181 to 18n are different, and the level determination circuit 181 is set to the highest and the level determination circuit 18n is set to the lowest.
The operation of the refresh cycle measuring circuit 177 of FIG. 7 will be described below.

First, after the power is turned on, a reset signal (RS
T) 112 is generated, which causes the charge circuit 162,
The RS flip-flop circuits in the level determination circuits 181 to 18n are reset, and all the outputs Am (0 <= m <= n) of the RS flip-flop circuits are set to the L level.

After that, the refresh entry is performed as described above, and the refresh activation signal (REFen) 110 is generated in the refresh circuit section 108 of the DRAM core section 2.
And refresh internal clock (CLKREF) 10
9 is generated. Then, the refresh circuit activation signal (REFen) 110 is used to activate the measurement circuit activation signal 124.
Set the internal clock for refresh (CLKRE
F) 109 and master clock (CLK) 111 are input to the NAND circuit 161.
The circuit 161 uses the internal clock for refresh (CLKRE
F) A passing clock (CLKCMP) 151 is generated between the pulses of the first shot and the second shot of 109 to charge the capacitor 162a of the charge circuit 162. As the charge level of the capacitor 162a rises, the outputs AO to An of the level decision circuits 181 to 18n sequentially become the H level from the lower decision level side. The measurement circuit activation signal 124 is reset by the pulse of the second shot of the internal clock for refresh (CLKREF) 109, the charge in the charge circuit 162 is stopped, and the level determination circuit 18
The state of the outputs AO to An of 1 to 18n at the H or L level is held. Therefore, the passing clock (CLKCMP) 15
1 by the PMOSFET 162 of the charge circuit 162
Considering the time when b is turned on (target time for changing the function in the logic circuit unit 1) and the charge capacity value, the cycle determination can be performed by the combination of the outputs AO to An of the level determination circuits 81 to 18n.

The refresh cycle measuring circuit 177 shown in FIG. 7 is provided on the DRAM core section 2 side, and the outputs A0-An of the level judging circuits 181-18n are connected to the logic circuit section 1.
Of course, it may be configured to be returned to the.

As described above, according to the present embodiment, the circuit architecture, function, operation timing, etc. in the logic circuit section 1 are changed according to the characteristics of the DRAM core section 2 such as the refresh cycle. Since the read / write access from the logic circuit unit 1 to the DRAM core unit 2 and the refresh operation in the DRAM core unit 2 can be achieved at the same time, the yield of the system LSI can be increased. In addition, even the same DRAM core unit 2 can support various processes.
Very useful as an IP.

(Second Embodiment) Next, the second embodiment of the present invention will be described.
The embodiment will be described with reference to FIG. In the first embodiment, the refresh internal clock (CLKREF) 109 is output to the logic circuit unit 1 as the internal control signal of the DRAM core unit 2. However, in the present embodiment, DR
Information based on the function and characteristics of the AM core unit 2 is stored in the DRAM core unit 2 side, and such information is output to the logic circuit unit 1.

In the semiconductor device of the present embodiment shown in FIG. 9, reference numeral 208 denotes an information setting circuit (information output means) provided in the DRAM core section 2, which is a data holding characteristic of a memory cell or a data access time. Ranks relating to functions and characteristics of the memory cell array such as are set in advance, and the rank signal is output to the logic circuit unit 1 as the performance rank determination signal 12. The same components as those in FIG. 1 are designated by the same reference numerals and the description thereof will be omitted.

In the present embodiment, the logic circuit section 1 is
Of the internal configuration shown in FIG. 2, the refresh cycle measuring circuit 177 is omitted, and the performance rank determination signal 12 output from the information setting circuit 208 is the same as the read / write command timing circuit 172 of FIG.
It is input to the precharge command timing circuit 173 and the data input / latch circuit 174. These circuits 1
72 to 174 change the order or timing of access control to the DRAM core unit 2 as a function of the logic circuit unit 1 according to the performance rank determination signal 12, and the DRAM as operation timing of the logic circuit unit 1.
The command to be output to the core unit 2, the read / write address, the setup timing of write data, and the D
The timing of fetching the data read from the RAM core unit 2 is changed, and constitutes a changing unit 190.

Next, the internal structure of the information setting circuit 208 will be described with reference to FIG. In FIG. 7A, 220 is an inverter that receives the reset signal (RST) 112, and 221 to 22n are n-bit setting circuits, which have the same configuration. The internal configuration will be described by taking the setting circuit 221 of the first bit as an example. This setting circuit 221
Has a PMOSFET 221a that receives an inverted reset signal from the inverter 220, and a fuse element 221b made of a wiring material of metal and polycide or polysilicon. The PMOSFET 221a has one end connected to the power supply VCC and the other end connected to one end of the fuse element 221b. The other end of the fuse element 221b is grounded. The PMOSFET 22
The connection point between 1a and the fuse element 221b serves as an output C1 and also passes through another inverter 221c to another PM.
It is connected to the gate of the OSFET 221d. This PMO
One end of the SFET 221d is connected to the power supply VCC, and the other end is connected to the output C1.

Next, the operation of the semiconductor device of this embodiment will be described. In advance, PCM measurement after wafer diffusion and professional
Process information and circuit information, for example, data holding characteristics of memory cells, operating frequencies, ranks of data access times, etc., by the inspection, the n-bit setting circuits 221 to
In order to obtain a combination of outputs C1 to Cn of 22n, a setting circuit for a predetermined bit to be disconnected (for example, 22n) at the same time as the redundant trimming for repairing a defective memory cell.
As shown in FIG. 11 in which the fuse element 221b of 1) is surrounded by a solid line, a predetermined area is laser blown to cut the fuse element 221b, thereby programming the process information and the like. In addition, it is not limited to laser cutting,
Electric fusing may be used.

Then, in such a state, after the power is turned on, the information setting circuit 208 of the DRAM core section 2 outputs the data holding characteristics of the memory cells to the logic circuit section 1. In the following, as shown in FIG. 10B, the fuse element 222 is provided only in the second bit setting circuit 222.
A case where b is cut will be described. That is, as shown in FIG. 12, after the power is turned on, an H level reset signal (RST) 1
12 is generated. Thereby, each setting circuit 221-2
Turn on PMOSFETs 221a to 22na in 2n
Then, the initial setting is performed. In this initial setting,
In the setting circuit 222 for the second bit, the fuse element 22
Since b is disconnected, O of PMOSFET 222a
The output C2 is charged by N to raise the potential, and this potential level is latched by the latch circuit composed of the inverter 222c and the PMOSFET 222d, and the output C2 becomes the H level. On the other hand, the other setting circuits 221, 223 to 22
In n, since the fuse elements 221a ... Are not blown, the potentials of the outputs C1 and C3 to Cn do not rise, and when the reset signal (RST) 112 shifts to the L level, it is completely set to the L level.
Become a level. Then, such n-bit information is output from the information setting circuit 208 to the logic circuit unit 1.

Therefore, in the present embodiment, the information based on the function and characteristics of the DRAM core section 2 is set and stored in the information setting circuit 208 and is output to the logic circuit section 1. The circuit architecture in the logic circuit unit 1 according to the functions and characteristics of the DRAM core unit 2,
The function and the like can be changed, the yield can be increased as a system LSI, and it is very useful as an IP.

(Modification of Information Setting Circuit) FIG. 13A
Shows a modification of the specific configuration of the information setting circuit 208 shown in FIG. Instead of using the fuse element in FIG. 10A, an anti-fuse element is used in the present embodiment.

That is, in FIG. 13A, the n setting circuits 241 to 24n have the same configuration. The internal configuration of the first setting circuit 241 will be described below.
Is a PMOSFET 24 whose one end is connected to the power supply VCC
1a and an anti-fuse element 241b arranged between the other end of the PMOSFET 241a and the ground. A reset signal (RST) 112 is input to the gate of the PMOSFET 241a via an inverter 234. Further, the antifuse element 241b has an AND
The circuit 261 is connected. The AND circuit 261 receives the test address 251, and when the address is its own address, level-shifts the output signal to the high voltage HV, and outputs the high voltage output signal to the anti-fuse element 241.
output to b. The antifuse element 241b is shown in FIG.
As shown in FIG. 3, a pair of electrodes is formed such that a very thin insulating film x such as a gate oxide film or a capacitive insulating film of a DRAM is arranged between two electrodes y, and a high voltage from the AND circuit 261. When receiving a voltage output signal, this output signal
When applied between two electrodes y, y, the ultrathin insulating film x breaks and becomes conductive. Further, the setting circuit 241 has
The PMOSFET 241a and the antifuse element 24
It has an inverter 241c arranged between the connection point with 1b and the output terminal C1, and another PMOSFET 241d having one end connected to the power supply VCC and the other end connected to the input side of the inverter 241c. This PMOSF
The output of the inverter 241c is input to the gate of the ET 241d.

Like the first setting circuit 241, the output signals of the AND circuits 262 to 26n are input to the other setting circuits 242 to 24n. Reset signal (RST) 1
The inverter 234 that receives 12 has the setting circuits 241 to
24n is common.

Next, the operation of the information setting circuit of this modification will be described. In this modification, the rank signals such as the data retention characteristics of the memory cells are set to the n-bit setting circuits 241 to 24.
In order to obtain a combination of n outputs C1 to Cn, the antifuse element 242b of the setting circuit (for example, 242) of the predetermined bit to be turned on is set to the corresponding test address 25.
2 and the AND circuit 262 with the level shift function breaks the circuit and makes it conductive. Hereinafter, a case where only the anti-fuse element 242b of the second setting circuit 242 is turned on will be exemplified.

In the above state, after the power is turned on, FIG.
As shown in, the H-level reset signal (RST) 11
2 occurs, the PMOS of each setting circuit 241 to 24n
The FETs 241a to 24na are turned on, and information is initialized. In this initial setting, in the setting circuits 241, ..., 24n other than the second bit, since the anti-fuse elements 241b and the like are non-conductive, the potential on the input side of the inverter 241c and the like rises to the H level, and this H The level is inverter 241c and PMOSFET 241d.
It is latched by a latch circuit including Output end C
The potentials of 1, ..., Cn and the like are inverted by the inverter 241c and the like and become L level.

On the other hand, in the setting circuit 242 for the second bit, since the anti-fuse element 242b and the like are conducting, the potential on the input side of the inverter 242c does not rise, and the reset signal (RST) 112 goes low. It will be completely at the L level with the transition. This L level is the inverter 24
Inverted at 2c, the potential of the output terminal C2 becomes H level.

In this way, the n-bit setting circuit 24
The combination of the outputs C1 to Cn of 1 to 24n is output to the logic circuit unit 1.

(Third Embodiment) Next, a third embodiment of the present invention will be described. The semiconductor device of the present embodiment is provided with a self-inspection circuit in the DRAM core section 2 and outputs the result of the self-inspection to the logic circuit section 1.

That is, in FIG. 16, the DRAM core unit 2
The self-inspection circuit 308 therein self-inspects the memory cell array of the DRAM core unit 2 and outputs the inspection result to the logic circuit unit 1 as the performance rank determination signal 12. The internal structure of the self-inspection circuit 308 is shown in FIG.

In FIG. 17, 321 is a self-check enable signal generation circuit, 322 is a control signal generator, and 3 is a control signal generator.
23 is an address generator, 324 is a data generator, 325 is a data comparator, and 326 is an inspection result register.

When the self-check enable signal generation circuit 321 receives the self-check signal (ST) 311 and generates the self-check enable signal, the control signal generator 322 is
A plurality of access patterns for the DRAM core unit 2 are generated, and a control command signal corresponding to each access pattern is generated. Further, according to the generation of the plurality of access patterns, the address generator 323 generates the row address and the column address of the data to be input to the DRAM core unit 2 for each access pattern, and the data generator 324 generates the access pattern for each access pattern. Then, a pattern of inspection data to be input to the DRAM core unit 2 is generated. These control command signals, addresses, and inspection data are input to the DRAM core unit 2 and DR
The AM core unit 2 outputs data according to these.

The data comparator 325 stores the DR
The data for each access pattern output from the AM core unit 2, the result (exclusive comparison result) TQCMP of the exclusive OR of these output data, and the inspection data generated by the data generator 324 are Input, these are logically processed by the data comparator 325,
The determination of PASS and FAIL is performed for each access pattern. These determination results FLG are stored in the inspection result register 326 in the order of access patterns. The determination result FLG stored in the register 326 is transferred to the logic circuit unit 1 as the performance rank determination signal 12.

Therefore, in this embodiment, the inspection result of the inside of the DRAM core unit 2 is transferred to the logic circuit unit 1 as a performance rank determination signal, and the circuit architecture, function, and operation timing in the logic circuit unit 1 are transferred. By changing the above, the read / write access from the logic circuit section 1 to the DRAM core section 2 and the refresh operation in the DRAM core section 2 can be achieved at the same time, as in the first and second embodiments. System LSI
As a result, the yield can be increased.

Further, the data latch timing in the data input / latch circuit 174 in the logic circuit section 1 and the internal operation timing in the logic circuit section 1 should be changed with respect to the delay in the data access time from the DRAM core section 2. As a result, it is possible to suppress a decrease in yield due to defective memory access. In addition, DRA of control signals, addresses, and input data transferred from the logic circuit unit 1 to the DRAM core unit 2
Even when the margin such as the setup time in the M core unit 2 is insufficient, the transfer timing in the logic circuit unit 1 is changed to suppress the yield decrease due to the memory access failure to the DRAM core unit 2 as well. can do.

In the above description, the semiconductor device including the DRAM core section 2 and the logic circuit section 1 has been described.
It goes without saying that the semiconductor device may include an analog circuit section in addition to the logic circuit section 1. Also, the case where the semiconductor memory circuit is the DRAM core unit 2 has been described, but the core unit of the static random access memory (SRAM
Needless to say, it may be the core part).

[0075]

As described above, according to the present invention,
In a semiconductor device as a system LSI composed of a semiconductor memory circuit unit and a logic circuit unit that realizes a system function, the function or operation timing of the logic circuit unit is changed according to the function or characteristics of the semiconductor memory circuit unit. It is possible to obtain a desired system LSI in a short time and suppress a decrease in the yield of the system LSI. Moreover, a wide variety of system requirements can be realized with the same semiconductor memory circuit unit. Further, the same semiconductor memory circuit unit can be used as a common IP for processes having different specifications. In addition, it becomes possible to manufacture products with different specifications on the same wafer, which can be expected to improve manufacturing efficiency.

[Brief description of drawings]

FIG. 1 is a block configuration diagram showing a semiconductor device according to a first embodiment of the present invention.

FIG. 2 is a diagram showing a specific internal configuration of a logic circuit unit of the semiconductor device.

FIG. 3 is a diagram showing another configuration example of the same logic circuit unit.

4 is a diagram showing an internal configuration of a refresh cycle measuring circuit provided in the logic circuit unit of FIG.

FIG. 5 is a diagram showing a specific configuration of the refresh cycle measurement circuit.

FIG. 6 is an operation explanatory diagram of the refresh cycle measurement circuit.

FIG. 7 is a diagram showing another specific configuration of the refresh cycle measuring circuit.

FIG. 8 is an operation explanatory diagram of the refresh cycle measurement circuit.

FIG. 9 is a block configuration diagram showing a semiconductor device according to a second embodiment of the present invention.

10A is a diagram showing a specific configuration of an information setting circuit provided in a DRAM core portion of the same semiconductor device, and FIG. 10B is a diagram showing one setting example of the information setting circuit.

FIG. 11 is a diagram showing an arrangement example of fuse elements included in the information setting circuit.

FIG. 12 is an operation explanatory diagram of the information setting circuit.

13A is a diagram showing another specific configuration of the information setting circuit, and FIG. 13B is a diagram showing one setting example of the information setting circuit.

FIG. 14 is a diagram showing a configuration of an anti-fuse element included in the information setting circuit.

FIG. 15 is an operation explanatory diagram of the information setting circuit.

FIG. 16 is a block configuration diagram showing a semiconductor device according to a third embodiment of the present invention.

FIG. 17 is a diagram showing a specific internal configuration of a self-inspection circuit provided in a DRAM core section of the same semiconductor device.

FIG. 18 is a block diagram of a conventional system LSI.

[Explanation of symbols]

1 Logic Circuit Section 2 DRAM Core Section (Semiconductor Memory Circuit Section) 107 Memory Control Circuit 108 Refresh Circuit Section 109 Clock (CLKREF) (Internal Control Signal, Internal Refresh Control Signal) Determining Refresh Cycle 111 Master Clock (CLK) 162 Charge Circuit 171 Refresh command generation circuit 172 Read / write command timing circuit 173 Command timing circuit 177 Refresh cycle measurement circuits 180, 190 Change means 181 Level determination circuit 208 Information setting circuits 221-22n Setting circuits 221b-22nb Fuse elements 241-24n Setting circuit 241b to 24nb Anti-fuse element 308 Self-test circuit 322 Control signal generator 323 Address generator 324 Data generator 3 25 Data comparator 326 Inspection result register

─────────────────────────────────────────────────── ─── Continuation of front page (51) Int.Cl. ⁷ Identification code FI theme code (reference) G11C 11/34 363M F term (reference) 5L106 AA01 AA02 CC04 CC13 DD25 GG07 5M024 AA74 AA75 BB17 BB30 DD20 DD60 EE05 EE09 EE22 EE24 EE27 EE30 GG17 GG20 HH10 KK35 MM10 PP01 PP02 PP03 PP07 PP10

Claims (15)

[Claims] 1. A semiconductor device having a semiconductor memory circuit section having a memory cell array and a logic circuit section for realizing a system function, wherein the logic circuit section is provided with an internal control signal of the semiconductor memory circuit section. A semiconductor device, further comprising: a changing unit that changes a function or an operation timing of its own logic circuit unit according to the internal control signal. 2. The semiconductor device according to claim 1, wherein the semiconductor memory circuit unit is a dynamic random access memory, and the internal control signal is an internal refresh control signal. 3. The internal refresh control signal is a clock that determines a refresh cycle in a self-refresh mode, and the changing means of the logic circuit section measures the cycle of the clock and outputs the self refresh control signal according to the measurement result. 3. The semiconductor device according to claim 2, wherein the function or operation timing of the logic circuit unit is changed. 4. The changing means of the logic circuit section inputs a clock for determining a refresh cycle of the self-refresh mode and a master clock for operating the logic circuit section, and the semiconductor memory circuit is based on the both clocks. 4. The semiconductor device according to claim 3, wherein the refresh cycle of the unit is measured. 5. The semiconductor device according to claim 3, wherein the function of the logic circuit unit changed by the changing unit is an order or timing of refresh control to the semiconductor memory circuit unit. 6. A semiconductor device having a semiconductor memory circuit section having a memory cell array and a logic circuit section for realizing a system function, wherein the semiconductor memory circuit section provides information based on the function and characteristics of the memory cell array. Information output means for outputting is provided, and the logic circuit section is provided with changing means for receiving the information from the information output means and changing the function or operation timing of its own logic circuit section in accordance with this information. A semiconductor device characterized by: 7. The information output means of the semiconductor memory circuit section has a plurality of fuse elements composed of a wiring material of metal and polycide or polysilicon, and one of the plurality of fuse elements is laser or electrical. 7. The semiconductor device according to claim 6, wherein information based on a function or a characteristic of the memory cell array is set by cutting the memory cell into the semiconductor device. 8. The information output means of the semiconductor memory circuit section has a plurality of antifuse elements each having a thin insulating film disposed between two electrodes, and any one of the plurality of antifuse elements is provided. 7. The semiconductor device according to claim 6, wherein information based on a function or a characteristic of the memory cell array is set by electrically connecting by applying an electric field. 9. A semiconductor device having a semiconductor memory circuit section having a memory cell array and a logic circuit section for realizing a system function, wherein the semiconductor memory circuit section has a self-test circuit for self-testing the memory cell array. The logic circuit unit is provided with a changing unit that receives a self-inspection result of the self-inspection circuit and changes a function or an operation timing of the self-logic circuit unit according to the self-inspection result. Semiconductor device. 10. The semiconductor according to claim 1, wherein the function of the logic circuit unit changed by the changing unit is an order or timing of access control to the semiconductor memory circuit unit. apparatus. 11. The operation timing of the logic circuit section changed by the changing means is a setup timing of a control signal, an address and write data output to the semiconductor memory circuit section. The semiconductor device described. 12. The operation timing of the logic circuit unit changed by the changing unit is a fetch timing of data output from the semiconductor memory circuit unit. Semiconductor device. 13. The semiconductor device according to claim 1, further comprising an analog circuit section together with the semiconductor memory circuit section and the logic circuit section. 14. The semiconductor device according to claim 1, wherein the semiconductor memory circuit unit is a dynamic random access memory. 15. The semiconductor device according to claim 1, wherein the semiconductor memory circuit unit is a static random access memory.