JP2003110465A - Hpsk diffusion modulation circuit and mobile communication terminal - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce a circuit scale while high-speed data process is realized with small power consumption, and carry out many kinds of tests for the circuit easily. SOLUTION: A 1/2 pixel skipping circuit and a 0/1 repeating circuit are provided in a scrambling code generator, and superfluous multiplication circuits can be eliminated to realize small size of circuit scale, high processing speed, and low power consumption. By turning off (multiplication is through) a channelization code, by turning off (complex multiplication is through) scrambling code or by turning off both sides, a calculation result necessary for many kinds of tests can be generated outside the circuit, and verification for many kinds of tests can be carried out easily.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a transmission system of a spread spectrum communication system, and more particularly to an HPSK (Hybrid Phase Shift Keyin) used in a third generation mobile terminal device or the like.
g) A spreading modulation circuit and a mobile communication terminal device using this spreading modulation circuit.

[0002]

2. Description of the Related Art Conventionally, a spread spectrum communication system adopts a modulation system in which a wide band signal is used as a carrier and is converted into a signal having a much wider band than the original signal, so that communication is protected from an interference wave and an interference wave, Even during communication, even the fact of communication can be kept secret due to noise. Focusing on this characteristic, this spread spectrum technique is applied to CDMA (Code Division Multiple Acces
It is used for mobile terminal devices such as s) type mobile phones, and in the third generation mobile terminal devices, spread modulation of transmission data is performed using an HPSK spread modulation circuit, which widens the signal bandwidth. The obtained data is transmitted from the antenna.

FIG. 5 is a circuit diagram showing a configuration example of a conventional HPSK spread modulation circuit. The HPSK spread modulation circuit includes a channel spread data code (Cd) and a control code (C
c) Channelization code (Channeli)
zation code) generator 13, data gain factor (βd) for determining the amount of amplitude, and control gain factor (β
output from the inter-channel power control circuit 14 for generating c), the scrambling code generator 15 for generating the in-phase component (C1) and the quadrature component (C2) code of complex spreading, and the scrambling code generator 15. ½ decimation circuit 16 for decimating the quadrature component (C2), a Walsh code generator 17 for generating a code at the chip rate, and a dedicated data channel (Dedicated Phisical Data Channel).
(DPDCH)) 11 output value (Dd) and a channelization code generator 13 output data code (Cd) are multiplied by a multiplier 18a and channel power control circuit 14 output gain factor (β).
a multiplier 18 for multiplying d) by the multiplication result of the multiplier 18a
b, a multiplier 18c for multiplying the multiplication result of the multiplier 18b by the code W0 of the Walsh code generator 17, and a multiplier 18
A subtracter 19a for subtracting the multiplication result of the multiplier 18i described later from the multiplication result of c, the subtraction result of the subtractor 19a and the in-phase component (C1) of the complex spread output from the scrambling code generator 15 are output. The multiplier 18d for calculating the value I, the dedicated control channel (Dedicated Phisical Cont
multiplier 18e for multiplying the output value (Dc) of the orol Channel (DPCCH) 12 by the data code (Cc) which is the output of the channelization code generator 13, and the gain factor for data which is the output of the inter-channel power control circuit 14. A multiplier 18f for multiplying (βc) by the multiplication result of the multiplier 18e, a multiplication result of the multiplier 18f and a multiplication result of a multiplier 18g, a multiplier 18g for multiplying the code W0 output from the Walsh code generator 17, and a description given later. Multiplier 18
The adder 19b for adding the multiplication result of j, the addition result of the adder 19b and the in-phase component (C1) of the complex spread output from the scrambling code generator 15 are multiplied to obtain the output value Q.
A multiplier 18 for multiplying the multiplication result of the multiplier 18h and the multiplication result of the multiplier 18b by the multiplication result of the multiplier 18k described later.
The quadrature component (C
2) and a code W1 output from the Walsh code generator 17, and a multiplier 18k.

Next, the operation of the HPSK spread modulation circuit will be described. First, the output value I is calculated as follows. The output value (Dd) of the DPDCH 11 and the data code (Cd) of the channelization code generator 13 are multiplied by the multiplier 18a, and the multiplication result (Dd × Cd) and the data gain factor (βd of the inter-channel power control circuit 14). ) Is multiplied by the multiplier 18b (Dd × C
d × βd) is calculated.

At the same time, the output value (Dc) of the DPCCH 12
And the control code (Cc) of the channelization code generator 13 are multiplied by the multiplier 18e, and the multiplication result (Dc
× Cc) and the control gain factor (βc) of the inter-channel power control circuit 14 are multiplied by the multiplier 18f to obtain a multiplication result (Dc × Cc × βc). These calculated results (Dd × Cd × βd) and (Dc × Cc × βc) are added to the in-phase component of the complex multiplication result of the complex multiplication result, which will be described later, and the in-phase component (C1 of the scrambling code generator 16 is added. ) Is multiplied by the multiplier 18d to obtain the output value I.

The complex multiplication described above is performed by using the {1-1} code (W0) of the Walsh code generator 17 and the DPDCH.
The multiplication result (Dd × Cd × βd) of the 11th system is multiplied by the multiplier 18c.
From the multiplication result (Dd × Cd × βd × W0) multiplied by
Quadrature component (C2) of scrambling code generator 16
1 and 2 are thinned by the 1/2 thinning circuit 16,
/ 2 thinning result (C2 ') and Walsh code generator 1
The {1-1} code (W1) of 7 is multiplied by the multiplier 18k, and the multiplication result (C2 ′ × W1) and the above DPCCH1
The multiplication result (Dc × Cc × βc × C2 ′ × W0) obtained by multiplying the multiplication result (Dc × Cc × βc) of the second system by the multiplier 18i
From the subtracter 19a. Therefore, the output value I is I = C1 (βd × Cd × Dd × W0−
It can be expressed by βc × Cc × Dc × C2 ′ × W1).

The output value Q is calculated as described below. The output value (Dd) of the DPDCH 11 and the data code (Cd) of the channelization code generator 13 are multiplied by the multiplier 18a, and the multiplication result (Dd × Cd) and the data gain factor (βd of the inter-channel power control circuit 14). ) Is multiplied by the multiplier 18b (Dd × C
d × βd) is calculated.

At the same time, the output value (Dc) of the DPCCH 12
And the control code (Cc) of the channelization code generator 13 are multiplied by the multiplier 18e, and the multiplication result (Dc
× Cc) and the control gain factor (βc) of the inter-channel power control circuit 14 are multiplied by the multiplier 18f to obtain a multiplication result (Dc × Cc × βc). These calculation results (Dd × Cd × βd) and (Dc × Cc × βc) are multiplied by the in-phase component (C1) of the scrambling code generator 16 to the in-phase component of the complex multiplication result described later. The output value Q is obtained by multiplying by 18h.

The complex multiplication described above is performed by using the {1-1} code (W0) of the Walsh code generator 17 and the DPCCH.
The multiplication result (Dc × Cc × βc) of the 12th system is multiplied by the multiplier 18g.
The multiplication result (Dc × Cc × βc × W0) and the orthogonal component (C2) of the scrambling code generator 16 are subjected to 1/2 thinning by the 1/2 thinning circuit 16 and the 1/2 thinning result (C2 ′) And the {1-1} code (W1) of the Walsh code generator 17 are multiplied by the multiplier 18k, and the multiplication result (C2 ′ × W1) and the multiplication result (Dd × Cd × βd) of the DPDCH11 system are multiplied. It is configured by the result of adding the multiplication result (Dd × Cd × βd × C2 ′ × W0) multiplied by the multiplier 18j by the adder 19b. Therefore, the output value Q is Q = C1 (βd × Cd × Dd × C2 ′ × W1
+ Βc × Cc × Dc × W0).

[0010]

However, if the HPSK spread modulation having the above-mentioned structure is embodied in an actual circuit, the scrambling code generator 15 itself has a degree of freedom, but the 1/2 decimation circuit 16 and the Walsh code generation are provided. Bowl 1
Since circuits such as 7 are provided as independent blocks, a large number of multipliers 18 for performing the complex multiplication described above are required.
Therefore, the HPSK spread modulation circuit itself becomes complicated and H
There is a problem that the circuit scale of the PSK spread modulation circuit increases, and since there are many multipliers, data processing becomes slow and power consumption also increases.

Also, the scrambling code generator 15
From the circuit, output the data and multiplication result required for the test, for example, the complex multiplication result of the input data and the scrambling code, the multiplication result of the input data and the channelization code, and the multiplication result of the input data and the gain factor (β). Therefore, there is a problem that various tests such as complex operation, diffusion, and amplitude confirmation cannot be easily performed.

The present invention has been made in view of the above circumstances, and a first object of the present invention is to provide an HPSK spread modulation circuit capable of reducing the circuit scale, high-speed data processing, and low power consumption. The second purpose thereof is to provide an HPSK spread modulation circuit capable of easily performing various tests of the circuit, and the third object thereof is to provide a mobile communication terminal device of small size, light weight and low power consumption. It is to be.

[0013]

The HPSK spreading modulation circuit of the present invention uses input data as a channelization code for generating a channel spreading code, a gain factor for determining an amplitude amount, and a scrambling code for complex spreading. An HPSK spread modulation circuit for calculating output I and output Q by performing HPSK spread modulation of the input data by calculation, and a scrambling code generation circuit for generating codes of complex spread quadrature component and in-phase component, A decimating circuit for decimating the quadrature component generated by the scrambling code generating circuit, a repeating circuit for repeatedly outputting 0/1 for each chip rate, and a scrambling code generating circuit A first exclusive OR of the in-phase component to be output and 0 or 1 output from the repeating circuit Exclusive OR circuit and said second take 1/2 decimated quadrature component output from the repeat circuit an exclusive OR of the output of said first exclusive OR circuit
And a new scrambling code generation circuit having an exclusive OR circuit in one block circuit, and multiplying the gain factor by a multiplication result of the input data and the channelization code, A complex multiplication is performed between the multiplication result, the in-phase component, which is the new scrambling code output from the new scrambling code generation circuit, and the new quadrature component, which is the output from the second exclusive OR circuit. Thus, the output I and the output Q are calculated.

The HPSK spread modulation circuit of the present invention is provided with an output stopping means for stopping the output of the channelization code, and by the output stopping means, the output of the channelization code is stopped, and the input data and the channel are stopped. Multiplying the input data and the gain factor by passing through the multiplication of the activation code,
A complex multiplication of the multiplication result and the scrambling code is performed, and a complex multiplication result of the input data and the scrambling code is output.

The HPSK spread modulation circuit of the present invention is provided with an output stopping means for stopping the output of the new scrambling code, and by this output stopping means, the output of the new scrambling code is stopped. The input data is multiplied by the channelization code by passing through the multiplication using a code, and the multiplication result is multiplied by the gain factor to output the multiplication result of the input data and the channelization code. It is characterized by doing.

The HPSK spread modulation circuit of the present invention is provided with output stopping means for stopping the output of the channelization code and the new scrambling code, and the output stopping means causes the channelization code and the new scrambling code to be output. By stopping the output and passing through the multiplication of the input data and the channelization code, and passing through the multiplication using the scrambling code, the input data and the gain factor are multiplied, and the multiplication result is It is characterized by outputting.

According to the HPSK spread modulation circuit of the present invention,
In a circuit that configures HPSK spread modulation, a 1/2 decimation circuit that decimates 1/2 in a scrambling code that generates a code of a quadrature component and an in-phase component of complex spreading, and 0/1 is repeatedly output in chip rate units. By having a circuit for, the multiplication of the channelization code that generates the spreading code of the channel and the input data, the multiplication result and the gain factor (β) that determines the amplitude amount,
Complex multiplication of this multiplication result and the scrambling code can be configured, and an extra multiplication circuit can be eliminated. Further, by turning off either one or both of the channelization code and the scrambling code (through multiplication), it is possible to output the calculation results required for various tests to the outside of the circuit in each off mode.

The mobile communication terminal apparatus of the present invention spread-modulates the input data, and the HPSK spread-modulation circuit according to any one of claims 1 to 4, and spread-modulation output from the HPSK spread-modulation circuit. A band limiting filter circuit for limiting a band of data, and a digital-analog conversion circuit for converting data output from the band limiting filter circuit into an analog signal and transmitting the analog signal from an antenna are characterized by being provided.

[0019]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings.

[First Embodiment] FIG. 1 shows the HP of the present invention.
FIG. 3 is a circuit diagram showing a configuration of the SK spread modulation circuit according to the first embodiment. However, the same parts as those of the conventional example will be described with the same reference numerals. The HPSK spread modulation circuit of this example has a channel spread data code (Cd) and a control code (C).
c) Channelization code (Channeli)
zation code) generator 13, data gain factor (βd) for determining the amount of amplitude, and control gain factor (β
c) the inter-channel power control circuit 14, which generates the in-phase component Si and the quadrature component Sq of the complex diffusion, the scrambling code generator 25, the dedicated data channel (DP)
DCH)) 11 output value (Dd) and channelization code generator 13 output data code (Cd) are multiplied by a multiplier 18a and channel power control circuit 14
18b that multiplies the data gain factor (βd) that is the output of the multiplier 18 by the multiplication result of the multiplier 18a, and the dedicated control channel (DP).
CCH)) 12 output value (Dc) and channelization code generator 13 output data code (Cd)
18e for multiplying by the channel power control circuit 1
4 for multiplying the data gain factor (βd) which is the output of No. 4 by the multiplication result of the multiplier 18e, the output (Si) of the scrambling code generator 25 and the multiplier 18
The output (S) of the multiplier 181 and the scrambling code generator 25 for multiplying the multiplication result of b
q) and a multiplier 18 for multiplying the multiplication result of the multiplier 18f
2. Output of scrambling code generator 25 (Si)
And a multiplier 183 that multiplies the multiplication result of the multiplier 18f, a multiplier 184 that multiplies the output (Sq) of the scrambling code generator 25 and the multiplication result of the multiplier 18b, and a multiplier 1
Subtractor 19a for subtracting the multiplication result of multiplier 182 from the multiplication result of 81, multiplication result of multiplier 183 and multiplier 184
It is composed of an adder 19b for adding the multiplication results of.

FIG. 2 is a circuit diagram showing a detailed configuration example of the scrambling code generator 25 described above. The scrambling code generator 25 generates a complex spreading in-phase component (C
1) and a scrambling code generator 15 for generating a quadrature component (C2) code, a ½ decimating circuit 16 for decimating the quadrature component (C2) code by ½, and repeatedly outputting 0/1 for each chip rate. 0/1 repeating circuit 3
7 and the exclusive OR circuit 3 that takes the exclusive OR of the in-phase component (C1) of the complex diffusion and the output of the 0/1 repeating circuit 37.
0a and the output of the exclusive OR circuit 30a and the decimated quadrature component (C2) code are exclusive ORed and output the orthogonal component Sq. Is configured to have.

Next, the operation of this embodiment will be described.
The output value I is calculated as described below. DPDCH
The output value (Dd) of 11 and the data code (Cd) of the channelization code generator 13 are multiplied by the multiplier 18a, and the multiplication result (Dd × Cd) and the gain factor (βd for data of the inter-channel power control circuit 14). ) Is multiplied by the multiplier 18b to calculate a multiplication result (Dd × Cd × βd). At the same time, the output value (Dc) of the DPCCH 12 and the control code (C
c) is multiplied by the multiplier 18e, and the multiplication result (Dc × C
c) and the control gain factor (βc) of the inter-channel power control circuit 14 multiplied by the multiplier 18f (D)
c × Cc × βc) is calculated. These multiplication results (Dd
The output value I is calculated by performing the complex multiplication described later on (× Cd × βd) and (Dc × Cc × βc).

In the scrambling code generator 25 shown in FIG. 2, the scrambling code generator 1 is used.
The in-phase component (C1) of the complex diffusion generated from 5 is output as it is as the in-phase component Si. The orthogonal component (C2) of the complex spread generated by the scrambling code generator 15 is decimated by a ½ decimation circuit 16. The exclusive OR circuit 30a has the in-phase component (C1).
And the exclusive OR of 0 or 1 generated from the 0/1 repeating circuit 37. The exclusive OR circuit 30b is a quadrature thinned quadrature component (C) from the output of the exclusive OR circuit 30.
2) with the exclusive OR, and the result is the orthogonal component (S
output as q).

The above (Dd × Cd × βd) and (Dc ×
The complex multiplication of Cc × βc) is performed by the in-phase component (Si) of the scrambling code generator 25 and the multiplication result (Dd × C) of the DPDCH11 system output from the multiplier 18b.
d × βd) multiplied by the multiplier 181 (Dd ×
Cd × βd × Si), the orthogonal component (Sq) output from the scrambling code generator 25 and the DPCC
The multiplication result (Dc × Cc × βc) of the H12 system is multiplied by the multiplier 18
It is composed of the result of subtracting the multiplication result (Dc × Cc × βc × Sq) multiplied by 2 by the subtracter 19a. Therefore, the output value I is I = βd × Cd × Dd × Si−βc × Cc ×
It can be expressed by Dc × Sq.

The output value Q is calculated as described below. The output value (Dd) of the DPDCH 11 and the data code (Cd) of the channelization code generator 13 are multiplied by the multiplier 18a, and the multiplication result (Dd × Cd) and the data gain factor (βd of the inter-channel power control circuit 14). ) Is multiplied by the multiplier 18b (Dd × C
d × βd) is calculated. At the same time, the output value (Dc) of the DPCCH 12 and the channelization code generator 13
The control code (Cc) is multiplied by the multiplier 18e, and the multiplication result (Dc × Cc) and the channel power control circuit 14
The multiplication result (Dc × Cc × βc) obtained by multiplying the control gain factor (βc) by the multiplier 18f is calculated. These multiplication results (Dd × Cd × βd) and (Dc × Cc × β
The output value Q is calculated by performing the complex multiplication described later on c).

The above (Dd × Cd × βd) and (Dc × Cc
The complex multiplication of xβc) is performed by the in-phase component (Si) of the scrambling code generator 25 and the multiplication result (Dc × Cc ×) of the DPCCH 12 system output from the multiplier 18f.
βc) multiplied by the multiplier 183 (Dc × Cc)
Xβc × Si) and a scrambling code generator 25
Orthogonal component (Sq) output from the DPDCH 11
The multiplication result (Dd × Cd × βd) of the system is multiplied by the multiplier 184 and the multiplication result (Dd × Cd × βd × Sq) is added by the adder 19b. Therefore, the output value Q is Q = βd × Cd × Dd × Sq + βc × Cc × Dc
It can be expressed by xSi.

According to the present embodiment, the scrambling code generator 15 for generating the in-phase component code (C1) and the quadrature component code (C2) of the complex spread, and the 1/2 decimation circuit for performing the 1/2 decimation. 16 and 0 per chip rate
Repeating circuit 37 for repeatedly outputting
By constructing a new scrambling code generator 25 with the circuit of the block, the channel spreading code (C) of the channelization code generator 13 is multiplied by the input data, and the multiplication result and the channel power between which the amplitude amount is determined. Gain factor (β) output from the control circuit 14
Since it is possible to construct a multiplication of the multiplication result and a complex multiplication of the multiplication result and the scrambling code (S) of the scrambling code generator 25, the number of multipliers 18 can be reduced as compared with the conventional example, and the 1/2 decimation circuit Since the independent block circuit of the Walsh code generator can be omitted,
The circuit scale of the HPSK spread modulation circuit can be reduced and the power consumption can be reduced. Moreover,
Since the number of multipliers is reduced, the data processing of the circuit can be speeded up.

[Second Embodiment] FIG. 3 shows the HP of the present invention.
It is a circuit diagram showing the composition concerning a 2nd embodiment of a SK spread modulation circuit. However, the same parts as those of the first embodiment shown in FIG. 1 are designated by the same reference numerals, and the description thereof will be appropriately omitted. The HPSK spread modulation circuit of this example selects either the output of the multiplier 18b or the output value (Dd) of the DPDCH 11 to select the multipliers 181, 184 and the selector 4 described later.
0d, a selector 40a for outputting to 0d, a selector 40b for selecting one of the output of the multiplier 18f and the output value (Dc) of the DPCCH 12 and outputting it to the multipliers 182, 183 and the selector 40c, and an output of the subtractor 19a. Selector 4
Selector 40c for selecting any of the outputs of 0b and outputting to the outside, selector 40c for selecting and outputting to the outside of either the output of adder 19b or the output of selector 40a.
d is inserted. Further, means (not shown) for turning off the channelization code generator 13 is provided, and the code generation from the channelization code generator 13 can be stopped. These points are different from the first embodiment, and other configurations are the same.

Next, the characteristic part of this embodiment will be described. Turn off the channelization code generator 13 (OF
F) That is, the output I when passing through the multiplication of the multipliers 18a and 18e is calculated as follows. With the selector 40a,
The multiplication result (Dd × βd) obtained by multiplying the output value (Dd) of the DPDCH 11 and the data gain factor (βd) of the inter-channel power control circuit 14 by the multiplier 18b is selected. At the same time, the selector 40b selects the multiplication result (Dc × βc) obtained by multiplying the output value (Dc) of the DPCCH 12 and the control gain factor (βc) of the inter-channel power control circuit 14 by the multiplier 18f. These multiplication results (Dd
The output I is calculated by performing a complex multiplication described later on (× βd) and (Dc × βc).

The complex multiplication described above is performed by the in-phase component (Si) of the scrambling code generator 25 and the selector 40.
The multiplication result of DPDCH11 output from a (Dd × β
d) is multiplied by the multiplier 181 (Dd × βd ×
Si) from the quadrature component (Sq) of the scrambling code generator 25 and the DP output from the selector 40b.
It is composed of the result of subtraction by the subtracter 19a of the multiplication result (Dc × βc × Sq) obtained by multiplying the output value of the CCH 12 by the multiplier 181. That is, the output value I is I = βd × Dd × S
It can be expressed by i-βc × Dc × Sq.

The output Q when the channelization code generator 13 is turned off, that is, when the multiplication of the multipliers 18a and 18e is passed, is calculated as described below. Selector 4
At 0a, the output value (Dd) of the DPDCH 11 and the data gain factor (βd) of the inter-channel power control circuit 14
The multiplication result (Dd × βd) obtained by multiplying by the multiplier 18b is selected. The selector 40b selects the multiplication result (Dc × βc) obtained by multiplying the output value (Dc) of the DPCCH 12 and the control gain factor (βc) of the inter-channel power control circuit 14 by the multiplier 18f. These multiplication results (Dd
The output Q is calculated by performing a complex multiplication described later on (× βd) and (Dc × βc).

The complex multiplication described above is performed by the orthogonal component (Sq) of the scrambling code generator 25 and the selector 40.
The multiplication result of DPDCH11 output from a (Dd × β
d) multiplied by the multiplier 184 (Dd × βd ×
Sq), the in-phase component (Si) of the scrambling code generator 25, and the DPCC output from the multiplier 40b.
The multiplication result (Dc × βc) of H12 is multiplied by the multiplier 183, and the multiplication result (Dc × βc × Si) is added by the adder 19b. Therefore, the output value Q is Q =
It can be expressed by βd × Dd × Sq + βc × Dc × Si.

According to this embodiment, the output of the channelization code (C) is turned off, that is, the multipliers 18a and 18a.
By providing a means for letting e through, multiplication of the input data and the gain factor (β) output from the inter-channel power control circuit 14 that determines the amplitude amount, and complex multiplication of this multiplication result and the scrambling code (S) are performed. Therefore, the complex multiplication result of the input data and the scrambling code can be output to the outside of the circuit, and the test verification of the complex multiplication can be easily performed.

[Third Embodiment] Next, the HPSK of the present invention
The operation of the spread modulation circuit according to the third embodiment will be described. However, the configuration of the HPSK spread modulation circuit of this example is shown in FIG.
The configuration is the same as that of the second embodiment shown in FIG. The HPSK spread modulation circuit of this example is the scrambling code generator 25 shown in FIG.
There is provided a means (not shown) for turning off the switch to stop the coat output. That is, the multipliers 181, 182, 18
It is a configuration in which 3, 184 are passed through.

Next, the operation of this embodiment will be described.
The output I when the scrambling code generator 15 is turned off is the output value (Dd) of the DPDCH 11 and the channelization code generator 1 selected by the selector 40a.
The data code (Cd) of No. 3 is multiplied by the multiplier 18a, and the multiplication result (Dd × Cd) and the data gain factor (βd) of the inter-channel power control circuit 14 are multiplied.
The multiplication result (Dd × Cd × βd) is obtained. Therefore, the output value I can be expressed by I = βd × Cd × Dd.

The output Q when the scrambling code generator 15 is turned off is the DP selected by the selector 40d.
The output value (Dc) of the CCH 12 and the control code (Cc) of the channelization code generator 13 are multiplied by the multiplier 18e, and the multiplication result (Dc × Cc) and the control gain factor (βc) of the inter-channel power control circuit 14 are multiplied. ) Is multiplied by the multiplier 18f to obtain a multiplication result (Dc × Cc × βc). Therefore, the output value Q can be expressed by Q = βc × Cc × Dc.

According to this embodiment, by providing means for turning off the output of the scrambling code (S), multiplication of the input data by the channelization code (C),
This multiplication result and the gain factor (β) that determines the amount of amplitude
Therefore, the multiplication result of the channelization code and the input data can be output to the outside of the circuit, and the diffusion test can be easily verified.

[Fourth Embodiment] Next, the HPSK of the present invention
The operation of the spread modulation circuit according to the fourth embodiment will be described. However, the configuration of the HPSK spread modulation circuit of this example is shown in FIG.
The configuration is the same as that of the second embodiment shown in FIG. The HPSK spread modulation circuit of this example has means (not shown) for turning off the channelization code generator 13 and turning off the scrambling code generator 25. That is, the multiplier 18a,
18e, 181, 182, 183, 184 is a through structure.

Next, the operation of this embodiment will be described.
Output when the channelization code generator 13 is turned off and the scrambling code generator 15 is turned off
I is the multiplication result (Dd × βd) obtained by multiplying the output value (Dd) of the DPDCH 11 and the data gain factor (βd) of the inter-channel power control circuit 14 selected by the selector 40c by the multiplier 18b. Therefore, the output value I is
It can be expressed by I = βd × Dd.

The output Q when the channelization code generator 13 is turned off and the scrambling code generator 15 is turned off is the DP selected by the selector 40d.
The output value (Dc) of the CCH 12 and the control gain factor (βc) of the inter-channel power control circuit 14 are multiplied by the multiplier 18f.
The multiplication result (Dc × βc) is obtained. That is, the output value Q can be expressed by Q = βc × Dc.

According to this embodiment, by providing means for turning off the output of the channelization code (C) and means for turning off the output of the scrambling code (S),
You can configure multiplication of input data and gain factor (β),
Therefore, the multiplication result of the input data and the gain factor (β) can be output to the outside of the circuit, and the test verification of the amplitude confirmation can be easily performed.

FIG. 4 is a block diagram showing the configuration of an embodiment of the mobile communication terminal device of the present invention. The mobile communication terminal apparatus of the present example uses one of the HPSK spread modulation circuits shown in the above-described first to fourth embodiments as an HPS.
A K-spreading modulation circuit 51, a band-limiting filter circuit 52 for limiting the band of the spread modulation result by the HPSK spread-modulating circuit 51, and a D / A conversion circuit for converting the data output by the band-limiting filter circuit 52 into an analog signal It has a (DAC) 53 and an antenna 54 for transmitting a signal.

Next, the operation of this embodiment will be described.
The transmission data 100 to be transmitted by CDMA wireless communication is
The SK spread modulation circuit 51 performs spread modulation, and the multiplication result is passed through the band limiting filter circuit 52 to be data of constant amplitude. This constant amplitude data is converted into an analog signal by the D / A conversion circuit 53 and transmitted from the antenna 54.

According to this embodiment, since the circuit scale of the HPSK spread modulation circuit 51 is small, the mobile communication terminal device can be made compact and lightweight. Further, since the power consumption of the HPSK spread modulation circuit 51 is low, it is possible to extend the life of the battery or the like mounted therein and further lengthen the continuous standby time.

The present invention is not limited to the above-described embodiments, and can be implemented in various other modes in specific configurations, functions, actions, and effects without departing from the scope of the invention. For example, the HPSK spread modulation circuit of the present invention can be mounted not only on the mobile terminal device but also on any communication device, and similar effects can be obtained.

[0046]

As described in detail above, according to the present invention, a scrambling code generator for generating the in-phase component code (C1) and the quadrature component code (C2) of complex spreading, By constructing a new scrambling code generator by forming a 1/2 decimation circuit that performs decimation and a repetitive circuit that repeatedly outputs 0/1 for each chip rate as a new scrambling code generator, an extra multiplication circuit can be provided. Since it can be deleted, the circuit scale can be reduced, high-speed data processing can be performed, and low power consumption can be achieved. In addition, by turning off either or both of the channelization code generator and the scrambling code generator, it is possible to output the operation results required for various tests to the outside of the circuit, so various tests can be performed easily. It can be carried out.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a configuration according to a first embodiment of an HPSK spread modulation circuit of the present invention.

FIG. 2 is a circuit diagram showing a detailed configuration example of the scrambling code generator shown in FIG.

FIG. 3 is a circuit diagram showing a configuration according to a second embodiment of an HPSK spread modulation circuit of the present invention.

FIG. 4 is a block diagram showing a configuration according to an embodiment of a mobile communication terminal of the present invention.

FIG. 5 is a circuit diagram showing a configuration example of a conventional HPSK spread modulation circuit.

[Explanation of symbols]

11 DPDCH 12 DPCCH 13 Channelization code generator 14 Channel power control circuit 15, 25 Scrambling code generator 16 1/2 thinning circuit 30a, 30b Exclusive OR circuit 37 0/1 Repeating circuit 40a-40d Selector 51 HPSK Spreading modulation circuit 52 Band limiting filter circuit 53 DAC conversion circuit 54 Antennas 18a, 18b, 18e, 18f, 181-184 Multiplier 19a Subtractor 19b Adder

Claims (5)

[Claims] 1. The input data is calculated by using a channelization code for generating a channel spreading code, a gain factor for determining an amplitude amount, and a scrambling code for complex spreading, thereby calculating the input data by using the HPS.
An HPSK spread modulation circuit for performing K spread modulation to calculate an output I and an output Q, comprising: a scrambling code generation circuit for generating codes of a quadrature component and an in-phase component of complex spreading; and a scrambling code generation circuit A decimating circuit for decimating the quadrature component by ½, a repeating circuit for repeatedly outputting 0/1 in chip rate units, an in-phase component generated from the scrambling code generating circuit and the repeating circuit. A first exclusive-OR circuit that takes an exclusive-OR of 0 or 1 that is output, a quadrature-decimated orthogonal component that is output from the repeating circuit, and an output of the first exclusive-OR circuit A second scrambling code generation circuit having a second exclusive OR circuit for taking the exclusive OR of the The gain factor is multiplied by the multiplication result of the channelization code and the gain factor, and the multiplication result and the in-phase component, which is a new scrambling code output from the new scrambling code generation circuit, and the second An HPSK spread modulation circuit, wherein the output I and the output Q are calculated by performing complex multiplication with a new orthogonal component which is the output of the exclusive OR circuit. 2. An output stop means for stopping the output of the channelization code is provided, and the output of the channelization code is stopped by the output stop means,
The input data and the scrambling code are multiplied by passing through the multiplication of the input data and the channelization code, and the multiplication result and the scrambling code are subjected to complex multiplication to obtain the input data and the scrambling code. The HPSK spread modulation circuit according to claim 1, which outputs a complex multiplication result with a ring code. 3. An output stopping means for stopping the output of the new scrambling code is provided, and the output of the new scrambling code is stopped by the output stopping means, and multiplication using the scrambling code is passed through. Thus, the input data and the channelization code are multiplied, the multiplication result is multiplied by the gain factor, and the multiplication result of the input data and the channelization code is output. Item 2. The HPSK spread modulation circuit according to Item 1. 4. An output stop means for stopping the output of the channelization code and the new scrambling code is provided, and the output stop means stops the output of the channelization code and the new scrambling code, The multiplication of the input data and the channelization code is passed through, and the multiplication using the scrambling code is also passed through to multiply the input data by the gain factor and output the multiplication result. The HPSK spread modulation circuit according to claim 1. 5. The spread modulation of the input data.
To the HPSK spread modulation circuit, a band limit filter circuit that limits the band of spread modulated data output from the HPSK spread modulation circuit, and data output from the band limit filter circuit. A mobile communication terminal device, comprising: a digital-analog conversion circuit for converting into an analog signal and transmitting from an antenna.