JP2003109914A - Method of forming metallic layer and method of manufacturing semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method by which a high-purity metallic layer can be formed by CVD. SOLUTION: This method of forming the metallic layer having an target thickness by a vapor growth method (CVD) includes a step (A) of causing a metallic layer having an extremely thin thickness as compared with the target thickness to deposit by the CVD, a step (B) of changing the surface state of the deposited layer without supplying any raw material after the step (A), and a step (C) of forming the metallic layer having the target thickness by repetitively performing the steps (A) and (B).

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a metal layer and a method for manufacturing a semiconductor device, and more particularly to a vapor phase growth method (CV).
The present invention relates to a method for forming a metal layer using D) and a method for manufacturing a semiconductor device.

[0002]

2. Description of the Related Art In semiconductor devices, further improvement in integration is required. Conventionally, after forming an Al wiring layer or a W wiring layer on an insulating layer, an etching mask such as a resist pattern is formed on the Al wiring layer or W wiring layer, the wiring layer is patterned, and the wiring is formed by embedding the insulating layer. .

As the integration degree is improved, the width of wiring is reduced,
It is required to reduce the wiring interval. Along with such miniaturization, there is a limit to a technique for forming a wiring by directly etching a wiring layer. Instead, a damascene wiring is formed in which a wiring groove and a via hole are formed in the insulating layer, and the wiring layer is embedded in the wiring groove and the via hole to remove an extra wiring layer on the surface of the insulating layer by chemical mechanical polishing (CMP). The process is beginning to be utilized.

As a wiring material, Cu, which has a lower resistivity and higher electromigration resistance than Al, Al alloy, W, etc., has begun to be used.

Electroplating is currently in practical use as a technique for embedding Cu in wiring trenches and via holes. In order to perform electrolytic plating, it is necessary to previously form a seed layer, and the seed layer is formed by sputtering. With the miniaturization of wiring, the wiring grooves and via holes become fine and complicated. It is difficult to form a uniform seed layer on the sidewalls of these recesses by sputtering.

Instead of sputtering, chemical vapor deposition (CVD) has been studied as a method for uniformly forming a seed layer on the sidewalls of high-aspect-ratio via holes and wiring trenches.
As a Cu material for forming the Cu layer by CVD, an organic Cu material such as trimethylvinylsilylhexafluoroacetylacetonate copper (Cu (hfac) tmvs) is used.

The Cu layer formed by CVD using such an organic Cu material contains impurities derived from the raw materials. Therefore, the Cu layer formed by CVD has a lower purity and a higher resistance than the Cu layer formed by sputtering. Further, the Cu layer having a low purity causes a decrease in adhesion and a deterioration in migration resistance.

[0008]

Cu formed by CVD
The layer tends to have low purity, which increases resistance, decreases adhesion,
This may cause deterioration of electromigration resistance.

An object of the present invention is to form a highly pure metal layer by CVD.

Another object of the present invention is vapor deposition (CVD).
Then, a Cu layer having high purity is formed.

Still another object of the present invention is to provide a method of manufacturing a semiconductor device which can be adapted to higher miniaturization. Is to provide.

According to one aspect of the present invention, there is provided a method of forming a metal layer having a target thickness by vapor phase epitaxy (CVD),
(A) CV a metal layer that is significantly thinner than the target thickness
A step of depositing in D, (B) a step of changing the surface condition of the deposited layer without supplying a raw material after the step (A), (C) the step (A), and (B) And a step of forming a metal layer having a target thickness are repeated to provide a method for forming a metal layer.

According to another aspect of the present invention, (a) a step of forming a semiconductor element on the semiconductor substrate, (b) a step of forming an interlayer insulating film above the semiconductor substrate, and (c) the interlayer A step of forming a recess for forming a wiring in the insulating film,
(D) a step of (A) depositing a metal layer having a significantly smaller thickness than the target thickness in the recess by CVD, and (B) after the step (A), the raw material is not supplied and the deposited layer is A semiconductor device comprising: a step of changing a surface state; and (C) a step of forming a wiring layer including a step of repeating the steps (A) and (B) to form a metal layer having a target thickness. A manufacturing method is provided.

[0014]

First, a Cu layer was formed by CVD and sputtering by a known method, and its impurity concentration was analyzed by SIMS.

CVD uses Cu (hfa
c) Using tmvs, to which tmvs (2.5w%) +
The material obtained by adding _{Hhfac · 2H 2 O (HDH)} (0.4w%) was Cu material gas. The Cu source gas is 1.
It was supplied at a flow rate of 0 g / min. The growth substrate is a substrate having a TiN layer formed by metal organic chemical vapor deposition (MOCVD) as a surface layer. Hold the substrate at 180 ℃, 500
Atmospheric pressure of Pa, carrier gas H ₂ (flow rate 500 sc
cm).

The sample prepared by the sputtering method is MO
It is a substrate having a TiN layer formed by CVD on its surface. The sputtering target is Cu.

[0017]

[Table 1]

Cu (hfac) tmvs is shown in FIG.
And has O, C, F, etc. as constituent elements. The CVD layer incorporates these elements as impurities. Even if the film forming conditions such as pressure and temperature in CVD are changed, the impurity concentration does not change significantly.
According to the preliminary experiment, the Cu layer formed by CVD is
It can be seen that the impurity concentration is significantly higher than that of the Cu layer formed by sputtering.

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1A is a perspective view schematically showing the structure of a CVD apparatus for growing a Cu layer by MOCVD. A susceptor 12 for mounting the substrate 30 is arranged below the reaction container 11, and is connected to the ground by the wiring 20. A large number of openings 1 are provided at the top of the reaction vessel 11.
The shower head 13 having the number 5 is arranged, is connected to the manifold valve 25 through the pipe 14, and is supplied with the source gas. The shower head 13 also serves as an electrode, and the wiring 18 makes a high frequency power source 19 of 13.56 MHz.
It is connected to the. The reaction container 11 is provided with an exhaust port 17 and is connected to an exhaust device.

The Cu source gas is supplied to the mass flow controller 22 and a predetermined amount is distributed to the vaporizer 23. The vaporizer 23 is provided with a carrier gas port P0 and supplies a source gas in which a carrier gas and a raw material are mixed. The manifold valve 25 has a large number of ports P.
1, P2, P3, ...

The port P1 is connected to the vaporizer 23 and receives the supply of the source gas. The port P2 receives the supply of H ₂ gas. The port P3 receives the supply of NH ₃ gas. In addition, a desired gas is supplied to each port. The manifold valve 25 can switch each supply gas.

A source gas is supplied from the shower head 13, and high-frequency power is supplied between the electrodes that form the shower head 13 and the susceptor 12 into parallel plates, so that plasma is generated between the parallel plate electrodes. Cu by plasma
The source gas is decomposed and a Cu CVD layer is formed on the substrate 30. Manifold valve 25, source gas and H
_{When the two} gases are switched alternately, the raw material gas is supplied intermittently.

By turning on / off the supply of the source gas, the growth of the CVD growth layer can be turned on or off. If the conditions for removing the impurities are set while the growth is stopped, the impurities are removed from the CVD deposited layer and the impurity concentration is lowered. As a gas effective for removing such impurities, a reducing gas such as H ₂ , NH ₃ and hydrazine can be used.

FIG. 1B shows a process of growing a high-purity CVD layer using the CVD apparatus of FIG. 1A.

In step S1, a very small amount of CVD metal layer, for example, about one atomic layer is grown on the substrate 30 by CVD. The metal is Cu, for example, as described above.

Subsequently, in step S2, the growth is stopped and the surface state of the grown CVD layer is changed. For example, reduction treatment of the impurity element with a reducing gas is performed. This treatment removes impurities from the surface. If the growth layer is of the order of one atomic layer, the incorporated impurities will be efficiently removed.

Then, in step S3, it is determined whether or not a predetermined film thickness has grown. If the predetermined film thickness has not yet grown, the process returns to step S1 following the NO arrow to continue the growth. If the predetermined film thickness has grown, the process proceeds to step S4 according to the YES arrow, and the CVD
Terminate growth.

When forming the Cu layer, the Cu raw material is, for example, Cu (hfac) tmvs shown in FIG.
To use. For example, in Cu (hfac) tmvs, tm
2.5 w% vs. HDH 0.4 w% is used. As the base substrate 30, a SiO ₂ layer having a thickness of about 100 nm is formed on a Si substrate, and a MO film is further formed thereon.
A TiN layer having a thickness of about 50 nm formed by CVD is used. The target Cu layer has a thickness of 200 nm, for example.
grow up. The growth conditions are, for example, a growth temperature of 180 ° C., a raw material supply rate of 1.0 g / min, a pressure of 500 Pa, and a carrier gas H ₂ (flow rate of 500 sccm).

CVD performed in step S1 of FIG.
The growth is preferably performed in an amount equal to or less than one atomic layer. The deposited (attached) impurity element is rarely embedded in the copper element, which facilitates removal.

FIG. 2B schematically shows the structure of the CVD growth layer grown by supplying the Cu raw material in this manner.
A Cu layer of one atomic layer or less is formed on the underlayer 30, but impurities C and F are also deposited at the same time.

In step S2 of FIG. 1B, the raw material supply is stopped and the surface condition of the deposited layer is changed. For example, H ₂ which is a reducing gas is supplied. Instead, N
H ₃ , hydrazine or the like may be supplied.

As shown in FIG. 2C, by supplying the reducing gas, impurities C and F are removed and discharged to the outside. Only the Cu layer remains on the base 30.

FIG. 2D shows a state in which a Cu layer is further grown by a small amount. The figure shows a state in which the second Cu layer is formed. C and F are also deposited together with the second Cu layer.

As shown in FIG. 2 (E), the growth is stopped and the impurities are removed to form Cu of about 2 atomic layers.
Layer 32 grows. By repeating such growth, a Cu layer having a desired thickness and high purity can be obtained.

The surface condition is not changed during the growth rest period.
The gas used for the treatment is H ₂, Hydrazine, etc.
In addition to reducing gas, impurities easily escape spontaneously
In this case, an inert gas or the like can also be used. Removal of impurities
To enhance the function, H₂And NH₃Reducing gas such as
It could be turned into a zuma and irradiated with plasma. Plas
It may be possible to promote the efficiency of removing impurities by using a mask.

As the metal raw material, a halide of a metal other than an organic metal can be used. For example, TiCl ₄ ,
Using TaCl ₅ , WF _6, etc., Ti (TiN) layer, Ta
A (TaN) layer, a W layer, etc. can be formed. It may be an organic metal halide. A metal nitride layer such as TiN or TaN is also referred to as a metal layer in this specification.

When MOCVD and general CVD are compared, MOCVD may lower the growth temperature and, in the case of CVD, the gas that is practically used contains F. Since (fluorine) tends to precipitate at the interface of the layers, it is necessary to always adjust the growth parameters in consideration of cleaning the interface state.
It is considered that CVD is more advantageous for obtaining a metal layer having a low impurity concentration.

Reducing the impurities in the CVD-grown Cu layer is also effective in improving the adhesion between the grown Cu layer and the base. In order to improve the adhesion, it may be effective to supply H ₂ O during the growth rest period. It may also be useful to perform a purge before the next growth.

For the purpose of improving the adhesiveness, it is not always necessary to perform the adhesiveness improving treatment on the entire thickness to be grown. If such treatment is performed only at the initial stage of growth, it will be effective for improving the adhesion.

In the CVD apparatus of FIG. 1 (A), a shower head having a uniform structure over the entire surface was used, and the source gas was intermittently supplied to intermittently grow the CVD. The configuration of the CVD device is not limited to this.

FIG. 3 shows an example of the structure of a CVD apparatus in which the source gas is applied only to a selected section of the multiple sections. A rotatable susceptor 12 is arranged in the reaction vessel 11, and a shower head 13 having four zones is arranged above it. The shower head 13 has zones 13-1 and 13-3 for supplying a raw material gas and zones 13-2 and 13-4 for supplying only a carrier gas,
A separating curtain is provided below the zone boundary.

When the susceptor 12 is rotated, the substrate 30 on the susceptor alternately passes through the zone where the source gas is supplied and the zone where the source gas is not supplied and only the carrier gas is supplied. Therefore, although the gas supply is continuously performed, the source gas supply and the carrier gas supply are alternately performed on the surface of the substrate 30.

The growth temperature is preferably selected from 100 to 250 ° C. More preferably, 150 to 200 ° C
Select from. The lower the temperature, the less likely Cu agglomeration occurs, and the better the morphology. The film forming pressure is 100 to 5
It is preferable to select from 00Pa. When the raw material is Cu (hfac) tmvs, the raw material supply amount is 0.5 to
It is preferable to select from 3 g / min.

For example, the temperature is 200 ° C. and the atmospheric pressure is 300.
When Pa and the raw material supply rate are 1.9 g / min, the film formation rate is 8
It becomes 5 nm / min. When one rotation is one second, the exposure time of the substrate to the raw material is 0.5 seconds per one rotation. Therefore, the film formation amount per one rotation is 0.71 nm / time.
When forming a film with a thickness of 10 nm, about 14 rotations are required. Assuming that the thickness of one atomic layer is twice the atomic radius of Cu (about 0.25 nm), one atomic layer grows when the raw material is supplied for about 0.35 sec. If the susceptor is rotated once in about 0.35 sec, one atomic layer / time is obtained.

Although the case where the Cu layer is grown by MOCVD has been described, other metal layers can be grown. For example, a Ti layer, Ta layer or Zr layer can be grown. In these cases, as a raw material of Ti, for example, tetrakisdimethylaminotitanium Ti [(CH ₃ ) ₂ ]
₄ (TDMAT) and tetrakisdiethylaminotitanium T
i [(C ₂ H ₅ ) ₂ ] ₄ (TDEAT) can be used. As the Ta raw material, for example, tetrabutylimide trisdiethylamide tantalum N (Et ₂ ) ₃ Ta = NBu ^t
(TBTDET) can be used. As the Zr raw material, tetrakisdiethylaminozirconium Zr [N
(C ₂ H ₅ ) ₂ ] ₄ can be used. Ti and Ta are
For example, it can be used for growing a barrier layer. TiN or TaN may be grown by using Ti or Ta source gas together with nitrogen gas.

FIG. 4 shows the damascene C using the above-mentioned CVD.
It is a schematic sectional drawing which shows the process of forming u wiring.

FIGS. 4A to 4D are schematic sectional views showing a process of forming a damascene Cu wiring.

As shown in FIG. 4A, a lower layer wiring is formed in the lower silicon oxide layer 50 by a barrier metal layer 56 and a Cu layer 57. SiN etching stopper layers 51 and 53 and silicon oxide layers 52 and 54 are alternately formed on the lower silicon oxide layer 50. Via holes 58 are formed in the etching stopper layer 51 and the silicon oxide layer 52 to perform etching. Stopper layer 53, silicon oxide layer 5
4 has a wiring groove 59 continuous with the via hole 58. On top of such a surface structure, Ti, Ta, TiN,
The barrier metal layer 60 such as TaN is sputtered or M
It is formed by OCVD.

As shown in FIG. 4B, the Cu seed layer 61 is formed on the formed barrier metal layer by the MOC described above.
The film is formed by VD. By forming the seed layer by MOCVD, the seed layer can be surely formed on the side surface of the recess having a high aspect ratio. Furthermore, the above M
By performing OCVD, impurities are efficiently removed, so that the impurity concentration of the formed seed layer becomes low.

As shown in FIG. 4 (C), a Cu layer was grown on the seed layer by electrolytic plating, and the C layer was integrated with the seed layer.
The u layer 63 is formed.

As shown in FIG. 4D, chemical mechanical polishing (CMP) is performed from the surface to remove the unnecessary wiring layer on the silicon oxide layer 54. In this way, damascene wiring is formed.

Although the manufacturing process for forming a part of the multilayer wiring layer has been described above, the multilayer wiring layer can have an arbitrary number of wiring layers. As the insulating layer, an organic insulator having a low dielectric constant, silicon oxide containing C or F, or the like can be used. Hereinafter, a configuration example of the multilayer wiring will be described.

FIG. 5 schematically shows the structure of a semiconductor device having a multilayer wiring structure. In a predetermined region of the semiconductor wafer 1 in which the well is formed, a device isolation groove is formed, an insulator such as silicon oxide is embedded, and a shallow trench isolation (STI) 4 is formed.

Insulated gate electrodes 5 and sidewall spacers 6 are formed on the active region defined by STI, and source / drain regions S / D are formed on both sides thereof by ion implantation. The n-channel transistor and the p-channel transistor are selectively ion-implanted in separate steps using a resist mask. S to cover the insulated gate electrode
A first etching stopper layer s1 such as iN is formed, and a first lower insulating layer da1 such as silicon oxide is formed thereon. A conductor plug is formed by a barrier metal layer 7 such as TiN and a wiring metal region 8 such as W, penetrating the first lower insulating layer da1 and the first etching stopper s1.

An organic insulating film cd1 and a first upper insulating layer db1 are formed on the first lower insulating layer da1. If the organic insulating film is a coating type, it has a flattening function. CMP may be performed. It is preferable to obtain a flat surface. Forming a wiring groove in the first upper insulating layer db1 and the organic insulating layer cd1;
The first wiring layer 9 is embedded. If CMP is used in the filling step, the surface is flattened.

A second etching stopper layer s2 is formed on the surface of the first wiring layer 9, and a second lower insulating layer d is formed on the surface thereof.
a2 is formed. The second lower insulating layer da2 is planarized by CMP. A second organic insulating film cd2 and a second upper insulating layer db2 are formed on the second lower insulating layer da2 to form a dual damascene wiring structure dd1.

Similarly, a third etching stopper layer s3 and a third lower insulating layer da3 are formed on the surface of the second upper insulating layer db2 and planarized by CMP. A third organic insulating film cd3 and a third upper insulating layer db3 are formed thereon, and the second dual damascene wiring structure dd2 is embedded therein.

Further, a fourth etching stopper layer s4 and a fourth lower insulating layer da4 are formed on the third upper insulating layer db3 and flattened by CMP. A fourth organic insulating film cd4 and a fourth upper insulating layer db4 are formed on the fourth lower insulating layer da4, and a third dual damascene wiring structure dd is formed.
3 is formed. A surface protective film cv is formed on the surface of these wirings.

Although the case of forming a multilayer wiring structure of four layers has been described, the number of wiring layers can be arbitrarily increased or decreased. Further, instead of the stack of the organic insulating film and the upper insulating layer, the stack of the etching stopper layer and the insulating layer may be used.
A laminated insulating layer including a low dielectric constant insulating layer such as a silicon oxide layer containing fluorine or carbon or a porous silicon oxide layer can also be used. It will be apparent to those skilled in the art that other configurations can be used as the interlayer insulating film.

The present invention has been described with reference to the examples, but the present invention is not limited to these. For example, a metal layer other than wiring may be formed. Although the case where the Cu layer is formed by MOCVD has been mainly described, Cu, Ti, Ta, and Ta are prepared using a raw material containing at least one of C, Cl, and F.
A metal layer containing either W or Zr can be formed. It will be apparent to those skilled in the art that various other modifications, improvements, and combinations can be made.

The features of the present invention will be additionally described below.

[0063]

As described above, according to the present invention,
A high-purity metal layer can be formed by CVD. The metal layer can be formed with high reliability even in the recess having a high aspect ratio.

A highly reliable copper wiring can be formed.

[Brief description of drawings]

FIG. 1 is a schematic perspective view of a CVD apparatus used in a method for forming a metal layer according to an embodiment of the present invention, and a flowchart illustrating a forming process.

FIG. 2 is a cross-sectional view schematically illustrating a chemical structural formula of an organic Cu raw material and formation of a metal layer according to an example of the present invention.

FIG. 3 is a schematic perspective view showing a metal layer forming apparatus according to another embodiment of the present invention.

FIG. 4 is a cross-sectional view showing a manufacturing process of wiring of a semiconductor device.

FIG. 5 is a cross-sectional view of a semiconductor device having multilayer wiring.

[Explanation of symbols]

11 Reaction vessel 12 susceptor 13 shower head 15 openings 17 exhaust port 18, 20 wiring 22 Mass flow controller 23 Vaporizer 25 manifold valve Pi port

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Claims (5)

[Claims] 1. A metal layer having a target thickness is formed by vapor phase epitaxy (CV).
The method of forming a metal layer having a thickness remarkably smaller than the target thickness (A) is a method of forming the metal layer by CV.
A step of depositing in D, (B) a step of changing the surface state of the deposited layer without supplying a raw material after the step (A), (C) the steps (A) and (B) And a step of forming a metal layer having a target thickness by repeating the above step. 2. In the step (A), a source gas containing at least one of C, F and Cl is used, and Cu, Ti and T are used.
a metal layer containing any of a, W, and Zr is deposited, and the step (B) is performed while supplying at least one of a reducing gas, hydrazine, and an inert gas, or H ₂ plasma, NH ₃ plasma The method for forming a metal layer according to claim 1, which is performed while irradiating any one of the above. 3. The method for forming a metal layer according to claim 1, wherein the step (A) forms a metal layer of one atomic layer or less. 4. The method according to claim 1, wherein the target thickness is a part of the final thickness, and further comprising (D) continuously depositing a metal layer having the remaining thickness by CVD. Item 1. The method for forming a metal layer according to Item 1. 5. A step of forming a semiconductor element on a semiconductor substrate, a step of forming an interlayer insulating film above the semiconductor substrate, and a step of forming a wiring in the interlayer insulating film. 5. A method of manufacturing a semiconductor device, comprising the step of: forming a wiring layer in the recess by the method of forming a metal layer according to claim 1.