JP2003109376A - Semiconductor memory device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a nonvolatile semiconductor memory device which can read data without destruction. SOLUTION: A silicon film 200 being useful for an active layer of a MIS transistor 20 is formed on a surface of an insulation film 37 of a ferroelectric capacitor 30. A gate insulation film 25 is formed on a surface of the silicon film 200, further a gate electrode 21 is formed on a surface of the gate insulation film 25. A source region 22 and a drain region 23 are formed on the silicon film 200 by such a method that automatic positioning is performed for the gate electrode 21. A channel region 24 is provided between the source region 22 and drain region 23.

Description

Detailed Description of the Invention

[0001]

FIELD OF THE INVENTION The present invention relates generally to semiconductor memory devices, and more particularly to non-volatile semiconductor memory devices.

[0002]

2. Description of the Related Art Among various kinds of semiconductor memory devices,
An FeRAM (ferroelectric memory) has memory cells, and each has a gate electrode 21A and a source region 22A of an N-channel type MIS transistor, as can be seen from FIG. 10A showing an equivalent circuit thereof. Word line WL
, And the bit line BL, and the ferroelectric capacitor 30A is electrically connected between the drain region 23A of the MIS transistor and the plate line PL.

In the case of such a type of semiconductor memory device 1A, when one of binary data "1" and "2", for example, data "1" is written in the memory cell 10A, the word line WL is written. Is set to a high level (H) while the bit line BL is held at a high level (H), while the plate line PL is held at a low level (L). As a result, the MIS transistor 10A is turned on. Therefore, in the ferroelectric capacitor 30A, as shown in FIG. 10B, the electrode 31A connected to the drain region 23A of the MIS transistor 10A.
Is set to a high level (H), while the electrode 32A electrically connected to its plate line PL is set to a low level (L). This is a ferroelectric capacitor 30A
Polarization occurs in the ferroelectric layer.

In contrast, when data "0" is written to memory cell 10A (ie, erased data is written to it), the word line WL is as shown in FIG. 11 (A). Is set to a high level (H) while the bit line BL is held at a low level (L),
The plate line PL is set to a high level (H). As a result, the MIS transistor 10A is turned on. In the ferroelectric capacitor 30A, as shown in FIG. 11B, the drain region 2 of the MIS transistor 10A is formed.
The electrode 31A connected to 3A is set to a low level (L), while the electrode 32A electrically connected to the plate line PL is set to a high level (H). Therefore, the ferroelectric layer of the ferroelectric capacitor 30A has data "1".
Is polarized in the direction opposite to the polarization direction when writing to it.

Next, the operation of reading information will be described below. First, the bit line BL is precharged to the ground potential. Therefore, the bit line BL is brought into a high impedance state. Then, the potential of the plate line PL is fixed to the ground potential. At that time, the ferroelectric capacitor 30A
Remains polarized as before. Then, the plate line PL is set to the high level (H). At that time, the electric charge is discharged from the ferroelectric capacitor 30A. The amount of charge discharged depends on the direction in which the polarization was previously generated. Further, the discharged charges appear as a voltage on the bit line BL. Therefore, whether the data represents "1" or "0" is determined by amplifying this voltage by the sense amplifier.

[0006]

However, the conventional FeR
In the case of AM, the ferroelectric capacitor 30A discharges when information is read. Therefore, it is necessary to hold the data in order to write it back there. That is, in the case of the conventional FeRAM, the destructive read operation is executed. Meanwhile, in the case of FeRAM, the number of times of writing data is usually limited. Therefore, for destructive read operations, writing of data is required each time the information is read. As a result, the application range of the conventional FeRAM is extremely limited.

Therefore, the problem to be solved by the present invention is to provide a non-volatile semiconductor memory device in which a memory cell is composed of one transistor and one capacitor and which can be read without destroying data. To do.

[0008]

In order to solve the above problems, according to a first aspect of the present invention, a plate electrode, a ferroelectric layer, an insulating film, and a channel of a MIS (metal insulator semiconductor) transistor. A semiconductor memory element is first provided that includes at least a plurality of memory cells each formed by stacking a region, a gate insulating film of a MIS, and a gate electrode of a MIS transistor in this order. The word line is electrically connected to the gate electrode of each of the plurality of memory cells. The first and second bit lines are electrically connected to the source region and the drain region of the MIS transistor, respectively. The plate line is electrically connected to the plate electrode.

In the specification of the present application, the term "MIS"
Is strictly for the purpose of representing the structure, and does not mean that the gate electrode is limited to the metal electrode. The term “MIS” means, for example, a doped silicon film may be used as the gate electrode.

According to the first aspect of the present invention, the MIS transistor is, for example, a thin film transistor.

In the semiconductor memory device of the present invention, when data is stored in the memory cell, a voltage having a polarity corresponding to the data is applied between the plate line and each of the first and second bit lines. Further, a gate voltage for turning on the MIS transistor is applied from the word line to the gate electrode.

For example, when one type of binary data is stored in a memory cell, one of the binary data is stored.
Voltages of polarities corresponding to one type are applied between the plate line and each of the first and second bit lines. Furthermore, M
A gate voltage that turns on the IS transistor is applied to the gate electrode from the word line. In contrast, when another type of binary data is stored in the memory cell, a voltage having a polarity opposite to that of the voltage applied when storing one type of data causes the plate Applied between the line and each of the first and second bit lines. Furthermore, MIS
A gate voltage that turns on the transistor is applied from the word line to the gate electrode.

When data is written to it in this manner, a charge corresponding to the polarity of the voltage applied between the plate line and each of the first and second bit lines is stored in the ferroelectric layer. In the semiconductor memory device having the above structure, the channel region of the MIS transistor is affected by the polarity of the polarized ferroelectric layer due to the charges accumulated in the ferroelectric layer. This is MIS
A change occurs in the source / drain current-gate voltage characteristics of the transistor. Therefore, “first gate voltage”
Is the gate voltage at which the source / drain current reaches a predetermined level according to the source / drain current-gate voltage characteristics of the MIS transistor when one kind of binary data “1” and “0” is written in it. Represent Furthermore, the "second gate voltage" represents the gate voltage at which the source / drain current reaches a predetermined level when another type of binary data "1" and "0" is written to it. Moreover, "data read gate voltage" represents the potential level between the first and second gate voltages. If the read voltage is applied between the source and drain of the MIS transistor and the data read gate voltage is applied from the word line to the gate electrode, whether the source / drain current is flowing or not is determined by the first bit. Detected from the line or the second bit line. As a result, it is determined which kind of data "1" and "0" is written to it.

According to the present invention, when data is read in this way, the charge stored in the ferroelectric layer only electrostatically affects the channel region and is not discharged to the semiconductor memory device. Therefore, even when the data written to the memory cell is read, the charge stored in the ferroelectric layer still remains stored therein. As a result, the data is not destroyed.

It has been known for quite some time that ferroelectric materials exhibit an internal polarization and this can be adapted to provide two stable polarization states. Switching between the two states can be used to store binary data. Memory devices have been implemented using this technique, but the problem was that the data read operation destroyed the data. That is, in order to distinguish between the two possible polarization states, it is necessary to apply sufficient voltage to switch between the two states. Therefore, the data is lost on reading. To overcome this problem, it is possible to rewrite the data after reading, but this obviously leads to overhead, power consumption, and operating speed in terms of unwanted circuit components. These factors have an undesirable effect on overall device size, ease of manufacture, and cost. further,
An increase in storage density requires a corresponding decrease in read current, which adversely affects read sensitivity.

A proposal to mitigate the above mentioned drawbacks is to use a thin film transistor structure in which a ferroelectric material is used as the gate insulator. The basic structure of such an element is shown in FIG. A layer of ferroelectric material (PZT) connects the gate (G) to the conventional source (S), channel (C),
And drain (D) provided on them to separate them from the active layer. That is, the ferroelectric material acts as a gate dielectric. Ferroelectric materials cause a variation in the threshold voltage of the transistor that depends on the polarization state of the ferroelectric material. In other words, this result is the introduction of hysteresis into the transfer characteristics of the transistor. The hysteresis of the conversion characteristic can be detected without changing the polarization state of the ferroelectric material. In this way, non-destructive reading of the stored data can be realized. In addition, the element sensitivity is W /
It can be seen that it remains constant as the L dimension changes.

From the above description it will be justified that the structure according to FIG. 12 has very important potential advantages. However, attempts to realize a practical memory structure have raised two important problems. First, difficulties have arisen at the physical interface between the ferroelectric material used for the active source / channel / drain layers and silicon.
Although this problem can be alleviated to some extent by the introduction of a buffer layer, such a buffer layer is difficult to fabricate and significantly degrades device performance. Second, and more importantly, when the structure is repeated in a matrix to form a large scale memory device, it is very susceptible to crosstalk, ie a write operation for one cell often affects another. I know that it will affect.

Against this background, in one aspect of the invention, it has been observed that the charge on the backside of the channel affects the threshold voltage of the transistor because the active layer is very thin (typically on the order of 50 Angstroms). It was The effect is significant, and a change of ± 1 volt in threshold voltage is ± 1.6
It is caused by a charge on the order of x10 ^-7 coulombs. One aspect of the present invention uses this normally undesirable property to alleviate problems in practical implementation of memory devices with thin film structures and ferroelectric data storage.

According to one aspect of the invention, an active layer in which the source, channel and drain of a transistor are formed, a gate for the transistor, a layer of ferroelectric material and a voltage to the ferroelectric material. A semiconductor memory device is provided with an electrode for applying, the electrode is spaced from the gate, and the layer of ferroelectric material has two stable states of internal polarization, in this arrangement two polarization states. Have a detectable difference in their effect on the conversion characteristics of the transistor.

Embodiments of the present invention will now be described for further illustration with reference to the accompanying drawings.

[0021]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS [First Embodiment] (Overall Structure) FIG. 1 shows an equivalent circuit illustrating the structure of memory cells formed in a matrix in a semiconductor memory device to which the present invention is applied. It is a circuit diagram.

As shown in FIG. 1, in the semiconductor memory device 1 according to the present embodiment, a plurality of first bit lines BL1 are provided.
a, BL1b, BL1c ,. ． ． (Hereinafter, referred to as “first bit line BL1”), a plurality of second bit lines BL2a, BL2b, the number of which is equal to that of the first bit line.
BL2c ,. ． ． (Hereinafter, referred to as "second bit line BL2"), and the plurality of plate lines PLa, PL
b, PLc ,. ． ． (Hereinafter referred to as “plate line PL”) extends in the vertical direction. Further, as can be seen in this figure, a plurality of word lines WLa, WLb, WLc ,. ． ．
(Hereinafter, referred to as “word line WL”) extends in the lateral direction. These word lines WL are the first bit lines BL1,
It intersects with the second bit line BL2 and the plate line PL.

Further, in the semiconductor memory device 1, the memory cells 10aa, 10ab, 10ac ,. ． ． 10,
ba, 10bb, 10bc ,. ． ． 10ca, 10c
b, 10 cc ,. ． ． (Hereinafter referred to as "memory cells 10") are arranged in a matrix corresponding to the intersections between these signal lines.

In the case of semiconductor memory device 1 shown in this figure, one MIS transistor 20 and one ferroelectric capacitor 30 are formed in each memory cell 10. In the case of this embodiment, an N-channel thin film transistor is used as the MIS transistor 20.

In this embodiment, the gate electrode 21 and the source region 22 are the word line WL and the first bit line BL1.
10 (A) and 10 respectively electrically connected to
(B), and similar to the conventional FeRAM described with reference to FIGS. 11 (A) and 11 (B).

By the way, in the semiconductor memory device 1 according to the present embodiment, the drain region 23 of the MIS transistor 20 is electrically connected to the second bit line BL2 in each of the memory cells 10. Further, the ferroelectric capacitor 30 includes the channel region 24 of the MIS transistor 20 and the plate line PL in each memory cell 10.
It is provided between.

In the present embodiment, such a configuration of the memory cell 10 is realized by the structure shown in FIGS.

FIG. 2 is a plan view showing the structure of each memory cell. FIG. 3 is a sectional view taken along line II-II ′ of FIG.

As shown in FIGS. 2 and 3, the plate electrode 35, the ferroelectric layer 36, and the insulating film 37 are arranged in this order from the bottom layer to the upper surface of the insulating substrate 2 serving as the base of the semiconductor memory device 1. Stacked in the direction to the layers. The ferroelectric capacitor 30 is formed from these layers. By the way, the ferroelectric capacitor 30 includes lead / zirconate / titanate (PZT), barium / strontium / titanate (BST), and strontium.
Bismuth niobium tantalate (Y1 system)
May be used as the material of the ferroelectric layer 36. This embodiment uses PZT. Moreover, the ferroelectric capacitor 30 uses the plate electrode 35 as one of the two electrodes and the channel region 24 (described below) of the MIS transistor 20 as the other electrode.

A silicon film 200 serving as an active layer of the MIS transistor 20 is formed on the surface of the insulating film 37 of the ferroelectric capacitor 30. The gate insulating film 25 made of a silicon oxide film is the silicon film 20.
It is formed on the surface of zero. Further, the gate electrode 21 composed of a metal film or a doped silicon film
Are formed on the surface of the gate insulating film 25. In the present embodiment, the source region 22 and the drain region 23
Are formed on the silicon film 200 by a method such as automatic alignment with the gate electrode 21. The channel region 24 facing the gate electrode 21 through the gate insulating film 25 is
It is provided between the source region 22 and the drain region 23.

In the case of the example shown in this figure, the gate electrode 21 is a part of the word line WL. Furthermore, in the case of the example shown in this figure, the intermediate layer insulating film 26 is
Formed on the surface of. The first bit line BL1, the second bit line BL2, and the plate line PL have a source region 22, a drain region 23, and And is electrically connected to the plate electrode 35.

Moreover, the channel region 24 has substantially the same length as the gate electrode 21 in the channel length direction. The ferroelectric layer 36 also has substantially the same length as the gate electrode 21 in the channel length direction.

(Data Writing Operation) FIGS. 4A and 4
(B) is a diagram showing how one type "1" of binary data is written to this memory cell, respectively, and electric charge is stored in the ferroelectric capacitor when data "1" is written to it. It is a figure which shows the method. Figure 5
(A) and 5 (B) are diagrams showing how other types of binary data "0" are written to this memory cell, respectively, and when the subsequent data "0" is written to it, the charge is strong. It is a figure which shows the method accumulated in a dielectric capacitor.

In the case of this type of semiconductor memory device 1, 2
When one of the binary data “1” and “0”, for example, the data “1” is written to the memory cell 10,
As shown in FIG. 4A, the first bit line BL1 and the second bit line BL2 are set to the high level (H), while the plate line PL is set to the low level (L). Fixed. In this state, the word line WL is set to a higher level (HH) voltage, which is higher than the level (H) of the first bit line BL1 and the second bit line BL2. As a result, as shown in FIG.
The transistor 20 is turned on, so that the channel region 24 is set to a high level voltage, which is higher than the level of the plate line PL. Therefore, as shown in 4 (B), polarization occurs in the ferroelectric capacitor 30 in response to the applied electric field.

In contrast, data "0" is stored in memory cell 10
When written in, as shown in FIG.
The first bit line BL1 and the second bit line BL2 are set to a low level (L), while the plate line PL is set to a high level (H) and fixed. In this state, the word line WL is set to a higher level (HH) voltage, which is higher than the level (H) of the plate line PL. As a result, as shown in FIG. 5B, the MIS transistor 20 is turned on, so that the channel region 24 is at a potential level lower than the level of the plate line PL. Therefore, as shown in FIG. 5B, polarization occurs in the ferroelectric capacitor 30 in response to the applied electric field.

(Data Read Operation) FIGS. 6A and 6A
(B) is a diagram showing the principle of reading the data written in the memory cell 10, and a MIS exemplifying this principle.
6 is a graph showing a relationship between a source / drain current and a gate voltage of a transistor. FIG. 7 shows this memory cell 10.
It is a figure which shows the method of reading the data written in.

When data is written in the memory cell 10, the charge corresponding to the polarity of the voltage applied between the plate line PL and each of the first bit line BL1 and the second bit line BL2 is ferroelectric. It is accumulated in the body layer 36.

Ferroelectric layer 36 of ferroelectric capacitor 30
The effect of the charge stored on the MIS transistor 20 on the characteristics thereof will be described below with reference to FIG.

FIG. 6B shows a counter electrode (that is, the plate electrode 3) facing the gate electrode 21 in relation to the channel region 24 of the MIS transistor 20 shown in FIG.
5) The source when changing the voltage V _sub applied to
The drain current characteristics are shown. As shown in this figure, M
The source / drain current characteristics of the IS transistor 20 are
The voltage V _sub varies as indicated by the solid line L1, the dashed-dotted line L2, and the dotted line L3, corresponding to having positive values, negative values, and zero, respectively.

That is, the voltage V_subIs MIS transition
When it is 0 in the star 20, it is indicated by a dotted line L3.
Therefore, the source / drain current is
Value V _gsIt has a minimum value when it has (Int). So
At this time, the source / drain voltage is constant. further,
If the gate voltage rises from such a value, the
The “current” flows through the MIS transistor 20. That
In addition, the source / drain current increases as the gate voltage increases.
Increase to a certain level. In addition, if the gate voltage is lowered
Off leakage current (ie source drain
Current) flows through the MIS transistor 20. So
In addition, the source / drain current increases the gate voltage.
Increase with By the way, the threshold is a certain level
As the gate voltage when the current it has flows through it
Defined here. The threshold in this case is "V_th(In
t) ”.

Such a relationship between the source / drain current and the gate voltage is similarly applicable to the case of positive and negative values of the voltage _Vsub . However, the gate voltage of the source-drain current has a minimum value, depending on the electrostatic effects of the voltage V _{s ub} in the channel region 24,
The value of this voltage is moved in the direction of increasing or decreasing. For example, if the voltage V _sub has a positive value,
The source-drain current has a minimum value when the gate voltage is equal to the value V _gs 0, as shown by the solid line L1. In addition, the threshold (ie, the first gate voltage)
Changes to a voltage value V _th (0).

In contrast, when the voltage V _sub has a negative value, the source-drain current has a minimum value when the gate voltage has a value V _gs 1, as indicated by the dashed-dotted line L2. . Further, the threshold value (that is, the second gate voltage) changes to the voltage value V _th (1).

By the way, binary data "1" and "0"
One of them, that is, the data “1” is stored in the memory cell 1
When written to 0, the ferroelectric layer 36 is
As shown in (B), the semiconductor memory device 1 is polarized according to this embodiment. This state is the voltage V _sub
Corresponds to the state where MIS transistor 20 has a negative value. Therefore, the MIS transistor 20 is
The source displayed by the one-dot chain line L2 in FIG.
Shows drain current characteristics

In contrast, data "0" is stored in memory cell 10
5B, as shown in FIG.
The ferroelectric layer 36 is polarized. This state is the voltage V _sub
Corresponds to the state where MIS transistor 20 has a positive value. Therefore, the MIS transistor 20 is
FIG. 6B shows the source-drain current characteristics displayed by the solid line L1.

[0045] Therefore, in the case of the semiconductor memory device 1 according to the present embodiment, when data is read from the memory cell 10, as shown in FIG. 7, the first voltage V _th
An intermediate voltage V _g between (0) and the second voltage V _th (1)
(Ie, the read gate voltage) is applied to the MIS transistor 20 from the word line WL. Further, a voltage substantially equal to the read gate voltage is applied to the plate line PL as the read plate potential V _plate .

Further, the read voltage VDD (which is a positive voltage) is applied to the first bit line BL1, while the ground voltage (ie zero voltage 0) is applied to the second bit line BL2.
Applied to.

As a result, the data "1" is stored in the memory cell 10
, The source-drain current is MIS
Almost no current flows through the transistor 20. Conversely,
When data “0” is written in the memory cell 10,
Large source / drain currents flow through it. Therefore, when the source / drain current is detected on the first bit line BL1 or the second bit line BL2, if the level of the source / drain current is less than a certain level, the data "1" is stored in the memory. It is decided to write to cell 10. Conversely, if the level of the source / drain current is equal to or higher than a certain level, it is determined that the data “0” is written in the memory cell 10.

By the way, when the memory cells 10 are arranged in a matrix, it is necessary that the voltage V _th (0) is a positive voltage in order to enable the selective reading of data. That is, it is necessary to satisfy the following inequalities. 0 <V _th (0) <V _g <V _th (1) The threshold value is controlled so that the relationship represented by such an inequality is maintained.

In this embodiment using such a principle, the read voltage VDD (which is a positive voltage) is the first bit line corresponding to the memory cell 10 (for example, memory cell 10bb) that needs to read data. BL1 (for example,
It is applied to the first bit line BL1b). In addition, the ground potential (0) is the memory cell 1 that needs to read data.
It is applied to the second bit line BL2 corresponding to 0 (for example, the second bit line BL2b). In such a state, the read gate voltage V _g and the plate potential V _{g
pl ate} (= gate voltage _{V g)} is a word line WL (for example, word line WLb) and the plate line PL (e.g., a plate line PLb) are respectively applied to, these correspond to the memory cell 10 which is necessary to read the data To do.
Meanwhile, zero voltage 0 is supplied to the other signal lines.

Therefore, when the read gate voltage V _g is applied to the word line WL corresponding to the memory cell 10 that needs to read the data, the change in the current is the first bit line B.
When detected by reading from L1b and the second bit line BL2b, which of the binary data “1” and “0” is the data stored in the memory cell selected by the word line WL. Can be determined.

(Effect of this Embodiment) As described above, the MIS
The channel region 24 of the transistor 20 is the ferroelectric layer 3
By utilizing the fact that the source-drain current-gate voltage characteristic of the MIS transistor 20 changes when it is electrostatically affected by the charge stored in the semiconductor memory device 6, The data written in the memory cell 10 is determined.

Moreover, the charges accumulated in the ferroelectric layer 36 at the time of reading the data only affect electrostatically and are not discharged. Therefore, even when the data written to the memory cell 10 is read, the charge stored in the ferroelectric layer 36 remains stored in the ferroelectric capacitor 30.

(Manufacturing Method) The semiconductor memory device 1 constructed by this method is well known in the semiconductor process, in particular,
It can be manufactured by combining low temperature polycrystalline silicon TFT (thin film transistor) processes. Therefore, the method for manufacturing the semiconductor memory device 1 is as shown in FIG.
It will be explained below by reference to 3 and 4.

First, a clean insulating substrate 2 is prepared.

Subsequently, a conductive film composed of a metal film or a doped silicon film is formed on the surface of the insulating substrate 2. Thereafter, patterning of this conductive film is performed using photolithographic techniques. Thus, the plate electrode 35 is formed.

Next, a thin film made of a ferroelectric material is
It is formed on almost the entire surface of the substrate 2 by a film forming method such as a CVD method, a sol-gel method using a metal alkoxide solution, and a sputtering method. then,
Patterning of this thin film is performed using photolithographic techniques to form the ferroelectric layer 36.

Subsequently, the insulating film 37 made of a silicon oxide film is formed on almost the entire substrate 2 by some kinds of film forming methods such as the plasma CVD method.

Next, a silicon film is formed on the insulating substrate 2 by some kind of film forming method such as a plasma CVD method.

After that, patterning of the silicon film is performed by using the photolithography technique to form the island-like silicon film 200. By the way, a material obtained by forming an amorphous silicon film by a low temperature process and then crystallizing the amorphous silicon film by a laser annealing method may be used for forming the silicon film.

Subsequently, the gate insulating film 25 made of a silicon oxide film is formed on almost the entire surface of the insulating substrate 2 by some kinds of film forming methods such as a plasma CVD method.

Then, the conductive film composed of the metal film or the doped silicon film is formed into the gate insulating film 2.
5 is formed on the upper surface. Thereafter, patterning of this conductive film is performed using a photolithography technique to form the gate electrode 21.

Next, N-type impurities are introduced into the silicon film 200 by using the gate electrode 21 as a mask. As a result, the source region 22 and the drain region 23 are formed on the silicon film 200 in such a manner that they are automatically aligned with the gate electrode 21.

Subsequently, the intermediate insulating film 26 made of a silicon oxide film is formed on almost the entire surface of the insulating substrate 2 by some kinds of film forming methods such as the plasma CVD method. After that, a contact hole is formed in the intermediate insulating film 26.

Next, a conductive film, for example, a metal film such as an aluminum film or a doped silicon film is formed. Subsequently, patterning of the conductive film is performed by using a photolithography technique, and the first bit line BL1, the second bit line BL2, and the plate line PL.
Is formed.

[Second Embodiment] FIG. 8 shows a second embodiment of the present invention.
FIG. 6 is a plan view showing the configuration of a memory cell formed in another semiconductor memory device which is the embodiment of the present invention. 9 is the line of FIG.
FIG. 8 is a sectional view taken along line VIII-VIII ′. by the way,
The basic structure of the semiconductor memory device according to the present embodiment is shown in FIG.
3 and 4 is similar to that of the semiconductor memory device according to the first embodiment described with reference to FIGS. Thus, in FIGS. 8 and 9, the same symbols represent common components of the first embodiment. Therefore, a description of such components is omitted here. Further, the data writing and reading operations of the another semiconductor memory device 1 according to the second embodiment are similar to those of the semiconductor memory device according to the first embodiment. Therefore, a description of these operations of the second embodiment is omitted here.

In the case of the semiconductor memory device 1 described with reference to FIGS. 2 and 3, the first bit line B
The L1 and the second bit line BL2 are connected to the intermediate insulating film 26.
It is formed by using a conductive film formed on the surface of. In contrast, in the case of the semiconductor memory device 1 shown in FIGS. 8 and 9, the wiring component obtained by straightening the conductive film of the plate electrode 35 in each of the memory cells 10 is used as the plate line PL. It Further, in each of the memory cells 10, MI
Silicon film 20 forming an active layer of the S transistor 20
Wiring components obtained by extending from both ends of a region formed as an active layer in 0 are used as the first bit line BL1 and the second bit line BL2.
That is, each of the first bit lines BL1 is a conductive region integrated with the source region 22 of the MIS transistor 20, while each of the second bit lines BL2 is integrated with the drain region 23 of the MIS transistor 20. Is a conductive region. By the way, each of the word lines WL is integrated with the gate electrode 21. The electrode 21 of the MIS transistor 20 is similar to that of the first embodiment.

When a semiconductor memory device is formed by this method, when source region 22 and drain region 23 are formed, first bit line BL1 and second bit line BL2 can be formed simultaneously.

Further, when the plate electrode 35 is formed, the plate line PL can be formed. Therefore, the second
The embodiment of 1 has an advantage that the number of processes for manufacturing the semiconductor memory device 1 is small.

[Other Embodiments] In any of the above embodiments, the upper gate type TFT is formed as the MIS transistor 20 formed in the memory cell 10. However, the bottom gate of the TFT may be used. Furthermore, the N-channel thin film transistor is MIS
It is formed as the transistor 20. As another option, a P-channel type thin film transistor may be used as the MIS transistor 20.

The structure of another embodiment of the present invention is shown in FIG. The structure comprises a conventional thin film arrangement of source (S) / channel (C) / drain (D) active layers with gates (G) separated by insulating layers (I). However, instead of forming this arrangement directly on the substrate (Sub), it is formed on a layer of ferroelectric material (PZT). The ferroelectric material (PZT) is supported by the device substrate (Sub).

Within the substrate and below the ferroelectric material is the electrode (E). This electrode (E) is used to apply a voltage to the ferroelectric material so as to switch the internal polarization of the ferroelectric material between two stable states. That is, this electrode (E) is used to write data to the memory. In the arrangement of FIG. 12, the conversion characteristics of the transistor are
Figure 4 shows an easily measured hysteresis that depends on the state of internal polarization of a ferroelectric material. Therefore, the data stored in the device can be read without being destroyed.

Unlike the arrangement shown in FIG. 12, FIG.
Structure has a ferroelectric material (PZT) on the opposite side of the active layer (S, C, D) to the gate (G) of the transistor. Furthermore, a gate is provided (in a conventional manner) for controlling the transistor, whereas a separate electrode (E) is provided.
Are provided to switch between the two polarization states of the ferroelectric material. Nevertheless, since the polarization of the ferroelectric material still affects the conversion properties of the transistor, the state of polarization can be determined easily and without destruction.

As shown in FIG. 13, the size of the electrode (E) for switching the ferroelectric material is significantly smaller than the size of the gate (G). The size of the gate (G) is determined by the need to ensure proper control of the active layers (S, C, D). In contrast, there are few restrictions on the minimum size of the electrodes (E) that switch the ferroelectric material. Therefore, by arranging the size of the electrode (E) for switching the ferroelectric material to be significantly smaller than the size of the gate (G), it is adjacent to the source (S) and the drain (D), respectively, and is strong. It is possible to ensure that it is the area that controls the switching of the dielectric material. In essence, the memory effect of a ferroelectric material is equivalent to data storage in a capacitor, one plate of the capacitor being provided by the electrode (E) and the other plate being adjacent to the source (S) and drain (D), respectively. Given by the combined effect of the areas of. Therefore,
The equivalent circuit diagram of the structure shown in FIG. 13 is the circuit shown in FIG.

As shown by the equivalent circuit of FIG. 14, the embodiment shown in FIG. 13 is equivalent to two series-connected transistors (110, 112) with one plate of the data storage capacitor (114) being a transistor ( 110, 112) may be considered to be connected to a series connection point. By arranging the switch collinearly with the capacitor (114), it is possible to eliminate interference problems that have traditionally prevented practical implementation of large scale data storage matrices using ferroelectric data memory cells.

FIG. 15 shows a waveform of a signal applied to the electrode (E) made of a ferroelectric material. A first pulse is applied during period (a) and equal and opposite pulses are applied during period (b). The desired data write operation is performed during the period (a) at the currently addressed memory cell. However, adjacent cells in the matrices see an overall zero change due to the equilibrium of the pulse in period (a) and the pulse in period (b). Elimination of the crosstalk problem allows for the realization of large storage matrices.

Compared with the structure of FIG. 12, the structure of FIG. 13 has a considerable advantage in the actual manufacturing process. Specifically, the structure of FIG. 13 may be manufactured by first forming a thin film transistor by conventional techniques.
These techniques include high temperature processes, especially laser annealing of active silicon layers. It is these high temperature processes that cause the interface problem between silicon and the ferroelectric material in the structure according to FIG. In the structure according to FIG. 13, the ferroelectric material can be spin-coated on the device, for example after fabrication of a conventional thin film transistor structure. There is no requirement for automatic alignment of electrodes (E) in the same way that there is a requirement for automatic alignment of gate (G) with channel (C) in a transistor structure. Therefore, interface problems may also be prevented, or at least mitigated, using the structure according to the invention and without using a buffer layer which degrades performance.

The embodiments of the invention described above are applicable to thin film arrangements, or in general, arrangements where the presence of a ferroelectric material affects the conversion characteristics of a transistor. But,
Another embodiment of the invention is based on the recognition of the values of the equivalent circuit shown in FIG. 14 and its general application, for example for single crystal transistor devices which are not necessarily thin films. FIG. 16 (d) shows a structural embodiment of the equivalent circuit of FIG. 14, which can be applied to a single crystal transistor device whose structure is not necessarily a thin film. FIG.
(A)-(d) show manufacturing steps for forming a memory device according to this embodiment of the present invention.

FIG. 16A shows an intermediate stage of manufacturing the conventional transistor structure. The source (S), channel (C), and drain (D) are built into the active layer, the insulating oxide layer (I) is formed on the active layer, and the gate (G) is self-aligned with the channel. Formed on the oxide layer. Proceeding beyond conventional manufacturing steps, and as shown in FIG. 16 (b), the upper middle portion of the structure divides the gate and below the gap thus formed in the gate. Etched to remove oxide. In addition, oxide is grown around the two newly separated partial gate electrodes (G1, G2). Next, a layer of ferroelectric material (PZT) is formed in FIG.
It is deposited over the entire surface of the structure shown in Figure 16 (b) to yield the structure shown in (c). Then, a metal electrode (M) is formed as shown in FIG.
Two of them are in contact with the source and the drain, respectively, and one is formed in the gap between the two partial gate electrodes (G1, G2).

A general planar layout of a memory device using the cell structure shown in FIG. 16 (d) is shown in FIG. In the same equivalent circuit (FIG. 14) as the embodiment of FIG. 13,
Apparently, the embodiments of FIGS. 16 and 17 are inter-cell when performing a write operation on a matrix semiconductor memory,
In particular, it presents the same advantage of preventing inter-row interference problems.

As another aspect of the invention, it has been recognized that it is possible to implement a memory cell by utilizing the variant of FIG. 14 in which the two switching transistors are reduced to a single switching transistor. It was The equivalent circuit of this modification is shown in FIG. Specifically, in terms of equivalent circuit, the circuit of FIG. 18 is the same as that of FIG. 14 except that one of the transistors (eg, transistor 112) is replaced by a simple switch (116). Is. In fact, this is
This means that the drains of the remaining switching transistors (110) can float.

The structural embodiment of the circuit of FIG. 18 has partial gate lengths (regions adjacent to the source and drain, respectively, in FIG. 13) L1 and L3, and ferroelectric contact (E) lengths. It can be deduced from other embodiments of the invention by letting L2 and let L3 go to zero. In practice, this means that it is not necessary to form the gate G and split it as in Figures 16 (a) and 16 (b),
Therefore, the manufacturing process shown in FIG. 16 is thus simplified.

It will be appreciated by those skilled in the art that the above description has been made for the purpose of illustration only and modifications may be made without departing from the scope of the invention.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing an equivalent circuit showing a configuration of each of a plurality of memory cells formed in a matrix in a semiconductor memory device according to a first embodiment of the present invention.

2 is a plan view showing a configuration of a memory cell formed in the semiconductor memory device shown in FIG.

FIG. 3 is a cross-sectional view taken along line II-II ′ of FIG.

[FIG. 4 (A)] One type of binary data “1” is shown in FIG.
FIG. 6 is a diagram showing a method for writing to a memory cell in the semiconductor memory device shown in FIG.

FIG. 4B is a diagram showing a method of accumulating charges in the ferroelectric capacitor when data “1” is written in the memory cell in the semiconductor memory device shown in FIG. 1.

FIG. 5A is a diagram showing a method of writing another type “0” of binary data to a memory cell in the semiconductor memory device shown in FIG. 1.

FIG. 5B shows that when the subsequent data “0” is written in the memory cell in the semiconductor memory device shown in FIG.
It is a figure which shows the method where an electric charge is stored in a ferroelectric capacitor.

6A is a diagram showing a principle of reading data written in a memory cell in the semiconductor memory device shown in FIG.

FIG. 6 (B) is a graph illustrating the relationship between source-drain current and gate voltage of a MIS transistor that illustrates this principle.

7 is a diagram showing a method of reading data written in a memory cell in the semiconductor memory device shown in FIG.

FIG. 8 is a plan view showing a configuration of a memory cell formed in a semiconductor memory device according to a second embodiment of the present invention.

FIG. 9 is a cross-sectional view taken along line VIII-VIII ′ of FIG.

FIG. 10A is a diagram showing a method of writing one type “1” of binary data to a memory cell of a conventional FeRAM.

FIG. 10B is a diagram showing a method of accumulating charges in the ferroelectric capacitor when the data “1” is written in the memory cell of the conventional FeRAM.

FIG. 11A is a diagram showing a method of writing another type “0” of binary data into a memory cell of a conventional FeRAM.

FIG. 11 (B): The subsequent data “0” is the conventional FeRA.
FIG. 6 is a diagram showing a method of storing charges in a ferroelectric capacitor when writing data in M memory cells.

FIG. 12 illustrates a structure of a memory device in which a ferroelectric material is disposed between an active layer of a transistor and a gate of the transistor.

FIG. 13 is a diagram illustrating a structure of a memory device according to example embodiments.

FIG. 14 is an equivalent circuit diagram of the structure shown in FIG.

FIG. 15 shows waveforms of signals applied in the embodiment of FIG.

16 (a) to 16 (d) show manufacturing steps for manufacturing the second embodiment of the present invention.

FIG. 17 is a diagram showing a general planar layout of a memory device using the structure shown in FIG. 16 (d).

FIG. 18 is a diagram showing an equivalent circuit of a modified example of the second exemplary embodiment of the present invention.

[Explanation of symbols]

1 semiconductor memory device, 1A semiconductor memory device, 2
Insulating substrate, 10 memory cells, 10A memory cells, 2
0 MIS transistor, 20A MIS transistor, 21 gate electrode, 21A gate electrode, 22 source region, 22A source region, 23 drain region,
23A drain region, 24 channel region, 25
Gate insulating film, 26 interlayer insulating film, 30 ferroelectric capacitor, 30A ferroelectric capacitor, 31A electrode,
32A electrode, 35 plate electrode, 36 ferroelectric layer, 37 insulating film, 110 transistor, 112 transistor, 114 capacitor, 116 switch,
200 silicon film, a period, b period, BL1 first bit line, BL2 second bit line, C channel, D drain, E electrode, G gate, G1 partial gate, G2 partial gate, H high level, HH High level, I insulating layer, Ids source / drain current, L Low level, L1 solid line, L2 1 dot-dash line, L3
Dotted line, M metal electrode, PL plate line, PZT lead / zirconate / titanate, S source, Sub substrate, VDD read voltage, Vds drain voltage, Vg
Gate voltage, Vgs Gate voltage, Vgs (Int)
Gate voltage, Vgs0 gate voltage, Vgs1 gate voltage, Vplate plate voltage, Vsub voltage, Vth (0) threshold voltage, Vth (Int) threshold voltage, Vth (1) threshold voltage, WL word line

Continued front page    (72) Inventor Clown Migliolat             UK Cambridge CB2 1SJ 8c               Kings Parade Epson Kenburi             Inside the Institute F-term (reference) 5F083 FR00 FR02 JA14 JA15 JA17                       JA36 LA12 LA16

Claims (15)

[Claims] 1. A plate electrode, a ferroelectric layer, an insulating film, M
A semiconductor memory device including a plurality of memory cells each formed by stacking a channel region of an IS transistor, a gate insulating film of the MIS, and a gate electrode of the MIS transistor in this order. Electrically connected to the gate electrode of each of the memory cells, first and second bit lines electrically connected to a source region and a drain region of the MIS transistor, respectively, and a plate line connected to the plate electrode. A semiconductor memory device that is electrically connected. 2. The semiconductor memory device according to claim 1, wherein the MIS transistor is a thin film transistor. 3. The active layer of the thin film transistor is a low temperature polycrystal silicon film.
A semiconductor memory device according to item. 4. When data is stored in the memory cell, a voltage having a polarity corresponding to the data is applied between the plate line and each of the first and second bit lines, and 4. The semiconductor memory device according to claim 1, wherein a gate voltage for turning on a MIS transistor is applied from the word line to the gate electrode. 5. One of the binary data is stored when one type of the binary data is stored in the memory cell.
A voltage of a polarity corresponding to two types is applied between the plate line and each of the first and second bit lines,
When a gate voltage for turning on the MIS transistor is applied to the gate electrode from the word line and another type of the binary data is stored in the memory cell, the one type of data is stored. Is applied between the plate line and each of the first and second bit lines, and a gate voltage for turning on the MIS transistor is applied. The semiconductor memory device according to claim 1, wherein the word line is applied to the gate electrode. 6. A potential between a first gate voltage and a second gate voltage is applied as a read gate voltage from the word line to the gate electrode when data is read from the memory cell, The gate voltage of 1 is the gate voltage at which the source / drain current reaches a predetermined level according to the source / drain current-gate voltage characteristic of the MIS transistor when one kind of binary data is written to it, The second gate voltage is a gate voltage at which the source / drain current reaches a predetermined value according to the source / drain current-gate voltage characteristic of the MIS transistor when another kind of the binary data is written therein. And the read voltage is M
A source-drain current is applied between the source and the drain of an IS transistor while a voltage approximately equal to the data read gate voltage is applied from the word line to the gate electrode. The semiconductor memory device according to claim 4, wherein the semiconductor memory device is detected from a bit line or the second bit line. 7. An active layer in which a source, a channel, and a drain of a transistor are formed, a gate for the transistor, a layer of a ferroelectric material, and an electrode for applying a voltage to the ferroelectric material, The electrodes are spaced from the gate, and the layer of ferroelectric material has two stable states of internal polarization, which array has a detectable difference in the effect of the two polarization states on the conversion characteristics of the transistor. A semiconductor memory device having: 8. The semiconductor memory device of claim 7, wherein the gate and a layer of ferroelectric material are provided on opposite sides of the active layer. 9. The semiconductor memory device according to claim 7, wherein the gate and the layer of ferroelectric material are provided on the same side of the active layer. 10. The semiconductor memory device according to claim 7, wherein the length of the electrode for the ferroelectric material is shorter than the length of the gate. 11. The gate is divided into two partial gates with a layer of ferroelectric material extending between them.
The semiconductor memory device according to 1. 12. A first insulating layer is formed on the active layer, the gate is formed on the first insulating layer, a second insulating layer is formed on the gate, and the ferroelectric layer is formed. 12. The semiconductor memory device according to claim 9, wherein a layer of a conductive material is formed on the second insulating layer. 13. A semiconductor memory device comprising a matrix of memory cells, each cell being in the form of a device according to any one of claims 7 to 12. 14. The method of manufacturing a semiconductor memory device of claim 7, comprising forming the transistor and then applying a layer of the ferroelectric material. 15. Prior to the step of applying the layer of ferroelectric material, the method further comprises splitting the gate so that the layer of ferroelectric material can be applied between the two partial gates. The method according to claim 14.