JP2003108434A - Memory control device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a memory control device capable of shortening a data transfer time at an excellent cost/performance ratio in a target device. SOLUTION: This memory control device for holding and transferring data is disposed in a computer system having a target 504 receiving a lead command from an initiator 503 as a bus master and transmitting the data to the initiator and a receiving buffer 523 belonging to the target and holding the lead command. The memory control device comprises an address holding buffer 543 holding the address of the data, a lookahead buffer 553 holding the data, and a transfer control device 510 comparing the address of the lead command held in the receiving buffer with the address of the data and, when these addresses are identical to each other, transferring the data in the lookahead buffer to the initiator.

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a processor and a storage device.
Systems such as devices, screen display devices, I / O devices, etc.
The present invention relates to a memory control device in a system, and more particularly to an SDRAM.
Suitable for fast and efficient data transfer to
The present invention relates to a memory controller. [0002] Conventionally, personal computers (PCs)
Microprocessor and memory (noted by
Storage device), screen display device, I / O device, etc.
Computer system (hereinafter simply referred to as system)
)) In order to speed up data transfer.
It is disclosed in Japanese Unexamined Patent Publication No. 2000-132503.
Such as multiple initiators on the target side.
Incorporating a data transfer device with a number of send / receive buffers
This allows an independent bus and data transmission / reception buffer
High-speed execution to speed up the entire system
ing. FIG. 2 shows a typical computer system.
FIG. 3 is a block diagram showing a configuration. As shown in the figure,
The processor 1 is connected via the system controller 2.
SRAM 8, flash memory 9, ROM 10, and
A main storage device including the SDRAM 11 and a
Graphics LSI4 and VRAM5 and peripherals
Controller 3 and bus master DMA controller 22
And the like. The peripheral controller 3
Hard disk, network, keyboard, etc.
Connected to the I / O device 6. FIG. 3 shows a system controller shown in FIG.
FIG. 3 is a block diagram showing an example of the configuration of FIG. As shown in the figure
Next, the system controller 2 connects to the processor 1.
Connected to the processor I / F port 12 and the SDRAM 11
Connected to the SDRAM I / F port 14, the SRAM 8,
Memory I / connected to rush memory 9 and ROM 10
F port 16 and a group connected to the graphics LSI 4
Fixed I / F port 13 and bus master DMA
Bus master DMA controller connected to the controller 22
Port 15 and the peripheral controller 3
Peripheral I / F port 19 and interrupt
And a timer counter 18.
You. Conventionally, VME (Versa Module)
(Europe) bus, PCI (Peripheral)
Components Interconnect
Bus, ISA (Industry Standard)
Architecture) buses and other local
In a bus, one device occupies the bus
That is, it becomes a bus master) and transfers data. these
Initiator on other bus (Issues instructions to other devices
That are controlled by the initiator
), Processor, memory (storage device), screen
A display device, an I / O device, etc. are connected to
Data system. On these buses, two at the same time
The above devices may request the occupation of the bus. So
In this case, the right to use the bus is determined by an arbitration circuit or the like. So
And the licensed device occupies the bus at that moment.
(Ie, become a bus master) and perform data transfer.
U. In particular, in a PCI bus, a bus bridge architecture is used.
Another that holds the architecture and is separated by a bridge
Perform concurrent data transfer on various buses
It is possible to do. But usually on the buses mentioned above
Is one device at a moment in data transfer
Only occupy the bus, other devices wait
become. FIG. 4 shows a system controller shown in FIG.
FIG. 4 is a diagram showing an example of a data flow in the embodiment. Process
I / F controller 20 and bus master DMA controller
The roller 22 has only an initiator function. Also,
Memory I / F controller 23, SDRAM I / F controller
Troller 24 and graphics I / F controller 2
5 has only a target function. Peripheral I /
The F controller 21 has an initiator function and a target
Has both functions. [0008] As shown in FIG.
Controller 21, memory I / F controller 23, SD
RAM I / F controller 24 and graphics I / F
The F controller 25 has a reception buffer (FIF
O) 51, 53, 54 and 55 are provided. And each
The reception buffer 51, 53, 54 or 55 is a peripheral
I / F controller 21, Memory I / F controller
23, SDRAM I / F controller 24 or graphics
Command transmitted to the controller I / F controller 25,
Holds data etc. However, two or more initiators
These requests transfer data to the target on the bus.
The initiator's right to use the bus.
The bus master device is determined by the network. This and
Initiator that failed to acquire the right to use
Initiator (that is, the bus master) that has acquired
Data transfer is completed. That is,
The initiator that cannot acquire the right to use the bus
Processing (data transfer) cannot be performed, and the execution time (bus
Transactions). In addition, the system
Performing an erase memory access transfer (DMA transfer)
The processor cannot own the bus during the
You will have to wait for access. On the other hand, a computer as shown in FIG.
Data system, every transaction
By handling data transfer efficiently, each initiator
There is an apparatus for improving the throughput on the
Hei 2000-132503). FIG. 5 shows a conventional computer system.
Device with a bus master function (initiator
Initiator) by the write command issued by the
Flow when data is transferred from the target to the target
FIG. For convenience, processor I / F controller
, Peripheral I / F controller 21 and bus
The master DMA controller 22 has a bus master function.
That are listed (that is, become initiators)
I have. The memory I / F controller 23, SD
RAM I / F controller 24 and graphics I / F
The F controller 25 has no bus master function (that is,
Target). Also, the memory I / F controller 23
Is data from the processor I / F controller 20 only.
Is not transferred. Therefore,
Communication buffer is connected to the processor I / F controller 20
Only the receiving buffer (FIFO) 26 is used. Toko
However, the SDRAM I / F controller 24
Controller I / F controller 20, peripheral I / F controller
Controller 21 and bus master DMA controller 22
Since data is transferred from each, each initiator
Each receiving buffer 27, 28 and 29 is provided. Also,
Similarly, the graphics I / F controller 25
Buffers 30, 31, and 32. Peripheral I /
The F controller 21 includes a processor I / F controller.
From the bus controller 20 and the bus master DMA controller 22.
Since the data is transferred, the two reception buffers 33 and 34
Is provided. [0013] In the reception buffer, the initiator
Enter command and data. For example, processor I / F
The controller 20 becomes an initiator and the SDRAM /
If the F controller 24 is targeted,
Receive buffer 27 from Sessa I / F controller 20
Then, a write command and data are input. Light frame
The posted light method is adopted as the command. Bath
Receive buffers 26 to 34
It is necessary to provide a capacity of 2W, 4W, 8W,. The data flow is as indicated by the arrow in FIG.
It is. For example, the target SDRAM I / F
The controller 24 includes a processor I / F controller
From the peripheral 20 via the reception buffer 27,
From the I / F controller 21 via the reception buffer 28
The bus master DMA controller 22
Each data is transferred via the buffer 29.
The controller 42 decodes the write command, and
Buffer 27, 28, 29 received data at the same time
Including SDRAM I / F controller 24
Determine the output priority and output. Data is transferred from a plurality of initiators.
Graphics I / F Controller 25 and Peripheral
The Ral I / F controller 21 has the same configuration.
You. In other words, the target receives
Initiator allows the initiator to
Immediately after transferring commands and data to the receive buffer
The initiator can start the next operation.
Data processing can be performed efficiently. FIG. 6 shows a conventional computer system.
Device with a bus master function (initiator
Target) depending on the read command issued by
Of data when data is transferred from the server to the initiator
FIG. As shown in the figure, the target
Memory I / F controller 23, SDRAM I / F controller
Troller 24 and graphics I / F controller 2
5, three initiators (processor I
/ F controller 20, peripheral I / F controller
Controller 21 and the bus master DMA controller 22).
Mode command is transferred, the corresponding data is fetched,
Transfer to initiator. Perife as target
For the Ral I / F controller 21, the processor I
/ F controller 20 and bus master DMA controller
Becomes the initiator. For example, an SDRAM I / F controller 2
4 is explained. Processor I / F Controller
The read command transferred from the receiving buffer (F)
I / F) 110, and the peripheral I / F controller
The read command transferred from the roller 21 is
Input to the bus master DMA controller
The read command transferred from the
Is forced. Stored in receive buffers 110, 111, 111
The read command is decoded by the controller 109.
And the priority of the output order is determined.
From the receiving buffers 110, 111, 112 according to
Mode command is issued to the SDRAM I / F controller 24.
And the data corresponding to the read command is read.
You. With the read data, the processor I / F control
What is to be transferred to the
Output via the peripheral I / F controller
21 are transmitted to the transmission buffer 114.
Output from the bus master DMA controller 2
2 should be transferred to the transmission buffer 115
Is output. Similarly, the memory I / F controller 23,
Graphics I / F controller 25 and peripheral
In the I / F controller 21, the corresponding
Receive buffer that receives read commands for each eta
And send the data specified by the read command
A buffer is provided. About data flow
Is as indicated by the arrow in FIG. The target transmits a buffer for each initiator.
By providing a target, the target
The next operation cycle immediately after transferring the data
The target is efficient
Can be processed. Next, the conventional interface port
An outline will be described. FIG. 7 shows a conventional computer system.
Device that has only slave functions
FIG. 2 is a block diagram illustrating an outline of a port. Inter
The face port 200 has only a slave function.
In other words, it becomes a target, but not an initiator.
I) Connect to device 510. For example, as shown in FIG.
SRAM 8, flash memory 9, ROM 10, SDR
Connect to AM11. Also, interface port 2
00 is a read command or write command issued by the initiator.
It has a flow of data transfer for the command. Receiving bar
Buffer (FIFO) 211, 212, 213
Light command sent from Eta (not shown)
Data, address, data, etc., and write control
To the client 206. Receive buffers 219, 220, 2
21 is the read command sent from the initiator
Data, address, etc., and transfer them to the read controller
I do. Transmission buffers (FIFO) 216, 217, 21
8 is requested to the initiator by that initiator.
Transfer the data. The light controller 206 controls
Receiving buffers 211, 212, and 213 via the
Control. Read controller 207 is a control
Transmission buffers 216, 217, and 218
To the receiving buffer 219,
220 and 221 are respectively controlled. Light control
Priority of roller 206 and read controller 207
The position is the interface port bus arbiter (ie
(Stop circuit) 204 is determined. Arbitration method is fixed priority
Type, round robin type, single level type, etc.
Yes, they can be combined, and throughput is improved
Settings can be changed as follows. Furthermore, an initiator having a bus master function
Overview of interface ports connected to data devices
explain. FIG. 8 shows a conventional computer system.
Connected to an initiator device having a master function.
FIG. 2 is a block diagram showing an outline of an interface port.
You. The interface port 300 is a slave function
However, to provide the bus master function, the address and
Read / write commands are sent to the interface
Has a function to issue to a port (not shown).
Is that the interface port 200 shown in FIG.
different. Bus master read controller 306
Sends a read command via the controller 314
Transmission buffers (FIFO) 311, 312, 313
To receive data via the controller 318.
Receive buffer (Through Buffer) 31
5,316,317. Bus Master Write
Transmission for write command transmission by the controller 307
Control the communication buffers (FIFO) 319, 320, 321
I do. For example, a write command is issued from the device 301.
The external controller 305, the bus master
Write controller 307 and transmission buffer 319
Therefore, the I / F port of the target to which the command is transferred is
The command is transferred to the receiving buffer 326 of the host. Similarly, a read command is issued. each
The priority of the controllers (206 and 207) is
Face port bus arbiter (ie, arbitration circuit) 20
4 is determined. The arbitration method is fixed priority, round ro
Bin method, single level method, etc. can be adopted, and combinations are also possible
Settings can be changed to improve throughput. [0025] By the way, as described above,
A computer with multiple initiators.
Data processing in computer systems.
However, in computer systems, data processing time
There is a problem that shortening is always required. to this
Are, for example, memory caches and buffers corresponding to each memory.
By providing a cache, especially read commands
To improve data read speed
However, these large caches are expensive,
There is a problem that the improvement of the degree is not remarkable. Therefore, the present invention solves the above-mentioned problem, and
Target device to reduce data transfer time
To provide a memory control device that can perform well in top performance
It is intended for that purpose. [0027] In order to achieve the above object,
As means of the present invention, the memory controller of the present invention
Initiator (peripheral controller 50)
1, DMA controller 502, microprocessor 5
03) and a read command is received from the initiator.
And a target for transmitting data to the initiator.
(SDRAM I / F controller 504)
A receiver belonging to a target and holding the read command.
Communication buffer (command reception buffers 521, 522, 5
23).
A memory controller for holding and transferring the data.
Address holding buffer for holding the address of the data.
Files 541, 542, and 543 and the data is held.
The prefetch buffers 551, 552, 553 and the reception buffer
Address of the read command held in the buffer
Compare with the address of the data, and if they match,
Transfer the data in the read-ahead buffer to the initiator
If they do not match, the target
Transfer controller that transfers the data specified by the command
(With an address decode controller 510).
A memory control device characterized by the following. Embodiments of the present invention will be described below.
Preferred embodiments will be described with reference to the drawings. <Embodiment> FIG. 1 shows an embodiment of a memory control device according to the present invention.
FIG. Memory control device 500 of the present embodiment
Can be integrated into the conventional computer system described above.
For example, a 32-bit microprocessor,
32 bit bus system memory, screen display
And I / O devices, and each block is connected efficiently
And posted data to enable high-speed data transfer.
Transmit / receive buffer corresponding to write / read command method
Target device in a system equipped with
And connect the read-ahead memory buffer to each
This is provided for each port of the initiator. As shown in FIG. 1, a memory control device 500
Is a peripheral controller 50 serving as an initiator.
1. DMA controller 502 and microprocessor
503, system controller and SDR not shown
Connected via AMI / F port, target
Is SDRAM I / F control
Connected via a printer 504. Here, SDRAM5
05 is a two-way interleave method for speeding up.
The bus width shall be 64 bits (address
Command + odd / even bank + odd / even bank ...)
It is assumed that For convenience, a 32-bit microprocessor
Processor, 32-bit system bus (bus structure in chip)
), The interface of the SDRAM 505
The description will be made assuming that the interleaving is used. 2 way
The interleave bank has the lowest address as 8 words.
Unit that can carry Here, one word is 4 bytes
You. The memory control device 500 includes a reception buffer 5
11, 512, 513, the command reception buffer 521,
522, 523, transmission buffers 531, 532, 53
3. Address holding buffers 541, 542, 543,
Dress decode controller 510 and look-ahead buffer
551, 552, and 553. Receive buffer
521, reception buffer 522, reception buffer 523
Is the peripheral controller (bus master) 501
From the DMA controller 502, the microprocessor
Read or write command from server 503
For example, from a FIFO with a capacity of 8 W
Be composed. The receiving buffer 511 and the receiving buffer 51
2. The reception buffer 513 is a peripheral controller
(Bus master) 501 to the DMA controller 502
From the microprocessor 503, from the write command
Receive the write data when the
For example, it is composed of an 8 W FIFO. Receiving
The write data stored in the buffers 511, 512, 513
Data is output to the SDRAM I / F interface 504.
And written to the SDRAM 505. Transmission buffer 531, transmission buffer 53
2. The transmission buffer 533 is a peripheral controller
(Bus master) 501 to the DMA controller 502
Read command from microprocessor 503
Is issued, the SDRAM I / F interface 5
Read from the SDRAM 505 via the IP address 04
Each of them temporarily stores data, for example, 8W
Is configured. A look-ahead buffer for storing SDRAM data
551, 552, 553 are provided.
Correspondingly, address holding buffers 541, 542, 54
3 are provided. The look-ahead buffer is the receive buffer
Having a capacity of twice or more (in this case, 16 W) the capacity of
It is composed of an IFO and has an address decode control.
And the receiving buffers 511 and 51
Can store data from any of 2,513
It is configured to be able to. Address holding buffer 5
41, 542, and 543 include prefetch buffers 551 and 551, respectively.
The address of the data stored at 52,553 is
Address decode controller 5
10 updates and references the address. The address decode controller 510 includes:
Connected to the SDRAM I / F controller 504
Stored in the reception buffers 511, 512, and 513.
Outputting data to SDRAM I / F controller
Control, and read-ahead buffers 551, 552, 553
To the receiving buffers 511, 512, 5
13 of the SDRAM 505.
Write data to prefetch buffers 551, 552, 553
Data of the prefetch buffers 551, 552, and 553.
Data in the transmission buffers 531, 532 and 533.
You. Write command from initiator device
Is issued, the write address and write data
Comment (write size [1 byte, 2 bytes, 4 bytes
Etc.) and data identifier).
File 521 (or 522 or 523).
You. Then, the write data is transferred to the corresponding reception buffer 511.
(Or 512 or 513). Read command from initiator device
Is issued, the read address, read data element
Comment (read size [1 byte, 2 bytes, 4 bytes
Command, etc.) and data identifier)
Buffer 521 (or 522 or 523)
To pay. And the corresponding initiator device is read
The transmission buffer 531 (or 532) to which the data corresponds.
Or wait until it is stored in 533). The address decode controller 510 includes:
Command reception corresponding to the initiator according to the priority
Select one of the buffers 521, 522, 523
To read and decode the command,
Write command, and if it is a read command,
Dress is 2-way interleaved, odd-numbered bank or even-numbered
Identify the bank. As an arbitration method to determine priority
Means fixed priority, land robin, single level
Method, combinations of them and variable priority levels
Shall be able to Here, if the address is an odd-numbered bank,
The corresponding read-ahead buffer 551 of the initiator (or
Stores the address of 552 or 553)
The address holding buffer 541 (or 542 or
543) and the address of the read command are compared.
You. If the addresses do not match, the SDRAMI
/ F controller 504 stores the address data in SDR
Odd / even van with 2-way interleaving from AM505
Data in the odd bank.
The corresponding transmit buffer 531 (or 532 or
533) and store the data.
Discarded. If the addresses match, the prefetch buffer 5
51 (or 552 or 553)
Data to the transmission buffer 531 (or 532 or
Is output to 533) and stored. On the other hand, if the address is an even bank, S
The DRAM I / F controller 504 is an SDRAM 505
From the odd address corresponding to the address by 2-way interleaving.
Read the data of the even / even bank and read the even bank
Data of the transmission buffer 531 (or 532
Or 533), and stores the data in the odd-numbered bank.
The corresponding read-ahead buffer 551 of the initiator (or
Are stored in 552 or 553) and correspond at the same time.
Initiator address holding buffer 541 (or
542 or 543), the address decode control
The prefetched address is stored via the memory controller. If the decoded command is a write command
If the address is an odd-numbered bank with 2-way interleaving,
And even banks. Where the address is odd
If it is a bank, this address and the address holding buffer
541, an address holding buffer 542, an address holding buffer
Compared to the contents of the
If there is a dress, its address holding buffer 541 (A
Or a look-ahead buffer corresponding to 542 or 543)
551 (or 552 or 553) data
Into the reception buffer 511 (or 512 or 51
Update with the data received and stored in 3). This and
Address matches the contents of multiple address holding buffers.
If they match, the data in all of those read-ahead buffers is received.
Update with the data in the communication buffer. At the same time, SDRAMI
/ SD controller 505 through / F controller 504
The data is stored and rewritten to the corresponding address of. The address and address holding buffer 5
41, an address holding buffer 542, and an address holding buffer.
Compare with the contents of each
For example, through the SDRAM I / F controller 504
And write data to the address of the SDRAM 505
Replace it. If the address is an even bank, SDRAM
Applicable SDRAM through I / F controller 504
The data is stored and rewritten to the address 505. Here, the computer system is cold
In reset or system reset state, all
Address holding buffers 541, 542, 543 are empty.
Configure to be in a state (flag empty
). Furthermore, prefetch buffers 551, 552, 553
If there is an instruction to empty the
The address holding buffer corresponding to the
To Further, in the memory control device 500,
The address holding buffer 541 (or 542 or
543) is empty, the address decode
The controller 510 is configured not to compare addresses.
Thus, the processing speed is increased and the circuit is simplified. The address holding buffer 541 (or 5
42 or 543) is empty, that is, the corresponding look-ahead buffer
If fa 551 (or 552 or 553) is empty
And the corresponding initiator issues a write command
If the address is an odd bank address,
If the initiator's prefetch buffer 551 (or
Stores data in 552 or 553) and stores the address
Holding buffer 541 (or 542 or 543)
To store the address. At the same time, SDRAM I / F
The corresponding address of the SDRAM 505 through the controller 504.
Store the data in the dress. In addition, here, other initiers
And the contents of the address holding buffer corresponding to the data
And if they are the same address,
Update the data of the web. As described above, the memory control device of the present embodiment
Configures a prefetch buffer from registers that are high-speed memories.
Data of the target SDRAM in advance.
Data is read, and a read command is issued from the initiator.
Is issued, the read data is stored in the prefetch buffer.
If it is acceptable, do not access the SDRAM.
To send data from the prefetch buffer to the initiator.
The data processing speed has been improved. The highest memory access speed is the highest.
SRAM, SDRAM, DRAM, RO
M slows down in the order of M, and the register
It can be taken out, but SRAM etc. give an address and read
Data reading requires more than one clock.
Need more time. Also, if the data is sequential
Since it has been ordered, its characteristics are
The memory controller is used. That is, the instruction
Access to applications and data is usually built into the CPU
A certain block is continuously
Often, so in the case of interleaving,
In particular, the effect of hitting the contents of the prefetch buffer is large.
No. Hereinafter, more specifically, the memory control device
The operation will be described. First, a system reset (
Peripheral reset)
Controller address holding buffer 541, DMA controller
And an address holding buffer 542 for the controller.
To the address holding buffer 543 for the microprocessor.
Set an empty flag each time to make it empty. Next, the microphone
From processor 503 to address 0xXXXXXX0000.
If there is read access to the dress for 8 words,
Since there are several banks, the SDRAM I / F controller 5
04, 0xXXXX000 of the SDRAM 505
Data from 0 to 0xXXXXXX001F is
The data is transferred to the transmission buffer 533 for the processor 503. simultaneous
0xXXXXXX0020 to 0xxXX of the SDRAM 505
XX003F data for the microprocessor 503
Stored in the look-ahead buffer 553, the microprocessor 5
0xXXXXXX0 in the address holding buffer 543 for
020 is stored. Next, the microprocessors 503 to 0x
Reads the address at address XXXX0020 for 8 words
If there is access, it is an odd bank, so the microphone
Of the address holding buffer 543 for the
Compare the contents with 0xXXXXXX0020. This value is
The read-ahead buffer for the microprocessor 503.
Of the file 553 for the microprocessor 503.
Transfer to the communication buffer 533. Next, the microprocessor
The address of address 0xXXXXXX0040 is set to 8
If there is read access for words,
Through the SDRAM I / F controller 504
0xXXXXXX0040 to 0xXXXX0 of the SDRAM
Send data up to 05F for microprocessor 503
Transfer to the communication buffer 533. At the same time, SDRAM 0x
XXXX0060 to 0xXXXXXX007F data
A prefetch buffer 553 for the microprocessor 503
And an address holding buffer for the microprocessor 503.
0xXXXXXX0060 is stored in the buffer 543. Next, the microprocessors 503 to 0x
Reads the address of XXXX00A0 for 8 words
If there is an access, it is an odd-numbered bank.
SDRAM 50 through AMI / F controller 504
5 from 0xXXX00A0 to 0xxxx00BF
Data is transferred to the transmission buffer 533 of the microprocessor.
Send. Because SDRAM 505 is interleaved
Data of 0xXXXXXX0080 to 0xXXXXXX09F
Throw away. Next, 0xx from the microprocessor 503
Read address of xx00C0 address for 8 words
If there is access, the SDRAM
SDRAM 505 through I / F controller 504
Data from 0xXXX00C0 to 0xXXXX00DF
Data to the transmission buffer 533 of the microprocessor 503.
Transfer to At the same time, 0xXXXXXX0 of SDRAM 505
0E0-0xXXXX00FF
Stored in the look-ahead buffer 553 for the processor 503, and
Address holding buffer 5 for microprocessor 503
43, 0xXXXXXX00E0 is stored. Note that these processes are not performed in units of eight words.
4 words, 2 words, 1 word, 2 bytes, 1 byte
The same behavior is performed even in read units of
To return the required data element to the
Here, the microprocessor 503 sends 0xXXXXXX0
If there is a write access to 0E8, an odd bank
Address holding for the peripheral controller 501
Buffer 541, address for DMA controller 502
Buffer 542 for the microprocessor 503
Each is stored in the address holding buffer 543.
Compare with address. In this case, the microprocessor 5
03 is 0xXXXXXX0
0E0 to 0xXXXXXX00FF
0xXXX00E8. Hit
When reading, the data of the corresponding prefetch buffer 553
Update part to that data, keep other data
To do. At the same time, SDRAM I / F controller 50
4 through 0xXXXX00E8 of the SDRAM 505
Store data at the address. About the part that does not hit
Data. Next, the microprocessor 503 outputs 0x
If there is a write access to XXXX0100, an even address is added.
SDRAM I / F controller 504
Through 0xXXXXXX0100 of SDRAM
It just stores the data. Thus each address
The addresses indicated by the holding buffers 541, 542, 543
If no hit occurs, the SDRAM I / F controller 50
4 to the SDRAM 505 at that address.
Just store. DMA controller 502 or
Is about data transfer from peripheral controller
Is performed similarly to the microprocessor. In addition,
Address decode controller
By the roller 510 (which becomes an arbitration circuit),
Select the initiator and perform its processing as described above.
Just do it. As described above, the prefetch buffer and the address holding buffer
Explains the case where a buffer is provided for each initiator device
However, more read-ahead buffers and address holding buffers
(For example, 3 times, 5 times, etc.)
Data processing system performance)
You can also. In this embodiment, the SDRAM
Although the description has been given of the case where the
The same applies to OM and flash memory.
It can be. In these cases, writing data
Since there is no such part, that part may be deleted. Also Perif
For I / O devices such as general controllers
Address when accessing I / O space (indirect register, etc.)
Control to empty the holding buffer by software
That I / O data is sequential data
If it is a memory space, it can be configured with the same system as described above.
Needless to say. As described above, the memory system of the present invention
The control device has an address holding buffer for holding the data address.
Buffer, a look-ahead buffer for holding the data, and a receiving buffer.
Address of the read command held in the
Compare with the address of the data, and if they match,
Transfer the data in the read-ahead buffer to the initiator
If they do not match, the target
Transfer controller that transfers the data specified by the command
And by providing in the target device
Reduce data transfer time with good cost performance
There is an effect that a memory control device can be provided. Further
With system cache and memory cache
High-speed response without the need for
The system saves space and costs,
Excellent responsiveness of sequential access, bus data transfer
There are few penalties in the pipeline at the time, I / O device
In the chair, I / O space (indirect register etc.)
Control to empty the address holding buffer during
It can be easily handled by using hardware.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a configuration diagram showing an embodiment of a memory control device of the present invention. FIG. 2 is a block diagram illustrating a configuration of a typical computer system. FIG. 3 is a block diagram illustrating an example of a configuration of a system controller illustrated in FIG. 2; 4 is a diagram showing an example of a data flow in the system controller shown in FIG. FIG. 5 is a diagram showing a data flow when data is transferred from an initiator to a target by a write command issued by a device (initiator) having a bus master function in a conventional computer system. FIG. 6 is a diagram showing a data flow when data is transferred from a target to an initiator by a read command issued by a device (initiator) having a bus master function in a conventional computer system. FIG. 7 is a block diagram showing an outline of an interface port of a device having only a slave function in a conventional computer system. FIG. 8 is a block diagram showing an outline of an interface port connected to an initiator device having a master function in a conventional computer system. [Description of Signs] 1 ... Processor, 2 ... System Controller, 3 ... Peripheral Controller, 4 ... Graphics LSI, 5
... VRAM, 6 ... I / O device, 8 ... SRAM, 9 ...
Flash memory, 10 ROM, 11 SDRAM,
22: Bus master DMA controller, 500: Memory controller, 501: Peripheral controller, 502
... DMA controller, 503 ... Microprocessor,
504 SDRAM interface (I / F) controller, 505 SDRAM, 510 address decode controller, 511, 512, 513 reception buffer, 521, 522, 523 command reception buffer
531, 532, 533... Transmission buffer, 541, 54
2,543 ... address holding buffer, 551, 552
553: Look-ahead buffer.

Claims (1)

Claims: 1. An initiator serving as a bus master, a target receiving a read command from the initiator and transmitting data to the initiator, and a receiving buffer belonging to the target and holding the read command. A memory control device that is arranged in a computer system including: an address holding buffer that holds and transfers the data; an address holding buffer that holds an address of the data; a prefetch buffer that holds the data; and a holding buffer that holds the data. The address of the read command is compared with the address of the data, and if they match, the data in the pre-read buffer is transferred to the initiator, and if they do not match, the address is designated by the read command from the target. Transfer the transferred data A memory control device comprising: a control device.