JP2003101487A - Device and method for processing synchronization - Google Patents

Abstract

PROBLEM TO BE SOLVED: To synchronize a digital sound signal coming from an outer part with an internal clock signal without deteriorating quality. SOLUTION: A synchronization processor is provided with a FIFO memory 23, a reading control part 24 and a sampling rate converter 26 and, then, a digital sound signal extracted from an SDI signal from the outside of a station by a sound signal extracting part 21 is written in the FIFO memory 23. The reading control part 24 reads the digital sound signal written in the FIFO memory 23 by a reading timing which is generated from the intra-station clock signal generated by a clock generating part 25 and from video connecting information. The sampling rate converter 26 re-samples the digital sound signal read from the FIFO memory 23 by a frequency rate which is synchronized with the intra-station clock signal generated by the clock generating part 25.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital broadcast signal transmission system for handling a multiplex signal, which is obtained by externally multiplexing a digital video signal and a digital audio signal having a transmission block structure of a predetermined data length unit, and more particularly to a multiplex signal. The present invention relates to a synchronization processing device and a synchronization processing method for extracting a digital audio signal from a digital audio signal and synchronizing the digital audio signal with a clock signal handled by a digital broadcast signal transmission system.

[0002]

2. Description of the Related Art In a broadcasting station of a digital broadcasting system, an SDI (Serial Dig) in which material data (video data and audio data) of a digital broadcasting program handled in the station is multiplexed.
In addition to ital interface) signals, SDI signals outside the office are also handled.

FIG. 6 shows an SDI from outside the station within the broadcasting station.
It is a block diagram which shows the structure of the signal processing apparatus which processes a signal.

The SDI signal coming from outside the station is first inputted to the voice signal extraction section 11 and the clock generation section 12.
Of these, the clock generator 12 generates a clock signal in synchronization with the input SDI signal. Audio signal extraction unit 1
Reference numeral 1 is an extraction timing synchronized with the clock signal generated by the clock generator 12, and extracts the digital audio signal multiplexed into the SDI signal. The extracted digital audio signal is converted by the D / A converter (D / A) 13 into
It is converted into an analog audio signal at a timing synchronized with the clock signal generated by the clock generator 12, and the A / D
It is input to the conversion unit 14.

The A / D converter 14 includes a clock generator 15
An analog audio signal is converted into a digital audio signal according to a clock signal that is synchronized with the in-station synchronization signal generated from the. After that, the digital audio signal is transferred to the audio signal multiplexing unit 16
Re-multiplexes into the SDI signal synchronized with the synchronization signal in the station.

On the other hand, the SDI signal from the outside of the office is input to the video signal extraction section 17 and a digital video signal is extracted. The digital video signal is written in the video signal combining unit 18 at a write timing synchronized with the clock signal generated by the clock generation unit 12 and read at a read timing synchronized with the clock signal generated by the clock generation unit 15. As a result, it is converted into a digital video signal synchronized with the clock signal in the station and output as an SDI signal to the audio signal multiplexer 16.

[0007]

By the way, in the above signal processing device, in order to synchronize the digital voice signal outside the station with the clock of the own station, the digital voice signal outside the station is once converted into an analog voice signal, After that, since it is converted into a digital audio signal synchronized with the clock signal of its own station (internal), the quality of the digital audio signal is deteriorated.

Therefore, an object of the present invention is to provide a synchronous processing device and a synchronous processing method capable of processing a digital material signal coming from the outside in synchronization with an internal clock signal without causing quality deterioration. To provide.

[0009]

In order to achieve the above-mentioned object, a synchronous processing device according to the present invention is constructed as follows. (1) Digital broadcasting that handles a multiplex signal that comes from the outside and that multiplexes a first digital material signal such as a digital video signal having a transmission block structure of a predetermined data length unit and a second digital material signal such as a digital audio signal. A clock signal applied to a signal transmission system, extracting a second digital material signal from a multiplex signal, synchronizing the second digital material signal with a clock signal handled by the digital broadcast signal transmission system, and handling the clock signal by the digital broadcast signal transmission system. A synchronization processing device for re-multiplexing the first digital material signal synchronized with the first digital material signal, the storage means storing the second digital material signal extracted from the multiplex signal, and the first digital material signal separately provided. At the read timing generated from the coupling information and the clock signal of And a resampling processing means for resampling the second digital material signal read from the storage means by the reading control means at a frequency rate synchronized with the clock signal. It is the one.

According to the above configuration (1), the digital audio signal extracted from the multiplexed signal from the outside is taken in and stored in the storage means. Then, the digital audio signal stored in the storage means is read at the read timing generated from the combined information of the clock signal of the digital broadcast signal transmission system and the first digital material signal, and the frequency synchronized with the clock signal thereafter. It will be resampled at the rate.

Therefore, in order to synchronize a digital audio signal from the outside with an internal clock signal, an A / D converter for converting the digital audio signal into an analog audio signal and this analog audio signal are synchronized with the internal clock signal. It is not necessary to prepare a D / A converter for converting into a digital audio signal, and a digital audio signal from the outside is processed in synchronization with an internal clock signal by digital processing by the storage means, the sampling processing means and the read control means. Therefore, it is possible to provide a relatively small and inexpensive device without causing quality deterioration or discontinuity in the digital audio signal and without using the A / D converter and the D / A converter. it can.

(2) The read control means of the above (1) is stored in the storage means at a read timing smaller than the reference clock number synchronized with the transmission block of the clock signal by a predetermined number when the digital video signal is missing. The digital audio signal reading function is provided.

According to the configuration (2), when the frequency of the external digital video signal is lower than that of the digital video signal in the own system, the digital video signal in the own system has a missing image at regular intervals. Since the same video as before loss is inserted to complement this, the digital audio signal stored in the storage means is read at a predetermined timing less than the number of reference clocks synchronized with the clock signal transmission block. By reading out, the missing portion of the image is offset. Therefore, if the number of clocks of the clock signal is controlled so as to complement the loss, it is possible to synchronously reproduce the digital audio signal without any discomfort even if the digital video signal is lost.

(3) The read control means of the above (1) is stored in the storage means at a read timing that is a predetermined number larger than the number of clocks synchronized with the transmission block of the clock signal when the interlacing occurs in the digital video signal. The digital audio signal reading function is provided.

According to the configuration (3), when the frequency of the external digital video signal is higher than the frequency of the digital video signal in the own system, the digital video signal in the own system is periodically added to the outside video. However, since the digital audio signal stored in the storage means is read at a read timing that is a predetermined number greater than the number of reference clocks synchronized with the clock signal transmission block, the skipped portion of the video is canceled out. I am trying to do it.
Therefore, if the number of clocks of the clock signal is controlled so as to complement the interlace, it is possible to synchronously reproduce the digital audio signal which does not cause any discomfort even if the interlaced digital video signal is generated.

[0016]

BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of a synchronization processing device according to the present invention.

As shown in FIG. 1, the synchronous processing device includes an audio signal extracting section 21, a clock generating section 22, and a FIFO.
(First In First Out) memory (FIFO) 23, read controller 24, clock generator 25, sampling rate converter 26, audio signal multiplexer 27, video signal extractor 28, video signal combiner 29. It has and.

The SDI signal coming from the outside of the station is first inputted to the voice signal extracting section 21 and the clock generating section 22.
Of these, the clock generator 22 generates a clock signal in synchronization with the input SDI signal. Audio signal extraction unit 2
Reference numeral 1 is an extraction timing synchronized with the clock signal generated by the clock generator 22, and extracts the digital audio signal multiplexed into the SDI signal. The extracted digital audio signal is written in the FIFO memory 23 at the timing synchronized with the clock signal generated by the clock generator 22.

The digital audio signal written in the FIFO memory 23 is read by the read control unit 24 by the internal (intra-station) clock signal generated by the clock generating unit 25 and the read timing generated by the separately provided video combination information. Is read out and input to the sampling rate converter 26. The internal clock signal is generated by the clock generator 25 from the internal synchronization signal.

The sampling rate converter 26 has an F
The digital audio signal read from the IFO memory 23 is resampled at a frequency rate synchronized with the internal clock signal generated by the clock generator 25.

Thereafter, the sampling rate converter 26
The digital audio signal sampled by the SD is synchronized with the in-station synchronization signal by the audio signal multiplexing unit 27.
Re-multiplex into I signal.

On the other hand, the SDI signal from the outside of the station is input to the video signal extraction section 28 and a digital video signal is extracted. The digital video signal is written in the video signal combining unit 29 at a write timing synchronized with the clock signal generated by the clock generation unit 22 and read at a read timing synchronized with the clock signal generated by the clock generation unit 25. As a result, it is converted into a digital video signal synchronized with the clock signal in the station, and is output to the audio signal multiplexing unit 27 as an SDI signal.

Next, the operation of the above configuration will be described. First, in order to synchronize the external digital audio signal with the internal clock signal, the audio signal extracting unit 21 extracts the digital audio signal from the external SDI signal, and the clock signal generated by the clock generating unit 22 is synchronized with the SDI signal. The extracted digital audio signal is written in the FIFO memory 23 according to the signal.

The digital audio signal written in the FIFO memory 23 is read by the read controller 24 at the read timing generated from the clock signal in the station and the video combination information, and written in the sampling rate converter 26 at the same clock as the read timing. Be done.

The sampling rate converter 26 has an F
The digital audio signal read from the IFO memory 23 is resampled at a frequency rate synchronized with the internal clock signal generated by the clock generator 25.

Here, when the frequency of the synchronization signal outside the station is lower than the frequency of the synchronization signal inside the station, the digital video signal inside the station is lost in a frame or field unit at every constant period, and thus is lost. The same video as before is inserted and complemented. FIG. 2 shows the reading process of the reading control unit 24 in this case.

In FIG. 2, N, N + 1, ... Are frames of the digital video signal, and R is the reference clock number (reference frequency) synchronized with the frame of the clock signal by the read controller 24.

Here, the read control section 24 reads the digital audio signal from the FIFO memory 23 with a clock having a frequency lower than the reference frequency (with a longer period) in order to cancel out the video loss, and Write to the sampling rate converter 26 with the same clock. Then, at a certain time (when the audio complement is completed), the clock for reading the digital audio signal from the FIFO memory 23 and the clock for writing to the sampling rate converter 26 return to the reference frequency.

For example, assuming that the reference clock number of the digital audio signal synchronized with the video unit frame is R, the digital audio signal from the FIFO memory 23 per video unit frame is sent at the time when it is notified that the video is lost. When the number of clocks to be read is R-α, it takes R / α frame periods to compensate for the missing image. It should be noted that α is a value that can be arbitrarily set so that the missing portion can be complemented.

On the other hand, when the frequency of the synchronization signal outside the station is higher than the frequency of the synchronization signal inside the station, the digital image signal within the station has a section where the image outside the station cannot be used in units of frames or fields at regular intervals ( (Jump) occurs. The state of the reading process of the reading control unit 24 in this case is shown in FIG.
Shown in.

Here, the read control section 24 reads the digital audio signal from the FIFO memory 23 with a clock having a frequency higher than the reference frequency (shortening the cycle) in order to cancel the skipped portion of the video, and Write to the sampling rate converter 26 with the same clock. Then, at a certain time (when the voice complement is completed), the FI
The clock for reading the digital audio signal from the FO memory 23 and the clock for writing to the sampling rate converter 26 return to the reference frequency.

For example, assuming that the reference clock number of the digital audio signal synchronized with the video unit frame is R, the digital audio signal from the FIFO memory 23 per video unit frame is sent at the time when it is notified that the video jump has occurred. When the number of clocks to be read is R + α, the interlaced portion of the image is complemented by taking R / α frame periods.

As a result, it is possible to realize the synchronous reproduction of the audio although it takes a certain fixed time to complete the audio complement.

As described above, in the above embodiment, instead of the A / D converter and the D / A converter, the FIFO memory 23,
Read control unit 24 and sampling rate converter 26
Is provided, and an audio signal extraction unit 21 from the SDI signal from outside the station is provided.
The digital audio signal extracted by is written in the FIFO memory 23. Then, the read control unit 24 reads the digital audio signal written in the FIFO memory 23 at the read timing generated from the in-station clock signal generated by the clock generation unit 25 and the video combination information, and the sampling rate converter 2
In 6, the digital audio signal read from the FIFO memory 23 is resampled at a frequency rate synchronized with the in-station clock signal generated by the clock generation unit 25.

Therefore, in order to synchronize the digital voice signal from outside the station with the clock signal inside the station, the A /
There is no need to prepare a D converter or D / A converter,
Digital processing by the O-memory 23, the read control unit 24, and the sampling rate converter 26 makes it possible to process the digital audio signal from outside the station in synchronization with the internal clock signal. It is possible to provide a relatively small-sized and inexpensive device without causing continuity, and since the A / D converter and the D / A converter are not used.

Further, in the above embodiment, the read control section 24.
In the above, when the occurrence of the loss of the digital video signal is notified from the outside, the digital audio signal stored in the FIFO memory 23 is read at a read timing that is a predetermined number less than the reference clock number synchronized with the video frame of the clock signal. Since the number of clocks of the clock signal is reduced by a predetermined number and control is performed so as to complement the video loss, synchronous playback of a digital audio signal that does not feel uncomfortable even if the digital video signal is lost You can

Further, in the above embodiment, the read control unit 2
In 4, the digital audio signal stored in the FIFO memory 23 is read at a read timing that is larger than the reference clock number synchronized with the video frame of the clock signal by a predetermined number when the occurrence of the interlacing of the digital video signal is notified from the outside. Therefore, by increasing the number of clocks of the clock signal by a predetermined number and controlling so as to complement the interlaced portion of the video, a digital audio signal that does not feel uncomfortable even if interlaced digital video signals occur. Synchronous playback is possible.

Although the hardware configuration has been described in the above embodiment, it may be implemented by a software configuration as shown in FIG.

That is, reference numeral 100 is a synchronous processing device, to which a FIFO memory 200 is connected. The processing by the audio signal extraction unit 21, the clock generation unit 22, the read control unit 24, the clock generation unit 25, the sampling rate converter 26, and the audio signal multiplexing unit 27 is realized by software processing of the synchronization processing device 100. .

First, when the synchronous processing device 100 starts the control process shown in FIG. 5, it extracts a digital audio signal from the SDI signal coming from outside the station (step ST5a), and extracts the extracted digital audio signal from the FIFO memory 200. (Step ST5b).

Subsequently, the synchronization processing device 100 determines whether or not a video loss has occurred from the outside (step S).
T5c).

If no video loss has occurred, the synchronization processing device 100 determines whether or not a video jump has occurred from the outside (step ST5d).

If no video jump occurs, the synchronous processing device 100 reads the digital audio signal from the FIFO memory 200 at the reference clock number R synchronized with the video frame of the internal clock signal (step S).
T5e), and further, the digital audio signal is resampled at the frequency rate synchronized with the internal clock signal (step ST5f), and the process is ended.

On the other hand, if a video loss occurs, the synchronous processing device 100 reads the digital audio signal from the FIFO memory 200 with a clock number that is smaller than the reference clock number R synchronized with the video frame of the internal clock signal by α. Step ST5g), and the process proceeds to step ST5f.

If a video jump occurs, the synchronization processing device 100 reads the digital audio signal from the FIFO memory 200 at a clock number that is α larger than the reference clock number R synchronized with the video frame of the internal clock signal ( Step ST5h), and the process proceeds to step ST5f.

As described above, the present invention can be implemented by the other embodiments described above. In particular, since each process can be realized by software, the configuration is simplified and it is possible to contribute to miniaturization.

In addition, the configuration of the synchronization processing device, the types of signals to be handled, the control procedure for synchronizing the digital audio signal with the clock signal in the office, and the contents thereof are variously modified without departing from the scope of the present invention. it can.

[0049]

As described above in detail, according to the present invention,
It is possible to provide a synchronous processing device and a synchronous processing method capable of processing a digital material signal coming from the outside in synchronization with an internal clock signal without causing quality deterioration.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a synchronization processing device according to the present invention.

FIG. 2 is a timing chart for explaining a processing operation when a video is missing in the same embodiment.

FIG. 3 is a timing chart for explaining a processing operation when an image is skipped in the embodiment.

FIG. 4 is a block diagram showing a configuration of a synchronization processing device according to another embodiment of the present invention.

FIG. 5 is a flowchart illustrating a processing operation according to the other embodiment.

FIG. 6 is a block diagram showing a configuration of a conventional signal processing device.

[Explanation of symbols]

11, 21 ... Audio signal extraction unit, 12, 15, 22, 25 ... Clock generator, 13 ... D / A converter (D / A), 14 ... A / D converter (A / D), 23, 200 ... FIFO memory, 24 ... Read control unit, 26 ... Sampling rate converter, 27 ... Audio signal multiplexing unit, 100 ... Synchronous processing device.

Front page continuation (51) Int.Cl. ⁷ Identification code FI theme code (reference) H04N 7/081 F term (reference) 5C063 AA01 AB03 AB07 AC01 AC05 BA08 CA20 CA23 CA36 DA05 DA13 DB10 5K028 AA01 EE02 EE03 KK03 KK17 NN22 NN23 SS26 5K041 BB10 CC01 CC04 CC07 DD04 FF01 FF32 HH41

Claims (6)

[Claims] 1. The present invention is applied to a digital broadcast signal transmission system for handling a multiplexed signal which is obtained by multiplexing a first digital material signal and a second digital material signal having a transmission block structure of a predetermined data length unit, and is applied to the multiplex. The first digital material signal is extracted from the signal, the second digital material signal is synchronized with the clock signal handled by the digital broadcast signal transmission system, and the first digital signal is synchronized with the clock signal handled by the digital broadcast signal transmission system. And a storage means for storing the second digital material signal extracted from the multiplexed signal, and a combination of the first digital material signal separately provided. At the read timing generated from the information and the clock signal, the second digital signal stored in the storage means is stored. And a resampling processing means for resampling the second digital material signal read from the storage means by the reading control means at a frequency rate synchronized with the clock signal. A synchronous processing device comprising: 2. The present invention is applied to a digital broadcast signal transmission system that handles a multiplex signal that is obtained by multiplexing a digital video signal and a digital audio signal having a transmission block structure of a predetermined data length unit, and is applied from the multiplex signal to the digital audio signal. A synchronization processing device for synchronizing the digital audio signal with a clock signal handled by the digital broadcast signal transmission system and re-multiplexing the digital audio signal with a digital video signal synchronized with the clock signal handled by the digital broadcast signal transmission system. Storage means for storing the digital audio signal extracted from the multiplex signal, and read timing generated from separately provided coupling information of the digital video signal and the clock signal,
A read control unit for reading the digital audio signal stored in the storage unit, and a resampling unit for resampling the digital audio signal read from the storage unit by the read control unit at a frequency rate synchronized with the clock signal. A synchronous processing device comprising a sampling processing means. 3. The read control means, when a dropout occurs in the digital video signal, is stored in the storage means at a read timing that is a predetermined number less than the number of reference clocks synchronized with the transmission block of the clock signal. The synchronization processing device according to claim 2, further comprising a function of reading the digital audio signal. 4. The read control means, when an interlace occurs in the digital video signal, is stored in the storage means at a read timing that is a predetermined number greater than a reference clock number synchronized with the transmission block of the clock signal. The synchronization processing device according to claim 2, further comprising a function of reading the digital audio signal. 5. The present invention is applied to a digital broadcast signal transmission system that handles a multiplexed signal which is a signal obtained by multiplexing a first digital material signal and a second digital material signal having a transmission block structure of a predetermined data length unit, and the multiplexing is performed. The first digital material signal is extracted from the signal, the second digital material signal is synchronized with the clock signal handled by the digital broadcast signal transmission system, and the first digital signal is synchronized with the clock signal handled by the digital broadcast signal transmission system. And a first process of storing the second digital material signal extracted from the multiplex signal in a memory, the first digital signal being provided separately. The first information stored in the memory is read at the read timing generated from the combination information of the material signal and the clock signal. Second step of reading the digital material signal of, and a third step of resampling the second digital material signal read from the memory by the second step at a frequency rate synchronized with the clock signal. And a synchronous processing method. 6. A digital broadcast signal transmission system that handles a multiplex signal, which is obtained by externally and multiplexes a digital video signal and a digital audio signal of a transmission block structure of a predetermined data length unit, and is applied from the multiplex signal to the digital audio signal. A synchronous processing method for extracting the digital audio signal, synchronizing the digital audio signal with a clock signal handled by the digital broadcast signal transmission system, and re-multiplexing the digital audio signal with a digital video signal synchronized with the clock signal handled by the digital broadcast signal transmission system, A first step of storing the digital audio signal extracted from the multiplex signal in a memory, and a read timing generated from the separately provided combination information of the digital video signal and the clock signal,
A second step of reading the digital audio signal stored in the memory; and a second step of resampling the digital audio signal read from the memory by the second step at a frequency rate synchronized with the clock signal. 3. A synchronous processing method comprising the steps 3) and 3).