JP2003100091A - Power source step-down circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce power consumption and to prevent spoiling reliability of an internal circuit, in a semiconductor memory. SOLUTION: Current consumption is reduced by making a step-down circuit itself a standby state by a transistor N3 at the time of standby state of an internal circuit, while a transistor P4 being a switch element supplying reference voltage Vref as power source voltage Vint for internal circuit is provided additionally and separately, at the time of standby state of the step-down circuit. Therefore, reference voltage Vref being the same voltage as that at the time of operation can be supplied as power source voltage of the internal circuit at the time of standby, the reliability of an element never be spoiled.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a power supply step-down circuit, and more particularly to a power supply step-down circuit for stepping down an external power supply to a predetermined reference voltage and outputting it as a power supply voltage for internal circuits in a semiconductor memory device.

[0002]

2. Description of the Related Art In recent semiconductor memory devices, high integration,
There is an increasing demand for lower power consumption and higher operating speed. One type of semiconductor memory device is one that includes a step-down circuit that steps down the power supplied from the outside and supplies it to the internal circuit in order to reduce power consumption or protect the elements that form the internal circuit. is there. In such a semiconductor memory device, it is necessary to reduce the power consumption of the step-down circuit in order to reduce the power consumption.

Conventionally, as one type of semiconductor memory device, an externally supplied power source is stepped down by a step-down circuit to be supplied to an internal circuit to reduce power consumption and protect elements constituting the internal circuit. There is something I did. As an example of such a step-down circuit, the configuration shown in FIG. 5 is widely known.

Referring to FIG. 5, the basic circuit of the step-down circuit is configured to include a differential circuit 1, and a differential pair of N-channel transistors N1 and N2 whose sources are commonly connected.
And P which is the drain load of these differential pair transistors
And a current mirror composed of channel transistors P1 and P2. The differential circuit 1 uses an external power supply Vext as an operating power supply, an internal reference voltage Vref is applied to the gate input of the transistor N2, and
An operating power supply voltage (power supply voltage for internal circuit) Vint to an internal circuit (not shown) is connected to the gate input of 1.

The gate of the P-channel transistor P3 is connected to the drain of the transistor N2, and the external power supply Vext is applied to the drain thereof. Also,
The power supply voltage Vint for the internal circuit is connected to the source. An N-channel transistor N3 for controlling activation of the differential circuit 1 is provided between the common source connection point of the transistors N1 and N2 and the ground point. A control signal generation circuit 2 is provided for on / off control of the transistor N3.
A CE (chip enable) signal in the semiconductor memory device is applied as an input thereto.

The CE signal corresponds to a signal indicating whether the internal storage circuit is in the standby state or the operating state. Therefore, when the storage circuit is in the operating state, the control signal generating circuit 2
Generates a control signal for turning on the transistor N3 to activate the differential circuit 1.

At this time, the differential circuit 1 compares the reference voltage Vref with the internal circuit power supply voltage Vint (having a function of a comparison circuit). If Vint is high, the transistor N1 is turned on and the transistor N2 is turned off. . Therefore, the P-channel transistor P3 is turned off. On the contrary, when Vint is low, the transistor N1 is turned off, the transistor N2 is turned on, the P-channel transistor P3 is turned on, and energy is replenished from the external power supply Vext. By such an operation, the internal circuit power supply voltage Vin
t is always adjusted so as to match the reference voltage Vref.

On the other hand, in the standby state, the differential circuit 1 is inactivated by controlling the transistor N3 to be off. Therefore, the step-down circuit including the differential circuit 1 does not consume current. At this time, the gate potential of the P-channel transistor P3 is pulled up to a high level, so that the transistor P3 is turned off and the energy for driving the internal circuit power supply voltage Vint is lost.
The internal circuit power supply voltage Vint will drop due to the internal circuit current during standby.

Therefore, Japanese Laid-Open Patent Publication No. 4-274504 discloses a circuit in which the external power supply Vext is applied as the power supply voltage for the internal circuit so that Vint does not drop during standby. . FIG. 6 shows the configuration of this circuit, and the same parts as those in FIG. 5 are designated by the same reference numerals.

In FIG. 6, an N-channel transistor N4 is provided between the gate of the P-channel transistor P3 and the ground point, and this transistor N4 is turned on / off under the control of the control signal generation circuit 2. The other structure is the same as that of FIG. 5, and thus the description thereof is omitted.

That is, during standby of the internal circuit, the transistor N4 is forcibly turned on to turn on the P-channel transistor P3, and a high level Vext is applied to the internal circuit power supply voltage Vint.

Further, as disclosed in Japanese Patent Laid-Open No. 10-74394, the step-down circuit is stopped during standby of the internal circuit so that the internal circuit power supply voltage Vint is changed to the external power supply Vext.
To Vth (threshold value of transistor), a method of driving at a lower voltage is disclosed.

FIG. 7 is a diagram showing the structure of this circuit, and the same parts as those in FIGS. 5 and 6 are designated by the same reference numerals. That is, an N-channel transistor N5 is provided between the external power supply Vext and the internal circuit power supply voltage Vint, and the control signal generation circuit 2 turns on the transistor N5 during standby of the internal circuit to reduce Vint = Vext−Vth. The voltage is supplied to the internal circuit. The other circuit configuration is the same as that of the example of FIG. 5, and the description thereof is omitted.

[0014]

In the circuit configuration shown in FIG. 6, the external power supply V is originally used as the power supply voltage for the internal circuit.
Although the voltage of ext is used to maintain the reliability of the elements of the internal circuit, the high level external power supply Vext is directly applied to the internal circuit during standby, so that the reliability of the internal circuit is reduced. It has the drawback of being difficult to maintain.

Further, in the circuit configuration shown in FIG. 7, the voltage (Vext-Vth) is supplied to the internal circuit in the standby state. However, even if the voltage is lower by Vth, it is still at the high level voltage. There is no difference and it is difficult to maintain reliability.

As described above, the internal voltage step-down circuit as shown in FIGS. 5 to 7 is used for a memory having a particularly large capacity and low power consumption among memory devices. Generally, the current consumption during operation is focused on. Also,
For higher capacity, fine processing has advanced and the withstand voltage limit of the device has become lower. Therefore, by reducing the external power supply voltage and using it, the reliability of the circuit device and the power consumption of the circuit can be further reduced. However, in recent years, in memories used in mobile terminals, it has been required to reduce current consumption during standby to a microampere order.

In order to meet such a requirement, it is apparent from the examples of FIGS. 5 to 7 that the internal voltage down converter is inactivated (stopped) during standby to reduce the current consumption. If you stop the internal step-down circuit during standby,
The standby current of the internal circuit lowers the power supply voltage Vint for the internal circuit, and the stored information in the memory is destroyed (in the case of the circuit of FIG. 5). Therefore, in the standby mode, the external circuit power supply Vext is used as it is as the internal circuit power supply voltage Vint (FIG. 6) and the one-step voltage drop of the transistor threshold Vth (FIG. 7) is used. Is applied to the internal circuit element, and the problem that reliability is lowered remains.

An object of the present invention is to provide a power supply step-down circuit which can reduce current consumption while the internal circuit is on standby and at the same time, does not impair the reliability of the internal circuit element.

[0019]

According to the present invention, there is provided a power supply step-down circuit for stepping down an external power supply to a predetermined reference voltage and outputting it as a power supply voltage for an internal circuit, wherein the internal circuit operates by the external power supply. Step-down means for maintaining the power supply voltage for use to be equal to the reference voltage, control means for activating and controlling the step-down means, and the control circuit for setting the reference voltage to the internal circuit when the step-down means is inactive. A power supply step-down circuit is obtained which includes switch means for deriving as a power supply voltage for use.

Further, the control means is characterized in that the step-down means is inactivated when the internal circuit is in a standby state, and the step-down means is operated by the external power source. A comparator circuit that operates and compares the reference voltage with the power supply voltage for the internal circuit, and turns on when the power supply voltage for the internal circuit decreases with respect to the reference voltage to turn on the external power supply for the internal circuit. It is characterized by having a switch element supplied as a voltage. Further, the comparison circuit has a differential circuit configuration in which a current mirror circuit is used as a load.

The operation of the present invention will be described. When the internal circuit is in the standby state, the step-down circuit itself is also in the standby state to reduce current consumption, and at the same time, when the step-down circuit is in the standby state,
A transistor, which is a switch element that supplies the reference voltage as the power supply voltage for the internal circuit, is additionally provided. As a result, as the power supply voltage of the internal circuit during standby,
It is possible to supply a reference voltage that is the same voltage as during operation, and the reliability of the device is not impaired.

[0022]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a circuit diagram of an embodiment of the present invention, and the same parts as those in FIGS. In this example, in the circuit of FIG. 5, the reference voltage Vre
A P-channel transistor P4 is provided between f and the internal circuit power supply voltage Vint, and the transistor P4 is controlled to be turned on / off by the control signal generation circuit 2. The other structure is the same as that of FIG. 5, and therefore the description thereof will be omitted.

FIG. 2 is a diagram showing a specific example of the control signal generation circuit 2 in FIG. That is, it has a NAND gate 22 which receives a CE (chip enable) signal which is an input of the control signal generation circuit 2 and a delay element 21 which delays this CE signal, and the output of this delay element 21 is It is the other input of the NAND gate 22. The output of the NAND gate 22 serves as a control signal to control the on / off of the transistors N3 and P4. In this example, the internal circuit is in the operating state when the CE signal is at the low level, and is in the standby state when the CE signal is at the high level.

FIG. 3 is a timing chart for explaining the operation when the internal circuit shifts from the operating state to the standby state. At time ts1, when the CE signal becomes high level, the internal circuit starts to stop, and when a certain time has elapsed, it enters a standby state at ts2. The current consumption is reduced accordingly and the standby current is 1
It changes as shown in.

At time ts3 thereafter, the control signal becomes low level (corresponding to the delay time of the delay element 21 in FIG. 2), the transistor N3 is turned off, the differential circuit 1 becomes inactive, and the current consumption is further reduced. (Standby current 2). At the same time, since the transistor P4 is turned on, the internal circuit power supply voltage Vint maintains the reference voltage Vref.
The delay time of the delay element 21 of the control signal generation circuit 2 is the time ts1 to ts3 in FIG.

FIG. 4 is an operation timing chart when shifting from the standby state to the operating state. At time ta1, the CE signal becomes low at the same time that the control signal becomes high, turning on the transistor N3 and activating the differential circuit 1 to activate the step-down circuit. When the internal circuit is activated at time ta2, the step-down circuit has already been activated, so there is no effect of stopping the step-down circuit. Naturally, at this time, the transistor P4 is off.

[0027]

As described above, according to the present invention, when the internal circuit is on standby, the step-down circuit itself is stopped to reduce the power consumption and the reference voltage is maintained as the power supply voltage for the internal circuit. Therefore, there is an effect that the reliability of the element is not impaired.

[Brief description of drawings]

FIG. 1 is a circuit diagram of an embodiment of the present invention.

FIG. 2 is a diagram showing an example of a control signal generation circuit 2 of FIG.

FIG. 3 is a timing chart at the time of transition from the operating state to the standby state in the embodiment of the present invention.

FIG. 4 is a timing chart at the time of shifting from a standby state to an operating state in the embodiment of the present invention.

FIG. 5 is a diagram showing an example of a conventional step-down circuit.

FIG. 6 is a diagram showing another example of a conventional step-down circuit.

FIG. 7 is a diagram showing another example of a conventional step-down circuit.

[Explanation of symbols]

1 Differential circuit (comparator circuit) 2 Control signal generation circuit P1, P2 Current mirror circuit transistor N1, N2 Differential pair transistor P3 Vext supply transistor N3 activation control transistor P4 Vref supply transistor

   ─────────────────────────────────────────────────── ─── Continued front page    F-term (reference) 5B015 HH04 JJ03 KB64 KB73 QQ18                 5B025 AD09 AE06                 5H430 BB01 BB09 BB11 EE04                 5M024 AA04 FF02 FF23 GG02 PP01                       PP02 PP03 PP07

Claims (4)

[Claims] 1. A power supply step-down circuit that steps down an external power supply to a predetermined reference voltage and outputs it as an internal circuit power supply voltage, wherein the internal circuit power supply voltage is made equal to the reference voltage by operating with the external power supply. A step-down means for maintaining the step-down means, an activation means for controlling the step-down means, and a switch means for deriving the reference voltage as the power supply voltage for the internal circuit by the control means when the step-down means is inactive. A power supply step-down circuit including: 2. The power supply voltage down circuit according to claim 1, wherein said control means is configured to deactivate said voltage down means when said internal circuit is in a standby state. 3. The step-down means is operated by the external power supply and compares the reference voltage with the power supply voltage for internal circuit; and the power supply voltage for internal circuit is lower than the reference voltage. The power supply step-down circuit according to claim 1 or 2, further comprising: a switch element which is turned on at a time to supply the external power supply as a power supply voltage for the internal circuit. 4. The power supply step-down circuit according to claim 1, wherein the comparison circuit has a differential circuit configuration using a current mirror circuit as a load.