JP2003100089A - Nonvolatile semiconductor memory - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enable preventing malfunction even if a mode is switched using two control signals /CE, /OE. SOLUTION: This device is provided with a mode recognizing means recognizing whether it is a command write-in mode or a read-out mode based on timing of two control signals, a latch command signal generating means generating a command signal commanding latching an address based on an output of the mode recognizing means, and an address buffer latching an address based on an output of the latch command signal generating means and holding or transferring latched address.

Description

DETAILED DESCRIPTION OF THE INVENTION [0001] BACKGROUND OF THE INVENTION
Non-volatile that can be erased, written and read all at once
The present invention relates to a semiconductor memory device. [0002] 2. Description of the Related Art
In addition, a flash E that can rewrite electrical data^TwoP
In a ROM (hereinafter simply referred to as a storage device),
Command switching of each mode such as data writing and erasing
Command (combination of data)
Expressions are the mainstream. For example, as a control signal, bar C
By the logic of three signals E, OE, and WE
The bar CE,
When the bar OE and the bar WE are “L”, “H” and “L” respectively
Command write mode, "L", "L", "H"
Is distinguished from the read mode. That is, bar C
When E is at "L", the storage device is activated and bar O
Command write mode and read with E and bar WE values
The mode is being switched. All bits of such a storage device
Figure 15 shows the automatic erase command mode for erasing
This will be described with reference to FIGS. The automatic erase command is
Pre-program to write to all bits
Erasing after programming
Judgment whether program is OK at ram and erase at erase
It is automatically determined whether or not it is OK. [0005] The operation inside the storage device at the time of this automatic erasure is shown in FIG.
The flowchart of FIG. First, make the initial settings
(See step F171) “0” is set in the first memory cell.
The data is written (see step F172). Followed by high
The recovery state and the data that discharge the voltage are written correctly.
Into a verify state to verify that
F173). And read the written data
And compared with the reference data (see step F174),
If not correctly written,
Repeat steps F172, F173, and F174
(See steps F176 and F177). Repeat this time
If the number exceeds, for example, 25 times, this storage device is defective.
judge. On the other hand, if data is written correctly,
1 is added to the address of the memory cell where the data was written.
(Refer to step F175), and return to step F172.
Data is stored in the next memory cell corresponding to the address to which 1 has been added.
Data "0", and the following steps F173 and F1
Repeat step 74 to write data "0" to all memory cells.
Put in. When data is written to all memory cells
Batch erase is performed (see step F180). Then Rika
The state is changed to the bury state and the verify state (step F1).
81), data is read from each memory cell, and
Verification of complete erasure by comparing with preliminary data
(See step F182)
If not, steps F180 and F1 are performed until the data is completely erased.
81 and F182 are repeated (steps F183, F18
4). However, this repetitive operation is performed repeatedly, for example.
If the number exceeds 3000 times, stop and remove this storage device.
It is determined to be defective. In such an automatic erase command mode,
FIG. 15 shows a timing chart of the normal operation.
A reset command to forcibly stop the current mode is input.
FIG. 16 shows a timing chart in the case of the above. FIG.
At the start of bar CE and bar WE
Is automatically erased by inputting the password data "30" twice.
It goes into the leaving mode. This command data is input
Since the data is 8 bits, it is expressed in hexadecimal. Self
When the system enters the automatic erase mode, the built-in timer
Automatic erasure is performed within the set time. State at this time
Is the least significant data bit as the status polling signal.
To the outside using D7. During erase operation (Bu
sy state), the status polling signal is “0”.
When the erase operation is completed (Ready state), “1” is output.
Become. Thereafter, in FIG. 15, the bar CE, the bar WE
Command data expressed in hexadecimal at the rising edge of
Data "10" is input to enter the automatic program mode. [0006] On the other hand, in FIG.
Up to the same as the case of FIG.
During the loading of the bar CE and bar WE,
When the set command “FF” is input twice and the automatic erase mode
Is forcibly stopped and reset. Conventional
Input of set command can be done in one step or two steps
This is done in two steps in FIG.
You. As described above, automatic erasing using the command method
Mode is either active or active during normal operation
Is completed by the status polling signal.
It was possible to know. However, during operation
If a reset is forcibly applied, the automatic erase operation
Stop immediately and accept the next command
Become. On the user side, when to reset
There were no restrictions, and in some cases, the next operation was immediately performed
Sometimes there are times. Reset is performed during program operation or erase operation
When applied in the middle, that is, when the memory cells and peripheral circuits
Immediately after resetting with the potential applied,
If the next operation mode is entered, the correct voltage cannot be set,
It causes operation. For example, reset during program
When the word line goes from high potential to V_cc(Power supply potential)
If read mode is set before reading, correct cell data
Can no longer be delivered. Correct behavior after reset
To perform the operation, wait for the internal
It has to be known, and the conventional product has a certain time (6 μs ~
10 μs) had to wait. Further, in a conventional storage device, data
When writing or erasing in block units, the address
Setting is required, and command input is controlled as shown in FIG.
Of the falling (or rising) of the signal bar WE to be controlled
Set at the timing. When entering a command, enter the address
Is the falling edge of the signal bar WE in the command input mode.
The address is fetched at the timing, and
Can be implemented by a device that maintains the address latch state during
You. This device is, for example, a CE buffer as shown in FIG.
61, WE buffer 62, V_ppThe detection circuit 63 and
Dress latch pulse generating circuit 66 and address buffer
67. CE buffer
61 is synchronized with the signal bar CE based on the signal bar CE
And activates the WE buffer 62 and the address buffer 67.
A signal CES1B to be converted is output. WE buffer 62
Is an address line based on the signal bars WE and CES1B.
Output a signal WES1B for controlling the generation of a switch pulse.
You. This signal WES1B is, as shown in FIG.
When signal 62 is activated, signal WE rises.
The signal WE falls after a predetermined time delay from the fall.
This signal rises in synchronization with the rise. V_ppDetection
The circuit 63 has a voltage V of an erasing power supply._ppHowever, when performing the erase operation
Detects whether the voltage has reached a sufficient value.
If, for example, it has reached enough (V_pp= 12V)
Becomes “0”, and if not reached (V_pp= V_cc)
The signal SVPPB which becomes “1” is output. Address
In the pulse generation circuit 66, the signal SVPPB is "0".
Address line synchronized with the fall of the signal WES1B
Circuit that outputs a switch pulse AL and its inverted pulse ALB
And configured, for example, as shown in FIG.
It is. When the signal ALB is "1", the address buffer 67
Only address A_iWhen the signal ALB is "0"
The address latched when the signal WES1B falls
And a decoder (not shown) that always holds the
20b, for example, as shown in FIG.
It is configured like this. FIG. 2 shows the timing of each signal described above.
1 is shown. As described above, two power sources V_pp, V_ccConventional using
, Erase, command input
In mode V_ppIs set to a high voltage (= 12V)
Is V _ppTo V_cc(= 5V) or 0V to high voltage (= 12
ALB goes to “L” when it is raised to
Slatch state (V_pp= 12V when the address is
Latched state) (see FIG. 22). Therefore, V_pp= After setting to 12V
In order to perform normal random read, the above address
There is a problem that can only be done after releasing the state
Was. Also, three control signals CE, OE,
Conventional storage device for switching modes using bar WE
Command write mode in program operation
Status signal indicating the status of the storage device from the
Timing of a series of control signals until the status read
FIG. Program operation in FIG.
Is performed in two steps.
And the second step is the address to program
And enter the data. Bar in command write mode
An address is taken at the falling edge of CE or WE.
And latches, rising of bar CE or bar WE
Data is latched at the edge. Stator signal
When reading the signal, in the previous command write mode
The latched address and data are held as they are.
As described above, the command writing mode indicates that the bar WE is
“L”, OE is “H”, and the read mode is
-WE is clearly distinguished from "H" and bar OE is clearly distinguished from "L"
ing. However, due to compatibility with EPROM, the control signal
A storage device controlled only by the bar CE and the bar OE was also proposed.
Have been. In such a storage device, the signal bar CE
Switch between the active state and the standby state
The distinction between command write mode and read mode is
-While CE is a negative pulse, signal OE is
It keeps the “H” state or the signals CE and OE
Switching is performed depending on whether the signal becomes "L" or "L", respectively. This
Command for program operation in such a storage device
Control signal from embedded mode to status read
24 is shown in FIG. Referring to FIG.
-The movements of CE and OE are the same as those shown in FIG.
You. However, because there is no signal bar WE, command write
In both mode and status mode, the falling edge of the signal bar CE
When the signal bar OE is at the "H" level, the signal bar CE
Only when falling, the current operation is
Mode or read mode (status read)
I do not know what it is. That is, the command write mode
Mode, it is added at the falling edge of the signal CE.
Readout while you have to capture the
In mode, no address is taken in and address is not latched
It is necessary to continue the state when the signal bar CE falls
There is a problem that it is not possible to make a judgment by itself. The present invention has been made in view of the above circumstances.
And using two control signals CE and OE
Non-volatile that does not malfunction even when the mode is switched
It is an object of the present invention to provide a nonvolatile semiconductor memory device. [0015] According to the present invention, there is provided a nonvolatile semiconductor memory device.
Conductor storage is based on the timing of two control signals
Command write mode or read mode.
Based on the mode recognition means and the output of the mode recognition means.
Generates a command signal to instruct whether to latch the address
Latch command signal generating means and a latch command signal generating means
Latch the address based on the output of the stage and
An address buffer that holds or transfers the latched address.
And a web browser. [0016] According to the storage device of the present invention configured as described above,
If the current mode is the command write mode, or
The read mode is recognized by the mode recognition means.
It is. Latch command signal generating means according to this mode recognition
Command signal is output from the
Address in command write mode.
Address is transferred to the decoder. This allows two controls
Even if the mode is switched by a signal, malfunction may occur.
It can be prevented as much as possible. [0017] DESCRIPTION OF THE PREFERRED EMBODIMENTS Non-volatile semiconductor memory device according to the first invention
FIG. 1 shows a configuration of an embodiment (hereinafter also referred to as a storage device).
Show. The storage device of this embodiment includes a control circuit 1 and an I / O bus.
Buffer 2, command register circuit 3, auto mode
Control circuit 4, write / erase control circuit 5, and erase circuit
6, a row decoder 7, a sense amplifier 8, and a column
And a memory cell array 10. control
The circuit 1 is based on the control signals CE, OE and WE.
Control the I / O buffer 2 and command register circuit 3
Control. The command register circuit 3 is an I / O buffer
Recognizes commands entered via the
This is a circuit for switching between modes, such as the one shown in FIG.
Program command register 3a and erase command
Has a register 3b and a reset command register 3c.
are doing. The auto mode control circuit 4 has a command register
The operation of each auto mode switched by the circuit 3
Control circuit, as shown in FIG.
Ram start circuit 4a, NAND gate and invert
A logic circuit 4b composed of data, a program timer 4c,
Program verify timer 4d and auto comparator
4e, an auto erase start circuit 4f, and a NAND gate.
Logic circuit 4g comprising a gate and an inverter, and an erase timer
4h, erase verify timer 4i, polling time
Road 4j. The write / erase control circuit 5
Voltage V applied to the memory cell array 10 during writing and erasing.
_ppIs a circuit for setting the program, as shown in FIG.
Control circuit 5a, verify control circuit 5b,
Path 5c, erase control circuit 5d, data latch circuit 5e
And The erasing circuit 6 operates at a high voltage V during erasing._ppGenerate
Circuit. The row decoder 7 corresponds to a row address.
Column memory 9 and the column address
Select a memory cell corresponding to the memory cell. The sense amplifier 8
Selected by the row decoder 7 and the column gate 9
The data stored in the memory cell is read. The program command register 3a stores a command
Command program data "1"
When "0" is set, it is recognized as the auto program mode.
Output signal APRO to "1" at the end of program or
Sets the output signal APRO to "0" when a reset command is input
Auto program start circuit 4a and
To the output circuit 4j. The erase command register 3b has an auto erase function.
Recognize commands "30" and "30" and output signal AER
S is set to "1" at the end of erasing or when a reset command is input
Output signal AERS to “0”
It is sent to the start circuit 4a and the polling circuit 4j. The reset command register 3c has a reset
Command "FF", "FF" is recognized and the first step
Generates pulse signal FF1P when inputting "FF" command
When the command “FF” of the second step is input,
Generates a loose signal FF2P and sends it to the polling circuit 4j
Signal FFRT between the first and second steps
Is set to “1”, and “0” is set in other periods. The auto program start circuit 4a is a professional
This circuit outputs a pulse signal PPUS at the start of a program.
Thus, specifically, the output signal AP of the command register 3a
When RO is "1" (at the time of auto program), the command
When the output signal AERS of the register 3b is "1" (
Program erase), or program operation restarts during auto operation.
In case of start (output pulse of auto comparator 4e
Generates pulse signal PPUS when signal APV is received)
I do. The logic circuit 4b receives a signal PROG (program
An output signal of the control circuit 5a, which is set to "1" at the time of writing.
The signal P which is a delay of "0"
ROGD and the output signal FF1P of the command register 3c
AND with the program timer 4c
To send to. The program timer 4c receives the signal PPUS.
After a predetermined time (for example, 10 μs) after the
No. TPRG is output. Program verify timer 4
d operates with the signal TPRG after programming, and
Outputs pulse signal TPR after a set time (for example, 6 μs)
I do. The auto comparator 4e has an automatic operation
Correct write to memory cell during program verify
Judge whether or not the
It is determined whether reselling has been correctly performed. Blog
Judgment when signal TPR is "1" at the time of lamb verify
At the time of erase verify, the erase verify timer 4i
The determination is made when the output signal TER is “1”. With the following behavior
The program start circuit.
4a, the pulse signal APV to be transmitted is set to "1".
When the ram start circuit 4a is driven and erasing is performed, erasing is performed.
The pulse signal AEV sent to the start circuit 4f is set to "1".
To drive the erase start circuit 4f. And the blog
At the end of the program operation in the ram mode, the pulse signal EN
Reset and erase command register 3a using DP
In the case of the mode, the pulse signal EN
The erase start circuit 4f is driven by using the DP to perform an erase operation.
At the end, the command register using the pulse signal ENDE
3b is reset. The auto erase start circuit 4f starts the erase operation.
Circuit that outputs a pulse signal EPUS to the
During operation, the output signal AEV of the auto comparator 4e is received.
To generate a pulse signal EPUS. The logic circuit 4g outputs a signal ERAS (erase control circuit).
This is an output signal of the path 5d, which is "1" at the time of the erase operation.
In other cases, the signal ERA which has been delayed
Between the SD and the output signal FF1P of the command register 3c.
Calculates the logical product and sends the logical product to the erasure timer 4h
You. The erasure timer 4h outputs the pulse signal EPUS.
After a predetermined time (for example, 10 ms) from the reception, the pulse
The signal TERS is output. After erasure, the erase verify timer 4i
After a predetermined time (6 μs) after receiving the
And outputs the output signal TER. The polling circuit 4j operates during the auto operation or
Status polling signal during recovery operation at reset
Signal in the "Busy" state, that is, input of the I / O buffer 2
In order to make the output of the output pin D7 “0”, the signal POL is
Set to “0” and recover after auto operation or reset.
After the burr operation is completed, the status polling signal is
dy ”state, that is, the output of the input / output pin D7 becomes“ 1 ”
And outputs it to the I / O buffer 2. At the time of programming, the program control circuit 5a
The word line and bit line of the write cell have boosted potentials (for example,
If the word voltage V_WL= 12V, bit line voltage V_BL= 6
V) to control the booster circuit 5c. The verify control circuit 5b operates at the time of verification.
Word line voltage write and erase margins
During program verification, the word line voltage V_WL
Is set to 7V, and V is set during erase verify._WLTo 3.5V
Set. The booster circuit 5c is connected to a word line and a bit line during programming.
It is used to boost the potential of the cut line. The erasure control circuit 5d operates at the time of erasing the memory cells.
A boosted potential is applied to the source (for example, the source voltage V_s= 12V)
The erasing circuit 6 is controlled so as to be given. The data latch circuit 5e has an auto program
This is a circuit that sometimes latches write data. Auto
When verifying the program, the output of the sense amplifier 8
And the data latched by the latch circuit 5e.
The comparator 4e compares and writes correctly
To determine if During auto erase,
All bits are set to “0” (write state) during program operation.
Auto-comparison of program verify as expected value
All the bits "1" (erasing) during the erasing operation.
Erase verify) with the expected value of
This is performed by the lator 4e. And these expected values are also
This is set by the tare latch circuit 5e. Next, the operation of this embodiment will be described with reference to FIGS.
It will be described with reference to FIG. Fig. 3 shows the case of normal auto erase mode
4 is a timing chart of the operation of FIG. In FIG.
Dynamic erase commands "30" and "30" are I / O buffer 2
Is input through the erase command register 3
b recognizes and sets the output signal AERS to "1". Then
Pulse signal PP from auto program start circuit 4a
US is output, whereby the program control circuit 5a
The output signal PROG becomes "1" and the booster circuit 5c is driven
And writing of data “0” to one memory cell is started.
Begun. That is, step F172 of FIG.
Is done. At this time, the output signal of the polling circuit 4j is output.
The signal POL also becomes "0", and this value is the value of the I / O buffer 2.
Output to the outside via the input / output pin D7, and
Inform the outside that the unit is in the “Busy” state. A predetermined time after the pulse signal PPUS is generated
When the time has elapsed, the pulse signal T is output from the program timer 4c.
PRG is output, whereby the program control circuit 5a
Output signal PROG becomes "0" and verify
The output signal PREC of the control circuit 5b becomes “1”, and FIG.
Step F173 of Step 7 is executed. After the pulse signal ENDP is generated,
After a predetermined time elapses, the auto erase start pulse signal TP
When a predetermined time has passed since the RG was generated, the program
Pulse signal TPR is generated from verify timer 4d.
To determine whether the program was executed correctly.
Execute program verification. That is, the step shown in FIG.
Step F174 is executed. During this verification,
And that data 0 was written
Address, increment the address to the next address
FIG. 17 for writing the memory cell corresponding to
Steps F175 and F172 are executed. Also, data
If it is determined that “0” cannot be written correctly,
Additional writing of the memory cell corresponding to the address is performed.
Steps F176, F177, and F172 in FIG.
Be executed. Repeat this operation until all addresses are
When data “0” is written to the recell,
The pulse signal ENDP is generated from the
Gram mode is completed. Also, a pulse signal ENDP is generated.
Auto erase start circuit after a predetermined time has passed
4f generates a pulse signal EPUS.
The signal RAS output from the control circuit 5d becomes "1".
Then, the erasing circuit 6 is driven to enter the erasing mode. sand
That is, step F180 shown in FIG. 17 is executed. A predetermined time after the pulse signal EPUS is generated
When the time has elapsed, the pulse signal TER is output from the erase timer 4h.
S is issued, thereby outputting the output ER of the erase control circuit 5d.
AS becomes "0" and the verify control circuit 5b
The output EREC becomes "1". That is, the switch shown in FIG.
Step F181 is executed. And whether the pulse signal TERS is generated
After a lapse of a predetermined time, the erase verify timer 4i
A pulse signal TER is generated. This allows Verifa
B) The output EREC of the control circuit 5b becomes "0" and the erase
Coverage mode ends. A pulse signal TER is generated
Eraser to determine whether the
Execute refining. That is, step F18 in FIG.
2 is executed. If the erase is incomplete with this verification
Is an auto erase start 4 via the auto comparator 4e.
f, a pulse signal EPUS is generated and erase is performed again.
It is. That is, steps F182 and F18 shown in FIG.
3, F184 and F180 are executed. If the erasure is complete, the comparator 4
e outputs a pulse signal ENDE. This will erase
Command register 3b stops and its output signal AER
S becomes "0" and the output signal of the polling circuit 4j
POL becomes "1", and the erasing is completed. FIG. 4 shows a state during automatic erasing (during program mode).
Timing chart of operation when reset is applied to
It is. In FIG. 4, the one-step command “FF”
Is the same as the case described with reference to FIG. The reset command “FF” of the first step
Is input through the I / O buffer 2,
The pulse signal FF1 is recognized by the reset command register 3c.
Generates P and sends it to the polling circuit 4j
The signal FFRT is set to “1”. Generates pulse signal FF1P
The operation of the erase command register 3b stops.
Then, the automatic erase mode is stopped. That is, the erase command
The output signal AERS of the register 3b becomes "0". Continued
And the output PROG of the program control circuit 5a becomes "0"
The internal operation (write operation in this case)
Stop, and start recovery from the program timer 4c.
When the lus TPRG is generated, the
The output signal PREC of the path 5b becomes "1" and the recovery mode
Code. A predetermined time has passed since the recovery mode was entered
Then, the pulse signal is sent from the program verify timer 4d.
Signal TPR is issued, and the output P of the verify control circuit 5b is output.
REC becomes "0". At this time, the reset command register
Since the output FFRT of the star 3c is "1",
Circuit 4j determines that the recovery mode has been completed,
The output POL is set to “1”. That is, I / O buffer 2
Status polling signal output from input / output pin D7
The signal is in the "Ready" state. Then, the reset command in the second step
When “FF” is input, the reset command register 3
c detects this and generates a pulse signal FF2P internally
You. As a result, the reset command register 3c outputs
The signal FFRT sent to the ringing circuit 4j is "0".
Become. As described above, the reset is performed during the automatic erase mode.
If it can be applied, the first step reset command
Reset frame in the second step after “FF” is input
Until the command “FF” is input, the internal state of the storage device
As shown in Fig. 5, whether the status is in recovery or
Status polling signal (input / output pin of I / O buffer 2)
The user can know this as the output of D7). As described above, according to this practical example,
Stored when external reset is applied during card operation
The device is in the “Ready” state or “Busy”
The status polling signal is used by the status polling signal.
The can know. This can cause malfunctions
It can be prevented as much as possible, and the waiting time is lengthened unnecessarily.
This can be prevented as much as possible. In the above embodiment, the automatic erase mode is used.
In the example above, automatic block erasure was performed.
Mode, automatic program mode (write in byte units)
Mode is reset during a mode such as
In the same way, the reset command of the first step and 2
During the reset command of the step, recovery is in progress.
Status polling signal that indicates
Can be output to the outside. Next, the nonvolatile semiconductor memory according to the second invention
1 illustrates a configuration of an embodiment of a device (hereinafter, also referred to as a storage device).
6 is shown. The storage device of the embodiment is a conventional device shown in FIG.
At V_ppWhen the pulse generating circuit 64 is newly provided,
In addition, an address latch pulse generation circuit 66 is replaced with an address.
A dress latch pulse generation circuit 65 is provided. V_ppThe pulse generation circuit 64 is, for example, as shown in FIG.
V is configured as shown in FIG._ppOutput of detection circuit 63
The voltage V of the erase power supply is determined based on SVPPB._ppIs the driving voltage V
_cc(For example, 5 V) or a predetermined high voltage (for example, 1 V to 0 V).
0V or more), the single pulse signal RSTAL is output.
Power. The address latch pulse generating circuit 65 is an example.
For example, it is configured as shown in FIG._ppDetection circuit
63 outputs SVPPB and V_ppOutput of the pulse generation circuit 64
It operates based on the force RSTAL and the voltage V_ppIs V_ccbelow
In other words, if SVPPB is "1",
Switch is released (AL is “0”, ALB is “1”).
Voltage V_ppIs a high voltage, ie, SVPPB is
In the case of “0”, the single pulse signal RSTAL is V_ppPulse
Output from the raw circuit 64, the two NOR gates N
Output 72 of flip-flop composed of OR1 and NOR2
Becomes “1” and the address latch is released (AL becomes
"0" and ALB keep "1"). After that, enter the command
When the pulse of the signal bar WE is input as the force mode,
The level of node 71 that is the reset input of flip-flop
Becomes “1”, the flip-flop is released, and the node
The level becomes “0” at level 72. That is, the address latch
State. FIG. 8 is a timing chart of the above signals.
You. Voltage V_ppIs set to a high voltage, the signal SVPPB
Becomes “0” and the level of the node 72 changes from “0” to “1”.
, And the level of the signal AL is maintained at “0”. The address latch state is one stage of signal WE.
It is performed at the rising edge of the first pulse.
It is performed at the falling edge of WE. Currently, the command method is
Flash E for writing and erasing using^TwoIn PROM
At the falling edge of the second pulse of the signal bar WE.
Address, and correct the address
Switch. Note that V_ppThe pulse generation circuit is shown in FIG.
Such a configuration may be adopted. In this case V_ppIs specified from 0V
RSTAL is output when the potential rises to
It is. As described above, according to the present embodiment,
Pressure V_ppCommand input even after setting to high voltage
Before, normal random reading becomes possible. Next, the nonvolatile semiconductor memory according to the third invention
FIG. 9 shows the configuration of an embodiment of the apparatus. Memory of this embodiment
The device includes a CE buffer 91, an OE buffer 92,
Mode recognition circuit 93 and address latch pulse generation
Circuit 94 and an address buffer 95;
Read mode recognition circuit 9 determines the timing of CE and OE.
Determine whether command write mode or read mode with 3
Feedback to the address latch pulse generation circuit.
It is determined whether the address is latched or not. The read mode recognition circuit 93 of this embodiment
A specific example is shown in FIG.
A specific example of the address buffer 95 is shown in FIG.
A specific example is shown in FIG. 12, and the operation of the embodiment is shown in FIG.
It is shown in the chart. The pulse for latching the address is 2
Signal ALS1B and ALS2B, and the signal ALS
1B is at the falling edge of the signal CE and the signal ALS2B is
-Pulses at the rise of CE. Further command book
Whether the write mode is the read mode or not
Judgment at the path 93, and in the command writing mode,
In the read mode, the output signal CR of the road remains “L”.
It becomes "H". Address buffer 95 is a two-stage latch
Circuit, the first-stage latch circuit is a signal ALS1B,
The second-stage latch circuit operates by the signal ALS2B,
Latch. As shown in FIG. 13, the fall of the signal CE.
Command writing mode or reading mode with only beam
When the signal is not known, the signal ALS is output at the fall of the bar CE.
1B becomes a pulse, and the first stage of the address buffer
Switch operation. After that, until the signal bar CE rises
And if OE is “H”, the command write mode
The signal ALS2B is turned on at the rise of the bar CE.
And the address at the fall of the signal bar CE is
The data is transferred to a decoder (not shown). Also, the signal bar CE rises.
Read mode if OE becomes "0" before rising
And the signal ALS2B does not become a pulse, and the address
Is kept as it is. The voltage V_ppIs set to high voltage
V so that the address latch is released._ppPulse generation
Address line when limiting with the output signal RSTAL of the circuit
FIG. 4 shows a specific example of the switch pulse generating circuit. As described above, two control signal bars
Even if mode switching is performed using only CE and OE
No malfunction occurs. [0061] According to the present invention, two control signals C
E. Malfunction even if mode is switched using OE
Crop can be prevented.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing a configuration of an embodiment of the first invention. FIG. 2 is a block diagram showing details of main components of the embodiment shown in FIG. 1; FIG. 3 is a timing chart for explaining the operation of the embodiment shown in FIG. 2; FIG. 4 is a timing chart for explaining the operation of the embodiment shown in FIG. 2; FIG. 5 is a timing chart for explaining the effect of the embodiment shown in FIG. 2; FIG. 6 is a block diagram showing a configuration of one embodiment of the second invention. FIG. 7 is a circuit diagram showing a specific example of a V _pp pulse generation circuit and an address latch pulse generation circuit according to the embodiment shown in FIG. 6; FIG. 8 is a timing chart for explaining the operation of the embodiment shown in FIG. 6; FIG. 9 is a block diagram showing the configuration of an embodiment of the third invention. FIG. 10 is a circuit diagram showing a specific example of a read mode recognition circuit according to the embodiment shown in FIG. 9; FIG. 11 is a circuit diagram showing a specific example of an address latch pulse generation circuit according to the embodiment shown in FIG. 9; FIG. 12 is a circuit diagram showing a specific example of an address buffer according to the embodiment shown in FIG. 9; FIG. 13 is a timing chart for explaining the operation of the embodiment shown in FIG. 9; FIG. 14 is a circuit diagram showing another specific example of the address latch pulse generation circuit. FIG. 15 is a timing chart illustrating operation of a conventional storage device. FIG. 16 is a timing chart illustrating operation of a conventional storage device. FIG. 17 is a flowchart illustrating an all-bit erasing operation of the flash E ² PROM. FIG. 18 is a block diagram illustrating a configuration of another conventional storage device. 19 is a timing chart illustrating operation of the storage device illustrated in FIG. 20 is a circuit diagram illustrating details of main components of the storage device illustrated in FIG. 18; FIG. 21 is a timing chart illustrating a problem of the storage device illustrated in FIG. 18; FIG. 22 is a timing chart illustrating a problem of the storage device illustrated in FIG. FIG. 23 is a timing chart illustrating the operation of still another conventional storage device. FIG. 24 is a timing chart illustrating the operation of still another conventional storage device. FIG. 25 is a circuit diagram showing another specific example of the Vpp pulse generation circuit according to the second invention. [Description of Signs] 1 control circuit 2 I / O buffer 3 command register circuit 4 auto mode control circuit 5 write / erase control circuit 6 erase circuit 7 row decoder 8 sense amplifier 9 column gate 10 memory cell array

   ────────────────────────────────────────────────── ─── Continuation of front page    (72) Inventor Hiroto Nakai             1 Komukai Toshiba-cho, Saiwai-ku, Kawasaki-shi, Kanagawa             Toshiba Microelectronics             Inside (72) Inventor Shigeru Matsuda             1 Komukai Toshiba-cho, Saiwai-ku, Kawasaki-shi, Kanagawa             Toshiba Microelectronics             Inside (72) Inventor Tadayuki Taura             1 Komukai Toshiba-cho, Saiwai-ku, Kawasaki-shi, Kanagawa             Toshiba Microelectronics             Inside (72) Inventor Sachiko Komino             1 Komukai Toshiba-cho, Saiwai-ku, Kawasaki-shi, Kanagawa             Toshiba Microelectronics             Inside F term (reference) 5B025 AD01 AD04 AD05 AD15 AE08

Claims (1)

Claims: 1. A mode recognizing means for recognizing a command write mode or a read mode based on timings of two control signals, and whether an address is latched based on an output of the mode recognizing means. Latch command signal generating means for generating a command signal for instructing, and an address buffer for latching an address based on an output of the latch command signal generating means and holding or transferring the latched address. A nonvolatile semiconductor memory device characterized by the above-mentioned.