JP2003098247A - Radar system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To restrain and remove an interference wave intruded from a side lobe of a radar antenna over a wide band. SOLUTION: Received signals from a main antenna 1 and a transceiving part 2, and an SLC antenna 3 and an SLC reception part 4 are supplied to an SLC processing part 5, to conduct interference wave restraining operation. The SLC processing part 5 executes the interference wave restraining operation repeatingly over plural times M within a data receiving period in one cycle time T supplied from the transceiving part 2 and the SLC reception part 4. The wide band interference wave, or the interference wave of which the frequency varies is effectively restrained and removed by repeating the interference wave restraining operation within the cycle time T, as shown hereinbefore, and a target signal is exactly displayed thereby on a display 6.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an improvement of a radar device having an interference wave suppression function.

[0002]

2. Description of the Related Art Conventionally, in order to avoid detection by a partner radar, various radio wave jamming (ECM: Electric)
Counter Measures is considered, and the radar side against this also uses various radio wave interference removal operations (ECC) as a countermeasure against the radio wave interference.
M: Electric Counter Count
r Measures) has been devised.

In the ECCM, the SL that removes the interference wave from the side lobe for the continuous interference wave that enters the radar side through the side lobe of the antenna beam.
C (Sidelobe Cancer) is known as one effective means.

FIG. 9 is a block diagram showing the main part of a conventional radar device equipped with an SLC.

That is, a conventional radar apparatus equipped with an SLC has a main antenna 1 which forms an antenna beam by a parabolic antenna or the like and rotates and scans, and the main antenna 1.
And an SLC antenna (auxiliary antenna) 3 forming an omnidirectional antenna pattern and its SLC receiver 4, and a transmitter / receiver 2
And an SLC processing unit 5 that is connected to the SLC reception unit 4 and that suppresses an interfering wave from the side lobe and outputs a reception signal,
Display 6 for displaying the received signal from which interference waves have been suppressed and removed
And a reference signal generator 7 for generating a clock signal R having a cycle r and supplying the clock signal R to the transmitter / receiver 2 and the SLC receiver 4.

The transmitter / receiver 2 connected to the main antenna 1 is
As shown in FIG. 9 (b), the transmission / reception switch 2 a, the low-noise high-frequency amplifier 2 b for amplifying the reception signal supplied through the transmission / reception switch 2 a, and the local oscillation signal from the local oscillator 8 are mixed. Mixer 2c for generating an intermediate frequency (IF) signal
, An intermediate frequency amplifier 2d for amplifying the IF signal, and a detector 2e for detecting in synchronization with the clock signal R from the reference signal generator 7 and supplying the detected output signal to the SLC processing unit 5.
It consists of and. A transmitter 9 is connected to the transmission / reception switch 2a.

On the other hand, the SL connected to the SLC antenna 3
The C receiver 4 also performs detection in synchronization with the clock signal R of the cycle r supplied from the reference signal generator 7, and the detected output is supplied to the SLC processing unit 5.

FIG. 10 is a diagram for explaining the interference wave suppressing action in the SLC processing section 5. As shown in FIG. 10 (a), the SLC is applied to the directional antenna pattern 1a of the main antenna 1 shown by the solid line. The antenna 3 forms an omnidirectional antenna pattern 3a including the side lobe level in the directional antenna pattern 1a, as indicated by the chain line.

The main beam of the main antenna 1 is directed at a certain angle azimuth P in the direction normal to the antenna aperture surface, and the angle of incidence of the interference wave J with reference to the angle azimuth P, that is, the incident angle θ.
, The main antenna 1 and the SLC antenna 3 respectively
The interfering waves Jm and Js received by the main antenna 1 and the SLC antenna 3 when being received by are supplied to the SLC processing unit 5 via the transmitting / receiving unit 2 and the SLC receiving unit 4, respectively.

The function of the SLC processing section 5 is to control the level of the antenna pattern 3a at the incident angle θ so that the interfering wave Js received by the SLC antenna 3 at the incident angle θ is
The interference wave Jm received through the side lobe of the main antenna 1 is compared, and the amplitudes are controlled so as to have the same amplitude and the same phase, and the subtraction between the two reception signals is performed.

Therefore, the SLC processing section 5 is set to a state in which the incoming radio wave is received by the arithmetic processing by the receiving antenna pattern having the null point (PN) at the incident angle θ as shown by the broken line in FIG. 10 (b). Therefore, the interfering wave J (Jm, Js) is suppressed and removed by subtracting the interfering waves Jm, Js of the same amplitude and the same phase, and the target detection signal arriving from the remaining angle azimuth P remains appropriately and is displayed on the display unit 6. Displayed on the supply.

The SLC processing section 5 is constructed as shown in FIG. 9A and has a subtracter 5A and an S connected to the transmitting / receiving section 2.
The SLC processor 5B connected to the LC receiver 4 and the interference wave Jm received via the main antenna 1 at the operation timing of the clock signal R having the cycle r supplied from the reference signal generator 7. The received output signal including the subtractor 5
A received output signal including the interference wave Js received by the SLC antenna 3 is supplied to the SLC processor 5B.

The SLC processor 5B is provided with first and second multipliers 5 to which the received signal from the SLC receiver 4 is branched and supplied.
B1, 5B2 and its first and second multipliers 5B1, 5B
And a narrow band filter 5B3 connected between the two.

The operating principle of the SLC processing unit 5 is that the disturbance wave Js (n-1) supplied to the first multiplier 5B1 of the SLC processing unit 5B at a certain timing is represented by a complex number generated by the narrow band filter 5B3. After being multiplied by the weight W (n) (hereinafter referred to as complex weight)
The interference wave Jm (n-1) from the main antenna 1 is subtracted.

Therefore, the residual component Jo (n) of the target signal or the like output from the subtractor 5A is expressed by the following equation (1). In the description of the present specification, it is assumed that the signals such as the interfering wave J (Jm, Js), the weight W (n), and the residual component Jo are all displayed as vectors.

Jo (n) = Jm (n-1) -W (n) .Js (n-1) (1) The residual component Jo (n) is displayed on the display 6 and at the same time
After being multiplied (correlation processing) with the interfering wave Js (n-1) received by the SLC antenna 3 and supplied to the multiplier 5B2, it is supplied to the narrow band filter 5B3 to generate a complex weight W (n). To be done.

The narrow band filter 5B3, as shown in FIG. 9A, multiplies the multiplication output of the second multiplier 5B2 by a constant coefficient value A1 in the amplifier 5B3a, and then adds it to the adder 5B.
The complex weight W (n), which is configured to be supplied to B3b and is output from the adder 5B3b, is supplied to the first multiplier 5B1 and, after being passed through the delay circuit 5B3c having a cycle r, is fixed by the amplifier 5B3d. After being multiplied by the coefficient value A2 of, the feedback is supplied to the adder 5B3b to form a narrow band filter. Therefore, the complex weight W (n)
Is expressed by the following equation (2).

W (n) = A1.Js (n-1) .Jo (n-1) + A2.W (n-1) (2) In the radar device shown in FIG. 9A, the main antenna 1 is Although mechanically rotationally scans in the azimuth direction and the like, the interfering wave removing function of the SLC is also adopted in a radar device including an electronic scanning antenna.

FIG. 11A is a block diagram of a radar apparatus equipped with an interference wave removing function by SLC and comprising an electronic scanning antenna in which a main antenna is arranged with a large number of antenna elements in an array.

That is, in the radar device shown in FIG. 11A, the SL is placed on the same antenna opening surface as the main antenna 1.
The C antenna 3 is arranged to suppress the interference wave received in the side lobe.

The main antenna 1 is composed of a plurality (N) of array antenna elements 1A1 to 1AN, and these plurality (N) of array antenna elements 1A1 to 1AN are also the same as a plurality (N) of the transmitting / receiving section 2. Transmitter / receiver circuits 2A1-2A
Correspondingly connected to N, the outputs of the transmission / reception circuits 2A1 to 2AN are supplied to the synthesis circuit 2B of the transmission / reception unit 2 to be synthesized.

Each transmitting / receiving circuit 2A (2A1 to 2AN) is
Each antenna element 1 is configured as shown in FIG.
The RF transmission / reception module 2Aa connected to A (1A1 to 1AN) is connected to the mixer 2Ac via the transmission / reception switch 2Ab.
Connected to.

In the mixer 2Ac, the received signal is mixed with the local oscillation signal of the local oscillator 8 to become an intermediate frequency (IF) signal, and the IF signal is subjected to the unnecessary frequency component removal by the bandpass filter 2Ad, and then A / D. Digital I via converter 2Ae
The signal is supplied to the / Q detector 2Af. The digital I / Q detection circuit 2Af receives the 0 ° and 90 ° local oscillator signals from the local oscillator 8 and orthogonalizes the received digital IF signal to the I signal.
/ Q signal and supplies to the synthesis circuit 2B.

As shown in FIG. 11A, the center position of the phase of the received signal at the main antenna 1 is set to point A, and the distance between the phase center position A and the SLC antenna 3 is set to D,
Letting θ be the incident angle of the interfering wave J (Jm, Js) and C be the radio wave propagation velocity, the interfering wave J (Jm, Jm, received at the incident angle θ
Js), a delay time Δt expressed by the following equation (3) is provided between the received interference wave Jm at the phase center position A of the main antenna 1 and the interference wave Js received by the SLC antenna 3. Occurs.

Δt = Dsin θ / C (3) Further, since the interference wave Jm received by the main antenna 1 is expressed by the following equation (4), the interference wave Js received by the SLC antenna 3 is given by the following (5). It can be represented by a formula.

Jm = Am · exp (j2πf · t) (4) Js = As · exp (j2πf (t + Δt)) (5) where Am and As are the amplitudes of the disturbing waves Jm and Js, respectively, and f is the disturbing wave. The frequency of the wave J (Jm, Js) is shown.

Therefore, the interfering wave Js received by the SLC antenna 3 is converted by the above equations and expressed as the following (6).

Js = As.exp (j2.pi.f.t) .exp (jKD.sin.theta.) (6) However, since K is the wave number (= 2.pi ./. Lamda.), The interfering wave J
It shows that it depends on the wavelength λ of (Jm, Js).

Since the phase difference between the main antenna 1 and the SLC antenna 3 is KD · sin θ, the phase difference (KD · sin θ) also depends on the wavelength λ of the interfering wave J (Jm, Js). And change.

The respective interfering waves J (Jm, Js) received by the main antenna 1 and the SLC antenna 3 are supplied to the SLC processing section 5, where the amplitude and the phase are aligned and subtracted as described above. Therefore, the interfering wave is suppressed and removed, and the residual component Jo of the desired target signal or the like is output and displayed on the display unit 6.

As described above, when the main antenna 1 is an array antenna, the phase difference (kD · sin θ) between the phase center position A of the main antenna 1 and the SLC antenna 3 is the wavelength λ of the interfering wave J, That is, it changes according to the frequency f.

In the suppression of the interfering wave J in the SLC processing unit 5, since the amplitudes and phases of the interfering waves Jm and Js received by the main antenna 1 and the SLC antenna 3 respectively are made uniform, the subtraction is performed. When the phase difference between the interfering waves Jm and Js received by the antenna 3 is constant, the SLC processing unit 5 performs phase matching,
The interfering wave J is suppressed, and the desired target signal or the like is displayed on the display 6 as the residual component Jo (n).

The same applies to the radar device shown in FIG.

[0034]

As described above, S
As shown in FIG. 11 (a), the radar device equipped with the LC has the main antenna 1 for the interfering wave J incident at the incident angle θ.
And SLC antenna 3 phase difference (KD · sin θ)
Occurs.

Therefore, the main antenna 1 and the SLC antenna 3
The interference wave J having a constant phase difference is suppressed between the interference waves Jm and Js respectively received at, but the broadband interference wave or the interference wave whose frequency changes on the time axis is received. Since the phase difference between the interfering waves Jm and Js is not determined, the variation of the difference is supplied to the display unit 6, and there is a problem in that only the target signal cannot be accurately displayed in the environment of the interfering waves. there were.

Therefore, it is an object of the present invention to provide a radar device which can obtain a sufficient suppression effect even for a frequency change or a wideband interference wave.

[0037]

In order to solve the above-mentioned conventional problems, the radar apparatus according to the present invention comprises a main antenna and an S antenna.
A unit that introduces each received signal from the LC antenna and outputs each received data that is serially synchronized in synchronization with the clock signal of the period T, and introduces each received data output by this unit and introduces a plurality of ( 1 / M cycle (T / M)
And an interfering wave suppressing means for repeatedly performing the interfering wave suppression calculation to output residual wave data.

As described above, in the radar device of the present invention, in the interference wave suppressing means, a plurality (M) of periods T of the received data are obtained.
Since the interference wave suppression calculation is executed a plurality of times (M) times in a cycle of 1 / T, it is possible to obtain a high effect of suppressing broadband interference waves and to significantly reduce the residual output of the interference waves themselves. Can be reduced.

[0039]

BEST MODE FOR CARRYING OUT THE INVENTION An embodiment of a radar device according to the present invention will be described below in detail with reference to FIGS. It should be noted that the same components as those of the conventional configuration shown in FIGS. 9 to 11 are denoted by the same reference numerals and detailed description thereof will be omitted.

FIG. 1 and FIG. 2 are main part configuration diagrams showing a first embodiment of a radar device according to the present invention. See also FIG.
4 is a timing chart showing operation output signals and the like of each part in the device shown in FIGS. 1 and 2, and FIG. 4 is an operation explanatory diagram of the device shown in FIGS. 1 and 2.

That is, as shown in FIGS. 1 and 2, the radar apparatus according to the first embodiment is arranged with a distance D between the main antenna 1 composed of an array antenna and the main antenna 1. The SLC antenna 3, the transmitter / receiver 2 and the SLC receiver 4 connected to the main antenna 1 and the SLC antenna 3, respectively, and the SLC processor 5 connected to the output terminals of the transmitter / receiver 2 and the SLC receiver 4. , A resampling circuit 51 connected to the SLC processing unit 5, a display 6 connected to the resampling circuit 51, and a cycle r.
Of the SLC processing unit 5, the frequency dividing circuit 71, and the reference signal generator 7 that supplies the clock signal R to the counter circuit 8. A transmitter 9 is connected to the transmitter / receiver 2.

FIG. 3 generated by the reference signal generator 7.
The clock signal R having the cycle r shown in FIG.
3, the frequency dividing circuit 71 generates a timing (frequency dividing) signal Dr having a period T (= M × r) that is a plurality (M) times the period r as shown in FIG. 2 and the SLC receiver 4 to drive them.

Therefore, as shown in an enlarged view of the main part in FIG. 2, the signal including the interfering wave Jm received by each antenna element 1A (1A1 to 1AN) of the main antenna 1 at the angle of incidence θ is , The transceiver circuit 2A of the transceiver unit 2 (2A1 to 2A
As shown in FIG. 3C, the reception data Jm of the cycle T is formed by the detection and the A / D conversion based on the timing signal Dr of the cycle T in N), and the SLC processing part 5 is formed via the synthesis circuit 2B. Is supplied to.

Also in the SLC antenna 3 which is arranged at a distance D from the main antenna 1, the incident angle θ is also the same.
The signal including the interfering wave Js received at the angle is subjected to detection and A / D conversion based on the timing signal Dr of the cycle T in the SLC receiving unit 4, and as shown in FIG.
The reception data Js of the cycle T is generated and supplied to the SLC processing unit 5.

The SLC processing section 5, as shown in FIG.
A subtractor 5A connected to the output terminal of the transmitter / receiver 2, and an SLC connected between the subtractor 5A and the SLC receiver 4
It is composed of a processor 5B.

The received data Jm from the transmitter / receiver 2 is SLC
The subtractor 5A of the processing unit 5 and the received data Js from the SLC receiving unit 4 are supplied to the SLC processing unit 5B.

Subtractor 5A and SLC of SLC processing unit 5
The processor 5B is driven by the clock signal R supplied from the reference signal generator 7, executes a plurality of (M) times of interference wave suppression calculation within the period T, and is shown in FIG. 3 (e) each time. As described above, the residual wave data Jo1 after the interference wave is suppressed is output and supplied to the resampling circuit 51.

The interference wave suppressing operation in the SLC processing unit 5 will be described with reference to FIG. 4. As described above, in the SLC processing unit 5, the reception data Jm and Js of the cycle T are transmitted a plurality (M) times. Since the interference wave suppression calculation of is executed, the degree of interference wave suppression is gradually improved, and the absolute value of the residual wave data | Jo1 |
That is, the interfering wave residual power decreases during the period T, as indicated by the broken line in FIG.

That is, in the SLC processor 5B in the SLC processing section 5, the received data Jm, Js input is inputted in the cycle T.
Each time it is updated, the received data Jm,
The phase term of Js changes and the residual power increases once. However, the complex weight W of the SLC processor 5B is set to the interference wave Jm by a plurality (M) times of interference wave suppression calculations within the period T.
Is updated so as to suppress and remove more, the residual wave data | Jo1 | changes on the sawtooth in the cycle of cycle T.

The resampling circuit 51 receives the residual wave data | Jo1 | when the minimum value is shown by the timing signal of the period T shown in FIG. (G) and FIG. 4 (b), the residual wave data (0M, 1M, 2M, ...) Of the last cycle r in the cycle T is selected, and this is output data for display | Jo2 | Is displayed on the display unit 6.

As described above, according to the first embodiment,
In the SLC processing unit 5, the interference wave suppression calculation corresponding to the SLC antenna 3 is executed and output a plurality of (M) times in the reception data of the cycle T. Therefore, the residual wave data | J
The residual wave data | Jo1 | when the value of o1 | is the smallest and the interference wave is most suppressed can be displayed on the display 6 as the output data for display | Jo2 |.

Therefore, even in a wideband interference environment,
Sufficient suppression performance for the interfering wave is obtained, and the target can be accurately detected.

In the first embodiment, the SLC
It is possible to further reduce the value of the residual wave data | Jo1 | within the period T by increasing the number of calculations of the interference wave suppression in the processing unit 5, but if the residual component is sufficiently small, the original purpose is achieved. It is also possible that the target signal component is suppressed more than necessary.

Therefore, a radar apparatus according to a second embodiment of the present invention constructed so as to effectively suppress only an interfering wave without excessively suppressing a target signal component will be described with reference to FIGS. Explain.

In the following description, the description of the points common to the configuration and operation shown in the first embodiment will be omitted, and the description will focus on the differences from the first embodiment. .

FIG. 5 shows the structure of the radar apparatus according to the second embodiment. The main difference from the first embodiment is that the counter circuit 8 in the first embodiment is replaced by the counter circuit 8 shown in FIG. The timing control circuit 10 and the threshold level for the amplitude, that is, the threshold level Th.
That is, a threshold value level setting circuit 11 for setting the (reference value) and controlling the timing control circuit 10 is newly provided.

The timing control circuit 10 has a so-called transversal filter (t) for introducing the residual wave data Jo1 from the SLC processing unit 5 as shown in FIG.
and a comparison circuit 102 for introducing the filter output of the transversal filter 101 and comparing the output level thereof with a threshold level Th preset by the threshold level setting circuit 11, and this comparison circuit. The timing selection circuit 103 receives the output signal of the signal 102 and controls the driving of the resampling circuit 51.

A clock signal R having a cycle T supplied from the reference signal generator 7 and a timing signal Dr having a cycle r supplied from the frequency dividing circuit 71 are introduced into the timing selection circuit 103, and output from the comparison circuit 102. Based on the above, the resampling circuit 51 is controlled by outputting the selection timing signal of the cycle T.

The operation of the radar device shown in FIGS. 5 and 6 will be described with reference to the timing chart shown in FIG. 7 and the operation characteristic diagram shown in FIG.

Similar to the first embodiment, the reference signal generator 7 and the frequency dividing circuit 71 respectively include the clock signal R shown in FIG. 7A and the timing signal Dr shown in FIG. 7B. Since the transmission / reception unit 2 and the SLC reception unit 4 are generated and derived, the transmission / reception unit 2 and the SLC reception unit 4 form the reception data Jm and Js shown in FIGS. It is supplied to the processing unit 5.

Based on the clock signal R having the cycle r from the reference signal generator 7, the SLC processor 5 receives the received data Jm,
The interference wave suppression calculation for Js is sequentially executed, and FIG.
The residual wave data Jo1 shown in (1) is generated and supplied to the resampling circuit 51 and the transversal filter 101 of the timing control circuit 10.

As is well known, the transversal filter 101 includes (n + 1) delay circuits (a1 to an) for sequentially storing input data and (n + 1) tap positions before and after the delay circuits (a1 to an). ) Designated gains (W0 to Wn) are respectively multiplied by (n + 1) multiplication circuits (b1 to b (b + 1)) and n addition circuits (c).
1 to cn) form a digital filter, and the average value thereof is calculated by weighted addition of the weighted past n times of data and supplied to the comparison circuit 102.

As shown by the solid line in FIG. 8A, the residual wave component Jo output from the transversal filter 101 is series-wise by executing the interference wave suppression calculation a plurality of (M) times within the period T. Decrease to.

Therefore, as described above, since excessive interference wave suppression also suppresses the target signal, the comparison circuit 102
Compares the amplitude level of the residual wave component Jo output from the transversal filter 101 with a threshold level Th (reference value) preset by the threshold level setting circuit 11, and detects the residual wave component Jo. When the threshold value level becomes Th or less, it is assumed that the interfering wave is sufficiently suppressed, and the comparison circuit 102 drives the timing selection circuit 103.

Since the timing selection circuit 103 which receives the signal from the comparison circuit 102 controls the resampling circuit 51, the residual wave component Jo is reduced and the threshold level Th is reduced.
8A, as shown by the alternate long and short dash line in FIG. 8A, the first interference wave suppression calculation (M =
The residual wave data Jo1 of 1) is selected as the display output data Jo2 and is supplied to the display 6.

In other words, the timing control circuit 10 reduces the amplitude of the residual wave data Jo1 and reduces the threshold value T which is the reference value.
Until the time becomes equal to or less than h, it is assumed that the interfering wave is not sufficiently suppressed, and the M-th operation result (0M, 1M, 2M, ...) Is selected as shown in FIG. 8C. After the resampling circuit 51 is controlled to reach the threshold level Th, as shown in FIG. 8D, the first time (M
= 1) the residual wave data Jo1 of the calculation result (11, 21, 31, ...) Is selected as the display output data Jo2 and is supplied and displayed on the display unit 6. Therefore, the target signal is excessively suppressed and displayed. Can be avoided. Note that, in FIG. 8, the characteristic curve shown by the broken line Q is the indicator 6 in the conventional radar device described with reference to FIGS. 9 to 11.
It shows the residual wave component J 0 of the broadband interference wave supplied to, which indicates that the interference wave is displayed as it is with almost no suppression.

In the above description, the comparison circuit 102 of the transversal filter 101 supplies the comparison result of the amplitude level of the residual wave component Jo and the threshold value Th to the timing selection circuit 103. Based on the timing selection circuit 103 shown in FIG.
The selection timing signal shown in (g) is supplied to the resampling circuit 51. Therefore, the resampling circuit 51
7 (h) or 7 (g) (that is, FIG.
Display output data J shown in (c) or FIG. 8 (d))
o2 is supplied and displayed on the display unit 6.

As described above, according to the second embodiment, whether or not the interfering wave has been sufficiently suppressed is determined by a preset reference value, that is, a threshold level Th.
In the state where the interference wave is automatically suppressed by the comparison with, and the interference wave is sufficiently suppressed, the calculation result of the M = 1st time is selectively displayed thereafter, so that the target signal is prevented from being suppressed more than necessary. be able to.

As described above, according to the radar device of the present invention, the wideband interference wave or the interference wave whose frequency characteristic changes can be accurately suppressed and removed by repeating the interference wave suppression calculation a plurality of times in the SLC processing section. Along with
The residual power of the interference wave can be effectively reduced, and the true target signal can be properly displayed.

Further, in the above-mentioned first and second embodiments, it is explained that the broadband interference wave or the interference wave whose frequency characteristic changes on the time axis is suppressed. However, according to the radar device of the present invention, The same effect can be obtained even when the interference wave suppression performance is deteriorated due to the difference in frequency characteristics between the constituent circuits of the receiving system of the antenna 1 and the SLC antenna 3.

In summary, according to the radar apparatus of the present invention, the interference wave is effectively suppressed by repeating the interference wave suppression calculation, and the target can be detected even in a wideband interference wave environment.

[0072]

According to the radar apparatus of the present invention, it is possible to appropriately and sufficiently suppress the interference wave even in the interference environment over a wide band by the interference wave suppression calculation repeatedly executed.
This is a large effect that can be obtained in practical use.

[Brief description of drawings]

FIG. 1 is a main part configuration diagram showing a first embodiment of a radar device of the present invention.

FIG. 2 is a detailed configuration diagram of a main antenna and an SLC antenna shown in FIG.

FIG. 3 is a timing chart of an interference wave removing operation in the device shown in FIG.

FIG. 4 is an explanatory view of the operation of the apparatus shown in FIG.

FIG. 5 is a main part configuration diagram showing a second embodiment of a radar device of the invention.

6 is a configuration diagram of the timing control circuit shown in FIG.

7 is a timing chart of an interference wave removing operation in the apparatus shown in FIG.

FIG. 8 is an explanatory diagram of an interference wave removing operation in the device shown in FIG.

FIG. 9 is a configuration diagram of a conventional radar device that employs SLC.

FIG. 10 is an operation explanatory diagram of the apparatus shown in FIG.

FIG. 11 is a configuration diagram of another conventional radar device that employs SLC.

[Explanation of symbols]

1 main antenna 2 Transmitter / receiver (received data output means) 3 SLC antenna 4 SLC receiver (received data output means) 5 SLC processing unit (interference wave suppression means) 51 resampling circuit (resampling means) 6 Display 7 Reference signal generator 71 frequency divider 8 counter circuits 9 transmitter 10 Timing control circuit 11 Threshold setting circuit

Claims (3)

[Claims] 1. A means for introducing each reception signal from a main antenna and an SLC antenna, and outputting each reception data which is sequentially synchronized with a clock signal of a period T, and each reception data output by this means. A radar device comprising: an interference wave suppression unit that introduces and repeatedly performs interference wave suppression calculation at a cycle (T / M) that is a multiple (M) of the cycle T and outputs residual wave data. . 2. Resampling means for introducing the residual wave data output from the interference wave suppressing means, and selecting and outputting the residual wave data by the interference wave suppressing operation performed last in the period T. The radar device according to claim 1, wherein: 3. When the amplitude level value of the residual wave data becomes equal to or lower than a preset reference value, the residual wave data by the interference wave suppression calculation first performed within the period T is selected and output. 2. The radar device according to claim 1, further comprising resampling means for performing the resampling.