JP2003091564A - Layout method for semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a layout device for a semiconductor device capable of shortening time till completion of layout. SOLUTION: In a layout process, a transistor having a dimension size complying with circuit information is formed at a desired place. A viacon for power connection is extracted from the circuit information to be connected to the transistor, and the transistor is laid out to a prescribed position to fill design standards for the semiconductor device. Signal wiring is connected between the transistors to fill the design standards. In an inspection process, if these are laid out in the same wiring route as in the circuit information or not is determined. When it is determined that an error exists in the wiring route, a step to change size of the transistor is taken, and signal wiring is changed to comply with the circuit information. These are repeatedly executed till it is determined that there is no error in the wiring route. When it is determined that there is no error in the wiring route, a power line is automatically connected to the viacon for power connection.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device layout method for laying out a semiconductor device based on circuit information.

[0002]

2. Description of the Related Art Conventionally, as a technique of this kind of field, there has been one as shown in FIG. 12, for example.

FIG. 12 is a flowchart showing a conventional layout method. 13 is a circuit diagram showing an example of an operational amplifier, and FIGS. 14A to 14D are layout pattern images when the conventional layout method of FIG. 12 is realized by using the circuit of this operational amplifier. It is a figure which shows an example. A conventional layout method will be described with reference to these drawings.

First, for example, after obtaining the circuit information of the operational amplifier shown in FIG. 13 as the circuit information (step S10).
1), as a layout step, transistors 211 to 21 having a dimension size according to this circuit information
3, 221 to 224 are created at arbitrary places (step S102, FIG. 14A).

Next, the transistors 211-213,
Main power supply wirings 230 and 231 for supplying power to the transistors are formed near 221 to 224, and the transistors 211 to 213 and 2 are formed from the main power supply wirings 230 and 231.
The power supply wiring is connected to 23 and 224 (step S10).
3, FIG. 14 (b)). Then, the signal wirings 240 and 241 between the transistors are connected (step S104, FIG.
4 (c)).

In this state, the layout has a margin and the chip size becomes large. Therefore, in order to reduce (optimize) the layout area, first, the transistors are moved so as to fill the empty area by satisfying the design standard. (Step S105), the power supply wiring connected to the transistor is moved accordingly (step S106), and the signal wiring connected between the transistors is moved (step S107, FIG. 14D).

The subsequent verification process of the created layout is performed. In the verification process, mainly verification of design standards, short-circuit verification of power supply wiring, and verification of wiring route are performed. First, the design standard is verified (step S108). If the design standard is verified and a violation of the standard is found, the power supply wiring connected to the transistor is changed (step S109),
The signal wiring connected between the transistors is changed (step S110) to correct the reference violation.

If there is no violation of the design criteria, then short-circuit verification of the power supply wiring is performed (step S111). If short-circuit verification of the power supply wiring is performed and a violation is found, the power supply wiring connected to the transistor is changed again (step S109), and the signal wiring connected between the transistors is changed (step S110) to confirm the violation. Make corrections.

If there is no short circuit in the power supply wiring, the wiring path is next verified (step S112). Make sure that the wiring route is the same as the circuit information. If a connection mistake in the wiring path is found, the size of the transistor is changed (step S113), the power supply wiring connected to the transistor is changed (step S109), and the signal wiring connected between the transistors is changed (step S109). S110), the connection mistake of the wiring route is corrected. If the wiring route is the same as the circuit, the layout is completed.

FIG. 15 is a flowchart showing a conventional large-scale cell layout method.

When laying out a large-scale cell, first, after obtaining circuit information (step S101), the above-mentioned steps S102 to S1 are performed for each small unit cell.
The layout process is executed while using the layout method of 07 (step S201).

Next, as a unit cell synthesizing step, power supply wirings between the unit cells are connected (step S202), signal wirings between the unit cells are connected (step S203), and the unit cells are moved. (Step S204), the power supply wiring between unit cells is moved (Step S205),
The signal wiring between unit cells is moved (step S20).
6).

After that, as a verification process, the above step S
The layout of the large-scale cell is completed by performing the same processing as 108 to step S113.

[0014]

However, the conventional layout method described above has a problem that it takes a long time to complete the layout.

Specifically, as a time ratio when the above-described conventional layout method is performed, FIG.
The ratio between the layout process and the verification process is shown in (a). As is clear from the figure, conventionally, the layout process is about 90% and the verification process is about 10%, and the most time is spent on the layout process. This shows an example in which there is one violation each in the verification process, but if the number of violations increases, the period will be further extended.

Note that FIG. 16B shows a breakdown of the period of each step in the layout process, and FIG.
Shows the breakdown of the period of each step in the verification process.

The present invention has been made to solve the above-mentioned conventional problems, and an object of the present invention is to provide a layout method of a semiconductor device which can shorten the period until the layout is completed. .

[0018]

In order to achieve the above object, in a layout method of a semiconductor device according to a first invention, a layout step of laying out the semiconductor device based on circuit information of the semiconductor device, In the layout method of the semiconductor device having a verification step for verifying the layout performed in the layout step, the layout step, a transistor creation step of creating a transistor having a dimension size according to the circuit information at any location, A step of creating a via contact for extracting power connection via contact data, which is power supply wiring connection information for connecting a power supply wiring to the transistor, from the circuit information and connecting the transistor to the transistor, and so as to meet the design criteria of the semiconductor device. Transistor that places the transistor in place And a signal wiring connecting step for connecting the signal wiring between the transistors so as to satisfy the design criteria, and the verification step determines whether or not the wiring path is the same as the circuit information. If the wiring route verification step determines that there is an error in the wiring route, the step of changing the size of the transistor and the signal wiring are changed so as to follow the circuit information. Step is repeated until the wiring route verification step determines that there is no error in the wiring route, and when the wiring route verification step determines that there is no error in the wiring route, the power supply connection is performed. The power supply wiring automatic generation step of automatically connecting the power supply wiring to the via contact data is performed.

A semiconductor device layout method according to a second aspect of the present invention is the same as the semiconductor device layout method described above,
The via contact creating step includes an extracting step of extracting the power supply connecting via contact data from the circuit information, a compaction step of performing a compaction of the entire transistor region created in the transistor creating step, and an extracting step of the extracting step. And a connecting step of connecting the power supply connecting via contact data to the transistor.

A semiconductor device layout method according to a third aspect of the present invention is the same as the semiconductor device layout method described above,
The power supply connecting via capacitor data created in the via capacitor creating step is created exclusively for each power source.

In the semiconductor device layout method according to the fourth aspect of the present invention, division data for dividing the generation area of the power supply wiring generated in the power supply wiring automatic generation step for each power supply is used.

A semiconductor device layout method according to a fifth aspect of the present invention is the semiconductor device layout method described above,
It is characterized in that each power source wiring arranged for each power source and the signal wiring are formed in different wiring layers by using a process capable of using multilayer wiring of three layers or more.

In the semiconductor device layout method according to the sixth aspect of the present invention, the layout process according to any one of claims 1 to 5 is used to perform layout for each unit cell having a plurality of transistors, and then, between the unit cells. A unit cell synthesizing step of connecting by signal wiring is performed, and the verification step and the power supply wiring automatic generating step according to claim 1 to 5 are executed on the result obtained in the unit cell synthesizing step. Characterize.

[0024]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings.

[First Embodiment] FIG. 1 is a flowchart showing a semiconductor device layout method according to a first embodiment of the present invention. 2 is a flowchart showing details of the viacon (viacon: circuit connection information) creation process shown in FIG. 1, and FIG. 3 is a circuit diagram showing an example of an operational amplifier, and FIGS. 2] is a diagram showing an example of a layout pattern image when the layout method according to the present embodiment of FIG. 1 is realized by using the circuit of this operational amplifier. The layout method of this embodiment will be described with reference to these drawings.

First, circuit information is obtained (step S1).
1). This circuit information describes the designed circuit based on a predetermined structure description language, and describes the connection relationship between elements such as transistors and each terminal one by one, and expresses a static circuit network at the transistor level. It has been done. In the present embodiment, for example, the circuit information of the operational amplifier as shown in FIG. 3 is used.

After obtaining the circuit information, as a layout step, first, the transistor information is extracted from the circuit information, and a transistor having a dimension size according to the transistor information is created at an arbitrary location (transistor creating step: step S12). ). In the example shown in FIG. 4A, the transistors 11 to 13 are on the N-Well pattern 10 and the transistors 21 to 24 are on the P-Wel.
Each pattern is created on the l pattern 20.

Next, the power supply wiring connection information (hereinafter referred to as a power supply connecting via capacitor) for connecting the power supply wiring to the created transistor is connected (via capacitor creating step:
Step S13, FIG. 4 (b)).

The step of creating the via capacitors will be described in detail with reference to FIG. 2. First, the power supply connecting via capacitors are extracted from the circuit information (step S21). Next, compaction of the entire transistor region created in the transistor creating step is performed (step S22). This compaction is a process of compressing the redundant portion of the layout pattern while satisfying the design criteria, and the drain or source region of the transistor is also shared. In the example shown in FIG. 4B, the source regions of the transistors 11 and 12 and the source regions of the transistors 21 and 22 are shared.

Then, the extracted power supply connecting via capacitors are connected to the transistors (step S23). Figure 4
In the example shown in (b), the power supply connection via capacitors 31 are connected to the sources of the transistors 11 and 12, the transistor 13, and the transistors 23 and 24, respectively.

In this way, the source data of each transistor is created in advance.

Returning to FIG. 1, following the above via-con creating step, the transistor is moved so as to fill the empty area by satisfying the design standard (transistor moving step: step S14), and further, satisfying the design standard and being empty. Signal wiring between the transistors is connected so as to fill the area (signal wiring connecting step: step S15). In the example shown in FIG. 4C, the signal wiring 4 is provided between the transistors.
1, 42 are connected.

Next, a layout verification process is performed. In this verification step, the wiring route is verified (wiring route verification step: step S16). In this step, it is confirmed whether the layout is the same wiring route as the circuit information.

If a connection mistake in the wiring path is found, the transistor size is changed (transistor changing step: step S17) and the signal wiring connected between the transistors is changed (signal wiring changing step: step S18).
And correct the connection mistake of the wiring route.

If the wiring route is the same as that of the circuit, an automatic generation process for automatically connecting the main power source wiring to the power source connecting via capacitor is performed. That is, in this step, the power supply connecting via capacitor is recognized, and the main power supply wiring is automatically connected to the power connecting via capacitor (power supply wiring connecting step:
Step S19). In the example of FIG. 4D, N-Well
The power supply wiring via-con 31 on the pattern 10 is connected to the VDD power supply wiring 51, and the power supply wiring via-con 31 on the P-Well pattern 20 is connected to the GND power supply wiring 52. Thus, the layout is completed after the automatic generation process.

The most important feature of performing the layout by the layout method of the present embodiment described above is a layout method in which, instead of connecting the transistor to the main power supply wiring, a via-connect dedicated to power supply connection is connected in the layout process. . Then, the power supply wiring is automatically generated after the layout process and the verification process.

With this, since the power supply wiring can be performed immediately before the layout is completed, the conventional power supply wiring moving step can be omitted, and the layout is performed in a state where the transistor spacing, the wiring spacing and the like meet the design criteria in advance.
It is possible to omit the conventional power supply wiring moving step and signal wiring moving step, and it is possible to shorten the period of the layout process, which takes the longest time. Furthermore, since there is no power supply wiring in the layout process, a simple and speedy layout can be performed. Further, since the power supply wiring is automatically connected after the verification process, there is no possibility of short-circuiting of the power supply wiring or violation of the design standard, and therefore the conventional power supply wiring short circuit verification step is also unnecessary.

FIGS. 5 (a) and 5 (b) are diagrams showing a comparison of the temporal ratios of the conventional layout method and the layout method of the present embodiment. FIG. 5 (a) shows the conventional method, and FIG. (B) shows the method of this embodiment.

As is apparent from the figure, by performing the method of this embodiment, it is possible to complete the layout in about 71% of the period of the conventional method. For details, see FIG.
FIGS. 7A and 7B show the breakdown of the step unit period in the layout process, and FIGS. 7A and 7B show the breakdown of the step unit period in the verification process, respectively. And the method of the present embodiment will be shown in comparison.

[Second Embodiment] In the step of connecting the power supply connecting via capacitor to the transistor of the first embodiment, one type of via capacitor for connecting the power source to the transistor is prepared, and N- is generated in the automatic generation process. Although the via capacitors on the Well pattern are used for the VDD power source and the others are used for the GND power source, in the second embodiment, the via capacitors are used for the VDD power source.
It is divided into a via-con for wiring connection and a via-con for GND wiring connection in advance.

FIGS. 8A and 8B are views showing examples of layout pattern images by the layout method of the semiconductor device according to the second embodiment of the present invention.

FIG. 8A shows the state of the signal wiring connecting step (step S15) shown in FIG. 1 above. The transistor 62 is provided on the N-Well pattern 60.
And a transistor 63 is formed on the P-Well pattern 61. And the transistor 6
A signal wiring 69 is connected between the signal wiring via capacitors 65 of the reference numerals 2, 63. Further, the transistor 62 is connected with a via contact 66 for connecting VDD wiring, and the transistor 63 is connected with a via contact 68 for connecting GND wiring.

FIG. 8B shows the state of the power supply wiring connecting step (step S19) after the signal wiring connecting step shown in FIG. 8A, and the VDD pad via capacitors 71 are shown.
The VDD wiring 73 is connected between the transistor and the via-connector 66 for connecting the VDD wiring of the transistor 62. Furthermore, GN
The GND wiring 74 is connected between the D-pad via capacitor 72 and the GND wiring connecting via capacitor 68 of the transistor 63.

In this embodiment, the via capacitors for connecting the power supply to the transistors are divided into the via capacitors for connecting the VDD wiring and the via capacitors for connecting the GND wiring.
In 2), the via-con creating step (step S13), and the transistor moving step (step S14), it is possible to visually perform a layout considering the path of the power supply wiring. Also, when using a plurality of power supplies, the layout of multiple power supply wirings can be easily performed by dividing the types of via capacitors by the number of the power supplies.

[Third Embodiment] In the automatic power generation process of the first embodiment, the power supply wiring via-cons on the N-Well pattern are used for the VDD power supply, and the other parts are used for the GND power supply. In the third embodiment, a division line (a division pattern) for dividing an area where a power supply wiring is generated is used.

FIGS. 9A and 9B are views showing examples of layout pattern images by the layout method of the semiconductor device according to the third embodiment of the present invention.

FIG. 9A shows the state of the signal wiring connecting step (step S15) shown in FIG. 1 above. The power source area dividing line 80 indicates that the area where the power source wiring is generated is the VDD power source side. It is divided into the GND power supply side.

N-Well pattern 8 on the VDD power supply side
1, 83 are created, and transistors 85, 86, 87 are created on the N-Well pattern 81.
Transistors 95, 96 and 97 are formed on the l pattern 83. On the other hand, P-Well is on the GND power supply side.
Patterns 82 and 84 are created, and transistors 88, 89 and 90 are created on the P-Well pattern 82,
Transistors 98 and 9 are provided on the P-Well pattern 84.
9,100 have been created.

The above transistors have the same structure,
For example, a signal wiring 91 is connected between the signal wiring via capacitors 85a of the transistors 85 and 88. Further, the transistors 85 and 88 are connected to via capacitors 85b for power supply connection.

FIG. 9B shows the state of the power supply wiring connection step (step S19) after the signal wiring connection step shown in FIG. 9A, and VD is shown on the VDD power supply side.
Viacon 111 of D pad and transistors 85, 86,
87, 95, 96, 97 power supply wiring connection via capacitors 8
The VDD wiring 120 is connected to the 5b. Further, on the GND power supply side, the via-con 112 of the GND pad and the transistors 88, 89, 90, 98, 99,
Between each of the 100 power supply wiring connecting via capacitors 85b
The ND wiring 130 is connected.

In this embodiment, since the dividing line for dividing the area where the power supply wiring is generated is used, a more ideal power supply path is automatically generated without dividing the type of via capacitors according to the power supply. be able to. Further, even when a plurality of power supplies are used, the layout of multiple power supply wirings can be easily performed by using partition lines (partition patterns) by the number that can divide the power supplies.

[Fourth Embodiment] In the fourth embodiment, three or more layers are further provided on the premise that the method is divided into the via contact for VDD wiring connection and the via contact for GND wiring connection described in the second embodiment. When a process capable of using the Al multi-layered wiring is used, the VDD wiring, the GND wiring, and the signal wiring are configured by different Al layers.

FIGS. 10A to 10E are views showing examples of layout pattern images by the layout method of the semiconductor device according to the fourth embodiment of the present invention.

FIG. 10A shows a layout state at the stage of the via-con creating step (step S13) shown in FIG. 1 above. Transistors 123, 124, 125 are formed on the N-Well pattern 121, P-We
The transistors 126 and 12 are provided on the ll pattern 122.
7,128 have been created. And transistor 1
23, 124, and 125, each of the signal wiring via capacitors 121a is connected to the drain, and VD is connected to the source.
The via contact 121b for D wiring connection is connected.

On the other hand, the transistors 126, 127, 12
In FIG. 8, each signal wiring via capacitor 121a is connected to the drain, and further, a GND wiring connecting via capacitor 122b is connected to the source.

Then, on the layout pattern in this state, as shown in FIGS.
D wiring 140, GND wiring 141 and signal wiring 142,
When 143 is composed of different Al layers, FIG.
The layout is completed as shown in (e).

In this embodiment, when a process capable of using Al multi-layered wiring of three layers or more is used, VDD wiring, G
Since the ND wiring and the signal wiring are configured by different Al layers, it is not necessary to satisfy the design criteria between the power supply wirings or between the power supply wiring and the signal wiring, and the layout can be further reduced. The effect of suppressing noise is also obtained by the parasitic capacitance of the wiring.

[Fifth Embodiment] FIG. 11 shows the fifth embodiment of the present invention.
7 is a flowchart showing a large-scale cell layout method according to the embodiment.

In the case of laying out a large-scale cell, first, after obtaining circuit information (step S11), the layout process is executed for each small unit cell while utilizing the layout method of steps S12 to S15 (step S11). Step S31).

Next, as a unit cell synthesizing step, the signal wiring between each unit cell is connected (step S32). Then, as a verification process, the steps S16 to S
By performing the same process as 18 and performing the same process as step S19 as the automatic generation process, the layout of the large-scale cell is completed.

As a result, in comparison with the conventional large-scale cell layout method shown in FIG. 15, the steps described above can be omitted in the layout process and the verification process, and the unit cell synthesizing process can be performed. In step S202, connection of power supply wiring between unit cells (step S202), movement of unit cells (step S204), movement of power supply wiring between unit cells (step S205), and movement of signal wiring between unit cells (step S206). Since each conventional step of 1) is omitted, it is possible to easily perform layout in the layout of a large-scale cell, and it is possible to significantly reduce the layout period.

[0062]

As described in detail above, according to the inventions of claims 1 and 2, since the power supply wiring is performed immediately before the layout is completed, the processing such as the movement of the power supply wiring is not necessary, and it is simple and speedy. Layout can be performed. Furthermore, since the power supply wiring is automatically performed after the verification process, there is no short circuit in the power supply wiring or violation of design standards,
High quality layout is possible. Further, since the layout is performed in a state where the design standard is satisfied in advance, the design standard verification is not necessary, and since the power supply wiring is automatically generated, the short-circuit verification of the power supply wiring is not necessary, so that the verification process period can be shortened. As a result, by executing the layout method of the present invention, it is possible to greatly shorten the period as compared with the conventional layout method and finish the layout.

According to the third aspect of the present invention, since the power supply connection via contact data is created for each power supply, the power supply wiring path is set in the transistor creating step, the via contact creating step, and the transistor moving step. The layout can be visualized in a visual way. Also, when using a plurality of power supplies, the layout of multiple power supply wirings can be easily performed by dividing the types of via capacitors by the number of the power supplies.

According to the fourth aspect of the invention, since the division data for dividing the generation area of the power supply wiring generated in the power supply wiring automatic generation step for each power supply is used, the type of via capacitors is changed according to the power supply. It is possible to automatically generate a more ideal power supply path without dividing the power supply.
Further, even when a plurality of power supplies are used, the layout of multiple power supply wirings can be easily performed by using the division data as many as the power supplies can be divided.

According to the fifth aspect of the present invention, a process capable of using a multi-layer wiring of three or more layers is used, and each power source wiring arranged for each power source and the signal wiring are formed in different wiring layers. Therefore, it is not necessary to satisfy the design criteria between the power supply wirings or between the power supply wirings and the signal wirings, so that the layout can be further reduced, and the parasitic capacitance of the power supply wirings can also suppress noise.

According to the invention of claim 6, even when a large-scale cell is laid out, it is possible to perform a simple layout by using the layout method of the present invention.

[Brief description of drawings]

FIG. 1 is a flowchart showing a layout method of a semiconductor device according to a first embodiment of the present invention.

FIG. 2 is a flowchart showing details of a via-con creating process shown in FIG.

FIG. 3 is a circuit diagram showing an example of an operational amplifier.

FIG. 4 shows the layout method of FIG. 1 using an operational amplifier circuit. It is a figure which shows the example of a layout pattern image at the time of implement | achieving.

FIG. 5 is a diagram showing a comparison of a temporal ratio between the conventional layout method and the layout method of the present embodiment.

FIG. 6 is a diagram showing a breakdown of a period of each step in the layout process.

FIG. 7 is a diagram showing a breakdown of a period of each step in the verification process.

FIG. 8 is a diagram showing a layout pattern image example by a layout method of a semiconductor device according to a second embodiment of the present invention.

FIG. 9 is a diagram showing an example of a layout pattern image by a semiconductor device layout method according to a third embodiment of the present invention.

FIG. 10 is a diagram showing an example of a layout pattern image by a semiconductor device layout method according to a fourth embodiment of the present invention.

FIG. 11 is a flowchart showing a large-scale cell layout method according to a fifth embodiment of the present invention.

FIG. 12 is a flowchart showing a conventional layout method.

FIG. 13 is a circuit diagram showing an example of an operational amplifier.

FIG. 14 is a layout pattern when the conventional layout method of FIG. 12 is realized by using an operational amplifier circuit.
It is a figure which shows the example of an image.

FIG. 15 is a flowchart showing a conventional large-scale cell layout method.

FIG. 16 is a diagram showing an entire period of a conventional layout method.

[Explanation of symbols]

10 N-Well pattern 11-13 transistors 20 P-Well pattern 21-24 transistors 31 Viacon for power connection 41, 42 signal wiring 51 VDD power supply wiring 52 GND power supply wiring

─────────────────────────────────────────────────── ─── Continuation of front page (51) Int.Cl. ⁷ Identification code FI Theme Coat (reference) H01L 21/82 D (72) Inventor Tomokazu Kawase 25-1, Ekimaehonmachi, Kawasaki-ku, Kawasaki-shi, Kanagawa Toshiba Microelectronics Co., Ltd. In-house (72) Inventor Kiyohisa Kuwana 25-1 Ekimae Honcho, Kawasaki-ku, Kawasaki-shi, Kanagawa Toshiba Microelectronics Co., Ltd. F-term (reference) 5B046 AA08 BA04 JA01 5F064 DD02 DD03 DD05 DD08 DD24 EE02 EE03 EE14 HH06 HH10

Claims (6)

[Claims] 1. A layout method of a semiconductor device, comprising: a layout process for laying out the semiconductor device based on circuit information of the semiconductor device; and a verification process for verifying the layout performed in the layout process. Is a transistor creation step of creating a transistor having a dimension size according to the circuit information at an arbitrary location, and power supply via connection data which is power supply wiring connection information for connecting a power supply wiring to the transistor. A via-con forming step of extracting from information and connecting to the transistor, a transistor moving step of arranging the transistor at a predetermined position so as to satisfy the design standard of the semiconductor device, and a step of connecting between the transistors so as to satisfy the design standard. Signal wiring to connect signal wiring And a wiring path verification step of determining whether or not the wiring path is laid out with the same wiring path as the circuit information, and the wiring path has an error in the wiring path verification step. When determined, the step of changing the size of the transistor and the step of changing the signal wiring so as to follow the circuit information are performed until it is determined that the wiring route is correct in the wiring route verification step. When it is determined in the wiring route verification step that there is no error in the wiring route, a power supply wiring automatic generation step of automatically connecting the power supply wiring to the power connection via contact data is executed. A method for laying out a semiconductor device, comprising: 2. The via contact creating step includes an extraction process of extracting the power supply connecting via contact data from the circuit information; a compaction process of performing a compaction of the entire transistor region created in the transistor creating step; 2. The layout method for a semiconductor device according to claim 1, further comprising a connection process for connecting the power supply connection via-con data extracted in the extraction process to the transistor. 3. The power supply connecting via capacitor data created in the via capacitor creating step is created exclusively for each power supply.
A method for laying out a semiconductor device as described. 4. The division data for dividing the generation area of the power supply wiring generated in the power supply wiring automatic generation step for each power supply is used.
A method for laying out a semiconductor device as described. 5. The power supply wiring arranged for each power supply and the signal wiring are formed in different wiring layers by using a process in which multi-layer wiring of three layers or more can be used. Layout method of semiconductor device. 6. The layout process according to claim 1 is used, after laying out for each unit cell having a plurality of transistors, a unit cell combining step of connecting the unit cells with a signal wiring is performed. The semiconductor device layout method, wherein the verification step and the power supply wiring automatic generation step according to claim 1 are performed on the result obtained in the unit cell synthesis step.