JP2003086809A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To secure 100 V or above of withstand voltage (source-to-drain withstand voltage) for a horizontal MISFET. SOLUTION: A semiconductor device comprises a semiconductor base on which a semiconductor layer of a first conductivity type is formed on a semiconductor substrate via an insulation layer, and a MISFET formed in the semiconductor layer. The MISFET comprises a channel diffusion layer of a second conductivity type formed in the semiconductor layer, a source diffusion layer of the first conductivity type formed in the channel diffusion layer, a drain field reducing layer of the first conductivity type formed in the semiconductor layer, being away from the channel diffusion layer, a drain diffusion layer of the first conductivity type formed in the drain field reducing layer, and a gate electrode formed on the channel diffusion layer via a gate insulation film. The cannel diffusion layer and the source diffusion layer are fixed to the same potential. The semiconductor layer is formed in a thickness of 3 μm or above and the insulation layer is formed in a thickness of 1 μm or above.

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly, to a technology effective when applied to a semiconductor device having a plurality of MISFETs connected in parallel. 2. Description of the Related Art As a semiconductor device, a power MOSFET (Metal) is used together with an integrated circuit such as a logical operation circuit and a control circuit.
Oxide Semiconductor Field Effect Transistor
A power IC (Integrated Circuit) in which a high voltage element referred to as) is mounted on the same semiconductor substrate is known. Power MOSFET is a fine pattern MOSFE
The configuration is such that a plurality of transistor cells made of T are connected in parallel to obtain large power. Here, the MOSFET is an insulated gate field effect transistor in which the gate insulating film is made of a silicon oxide film. In general, MOSFETs can be roughly classified into a horizontal type and a vertical type. A MOSFET in which a current flows in the surface direction of a semiconductor substrate is called a horizontal type, and a MOSFET in a thickness direction (depth direction) of the semiconductor substrate is called a vertical type. Also,
In MOSFET, n-type (n-channel conductivity type) and p-type
A type in which an electron channel (passage) is formed under a gate electrode is called an n-type, and a type in which a hole channel is formed is called a p-type. As for the power IC, for example, “El
ectronic Design / December 17,1999 P83, Intelligent
Power Ics Tout System-Level Integration, STMicro E
electronics ". [0004] By the way, the automobile industry tends to reduce the weight of the vehicle body in order to reduce fuel consumption mainly in Europe and the United States, and is trying to switch from the conventional hydraulic control to an electric control system. . The power supply battery of the electric control system is tripled in power supply capacity, and the use of a power IC mounted thereon requires a withstand voltage of 80 V (room temperature 100 V) and a low on-resistance to reduce power consumption at the same time. [0005] At a conventional withstand voltage of 60 V or less, Vertical Double Diffusion Se is advantageous for ensuring a withstand voltage.
lf-aligned) MOSFET (LD-MOSFE)
T). However, since high breakdown voltage and low on-resistance are in a trade-off relationship, lateral double diffusion (Self-al) is advantageous for low on-resistance in order to suppress the on-resistance and increase the breakdown voltage to 100 V.
It is effective to use a MOSFET (LD-MOSFET) having an igned) structure. An object of the present invention is to provide a technique capable of securing a withstand voltage (source / drain withstand voltage) of a lateral MISFET of 100 V or more. The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings. Means for Solving the Problems Of the inventions disclosed in the present application, the outline of a representative one will be briefly described.
It is as follows. A semiconductor substrate having a first conductivity type semiconductor layer formed on a semiconductor substrate with an insulating layer interposed therebetween, and a MISFET formed on the semiconductor layer;
Forming a second conductivity type channel diffusion layer formed in the semiconductor layer, a first conductivity type source diffusion layer formed in the channel diffusion layer, and forming the second conductivity type channel diffusion layer in the semiconductor layer apart from the channel diffusion layer A drain electric field relaxation layer of the first conductivity type, a drain diffusion layer of the first conductivity type formed on the drain electric field relaxation layer, and a gate electrode formed on the channel diffusion layer with a gate insulating film interposed therebetween. Wherein the channel diffusion layer and the source diffusion layer are fixed at the same potential, wherein the semiconductor layer is formed with a thickness of 3 μ or more, and the insulating layer is formed with a thickness of 1 μ or more. It is formed with. The structure of the present invention will be described below together with an embodiment in which the present invention is applied to a power IC (semiconductor device). In the drawings for describing the embodiments, components having the same function are denoted by the same reference numerals, and a repeated description thereof will be omitted. FIG. 1 is a plan layout view of a power IC according to an embodiment of the present invention, FIG. 2 is a plan view of a main part of a high voltage element section of FIG. 1, and FIG. a-
FIG. 4 is a sectional view of a main part along line a, and FIG. 4 is a breakdown voltage characteristic diagram determined by a voltage applied between the drain and the substrate of the MOSFET. As shown in FIG. 1, a power IC according to this embodiment includes a logic operation circuit section 15 on one main surface of a semiconductor substrate 1.
, A control circuit section 16 and a high-voltage element section 17. For example, an n-channel conductivity type power MOSFET-PW is mounted on the high voltage element section 17. The power MOSFET-PW is configured to obtain a large power by connecting a plurality of MOSFETs (transistor cells) -18 having a fine pattern shown in FIG. 2 in parallel. As shown in FIG. 3, the semiconductor substrate 1 is composed of, for example, a p-type semiconductor substrate 1a made of single-crystal silicon and a silicon oxide film, and an insulating layer (buried oxide) formed on the p-type semiconductor substrate 1a. Membrane: Bured Oxide (BO
X)) 1b, and an n-type semiconductor layer 1c made of single-crystal silicon and formed on the insulating layer 1b. That is, the semiconductor substrate 1 has an SOI structure in which a silicon layer is formed on the insulating layer 1b. On the main surface of the n-type semiconductor layer 1c, a plurality of active regions partitioned by the field insulating film 2 are formed. As shown in FIGS. 2 and 3, a fine pattern MOSFET-18 is formed in each of the plurality of active regions. The MOSFET-18 mainly includes an n-type drain electric field relaxation layer 3, a gate insulating film 4, a gate electrode 5,
The structure includes a p-type channel diffusion layer 6, an n-type source layer 7, an n-type drain layer 8, and a p-type diffusion layer 9 for fixing channel potential. The p-type channel diffusion layer 6 is an n-type semiconductor layer 1c
And the n-type source layer 7 and the channel potential fixing p
The n-type diffusion layer 9 is formed in the n-type semiconductor layer 1c, and the n-type drain electric field relaxation layer 3 is formed in the n-type semiconductor layer 1c apart from the p-type channel diffusion layer 6 in the plane direction of the n-type semiconductor layer 1c. The n-type drain layer 8 is formed on the n-type drain electric field relaxation layer 3. The n-type drain electric field relaxation layer 3 and the p-type channel diffusion layer 6 are formed with a higher impurity concentration than the n-type semiconductor layer 1c. The n-type source layer 7, the n-type drain layer 8, and the p-type diffusion layer 9 for fixing the channel potential are formed with a higher impurity concentration than the n-type drain electric field relaxation layer 3 and the p-type channel diffusion layer 6. The channel potential fixing p-type diffusion layer 9 is formed in contact with the n-type source layer 7. The gate insulating film 4 is formed on the active region in contact with the field insulating film 2, and the gate electrode 5 is formed on the gate insulating film 4 and the field insulating film 2. The gate insulating film 4 and the field insulating film 2 are formed of, for example, a silicon oxide film, and the gate electrode 5 is formed of, for example, a polycrystalline silicon film into which an impurity for reducing a resistance value is introduced. The gate electrode 5 extends continuously along the end of the field insulating film 2 and has a frame shape in plan view. The p-type channel diffusion layer 6 is an n-type semiconductor layer 1c
The n-type source layer 7 is formed by introducing an impurity (for example, boron (B)) into the p-type channel diffusion layer 6 by self-alignment with the gate electrode 5. For example, it is formed by introducing arsenic (As). That is, the MOSFET-18 has a horizontal double diffusion structure (LD structure). N-type source layer 7 and channel potential fixing p
Source wiring 11 is electrically connected to mold diffusion layer 9 through a connection hole formed in interlayer insulating film 10. A drain wiring 12 is electrically connected to the n-type drain layer 8 through a connection hole formed in the interlayer insulating film 10. The insulating layer (BOX) 1b is formed with a thickness of about 1 μm, the n-type semiconductor layer 1c is formed with a thickness of about 3 μm, and the n-type drain electric field relaxation layer 3 is formed with a thickness of about 2 μm. (Diffusion depth). N-channel conductivity type LD-MOSFET-1
8 is measured under the condition that the n-type source layer 7 and the p-type channel diffusion layer 6 are short-circuited and a reverse bias potential is applied between the n-type drain layer 8 and the p-type channel diffusion layer 6. I do. A ground potential V1 having the same potential as the p-type channel diffusion layer 6, the n-type source layer 7, and the gate electrode 5 is applied to the p-type semiconductor substrate 1a. Under the above conditions, when a positive potential V2 is applied to the n-type drain layer 8, the depletion layer formed in the n-type semiconductor layer 1c becomes RESURF (Reduced Surface Elecrti).
c Field: surface field relaxation) layer, and n-type semiconductor layer 1c
This has the effect of relaxing the electric field at the junction between the gate electrode and the p-type channel diffusion layer 6. Therefore, the lateral electric field between the source and the drain is reduced in proportion to the length Loff of the field insulating film 2 in the direction between the source and the drain, and the withstand voltage BVDSS between the source and the drain is improved. On the other hand, drain /
The vertical electric field between the substrates is an n-type drain electric field relaxation layer 3
To concentrate on the depletion layer formed in the diffusion layer between the substrate and
It does not depend on off. Therefore, it is necessary to secure a depletion layer formed immediately below the n-type drain electric field relaxation layer 3 according to the required source-drain breakdown voltage BVDSS. The n-type drain electric field relaxation layer 3 has a depth of about 2 μm because phosphorus (P) is ion-implanted as an impurity and diffused simultaneously with the p-type channel diffusion layer 6. For this reason,
In order to withstand an electric field composed of a vertical voltage, the thickness of the n-type semiconductor layer 1c needs to be 3.0 μm or more. The insulating layer 1b plays an important role of absorbing the vertical electric field between the drain and the substrate. However,
Since the substrate side has a negative potential, a p-type inversion layer is formed at the interface between the insulating layer 1b and the n-type semiconductor layer 1c. The p-type inversion layer formation voltage ΔV depends on the capacitance C of the insulating layer 1b and the concentration N of the n-type semiconductor layer 1c, and has the following proportional relationship. ΔV∝√N · 1 / C = √N · T / ε ₀ ε _si T: Thickness of Insulating Layer 1b As a result of device simulation of the above-mentioned MOSFET-18, it is composed of a portion between the drain and the substrate. It has been found that the thickness of the insulating layer 1b needs to be 1 μm or more in order to obtain a vertical breakdown voltage of ≧ 100V. Figure 4 shows MOSFET-1
8 withstand voltage characteristics determined by the drain-substrate applied voltage (L
off: device simulation result at ∞). Further, in the breakdown voltage simulation of FIG. 4, it is found that the thickness of the Epi layer, that is, the thickness of the n-type semiconductor layer 1c and the drain-source breakdown voltage BVDSS have a dependency. That is, when the thickness of the n-type semiconductor layer 1c is set to 3 μm or more, the n-type semiconductor layer 1c and the insulating layer 1b are removed from the n-type drain electric field relaxation layer 3 around the n-type drain layer 8.
And a depletion layer extending to the interface between the n-type semiconductor layer 1c and the n-type drain electric field relaxation layer 3 can be secured to 30 V or more. Further, by setting the thickness of the insulating layer 1b to 1 μm or more, the p-type inversion layer generated at the interface between the insulating layer 1b and the n-type semiconductor layer 1c due to the negative potential of the p-type semiconductor substrate 1a. A potential of 70 V or more can be secured. Therefore, the thickness of the n-type semiconductor layer 1c is set to 3.0
By setting the thickness of the insulating layer 1b to 1.0 μm or more, the MOSFET having a withstand voltage of 100 V or more
-18 is obtained. In the withstand voltage simulation of FIG.
With this structure, BVDSS ≧ 160V is obtained. However, in the three-dimensional simulation, BVDSS ≧ 120
V. Incidentally, for the p-type inversion layer generated at the interface between the insulating layer 1b and the n-type semiconductor layer 1c, a method of increasing the resistance (low concentration) of the p-type semiconductor substrate 1a is also effective. .
Since the p-type semiconductor substrate 1a and the n-type semiconductor layer 1c are insulated by the insulating layer 1b, there is not much electrical restriction. Accordingly, by using the low-concentration p-type semiconductor substrate 1a, a depletion layer formed between the insulating layer 1b and the p-type semiconductor substrate 1a is expanded, and the capacitance of the depletion layer is reduced to make it difficult for parasitic p-type inversion to occur. Is also conceivable. There is a method of making the concentration of the n-type semiconductor layer 1c higher (higher) in order to make the parasitic p-type inversion harder. But n
The type semiconductor layer 1c is used as the above-mentioned RESURF, and it is difficult to increase the concentration because the effect may be lost. Therefore, it is effective to selectively form a high-concentration n-type diffusion layer at the interface between the insulating layer 1b and the n-type semiconductor layer 1c. As described above, the invention made by the present inventor is:
Although specifically described based on the embodiment, the present invention
It is needless to say that the present invention is not limited to the above-described embodiment, but can be variously changed without departing from the gist thereof. For example, the present invention provides a plurality of n-type MOSFETs.
The present invention can be applied to a semiconductor device having a power MOSFET in which T is connected in parallel. The present invention can be applied to a semiconductor device having a power MISFET in which a plurality of MISFETs each having a gate insulating film in which a silicon oxide film is nitrided are connected in parallel. The present invention can be applied to a semiconductor device having a p-type MOSFET. The effects obtained by typical aspects of the invention disclosed in the present application will be briefly described as follows. It is possible to secure the withstand voltage (source / drain withstand voltage) of the lateral MISFET of 100 V or more.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a plan layout diagram of a power IC (semiconductor device) according to an embodiment of the present invention. FIG. 2 is a plan view of a main part of the high-voltage element section of FIG. FIG. 3 is a cross-sectional view of a main part along the line aa in FIG. 2; FIG. 4 is a breakdown voltage characteristic diagram determined by a voltage applied between a drain and a substrate of MOSFET-18. DESCRIPTION OF SYMBOLS 1 ... semiconductor substrate, 1a ... p-type semiconductor substrate, 1b ... insulating layer, 1c ... n-type semiconductor layer, 2 ... field insulating film, 3 ...
n-type drain electric field relaxation layer, 4 ... gate insulating film, 5 ... gate electrode, 6 ... p-type channel diffusion layer, 7 ... n-type source layer,
8 n-type drain layer, 9 p-type diffusion layer for fixing channel potential, 10 interlayer insulating film, 11 source wiring, 12 drain wiring, 18 MOSFET, PW power MOSF
ET.

   ────────────────────────────────────────────────── ─── Continuation of front page    (72) Inventor Mitsuru Sekino             5-22-1, Kamizu Honcho, Kodaira City, Tokyo             Hitachi, Ltd. LSI System             Inside (72) Inventor Masashi Watanabe             5-22-1, Kamizu Honcho, Kodaira City, Tokyo             Hitachi, Ltd. LSI System             Inside (72) Inventor Tomoko Obata             5-22-1, Kamizu Honcho, Kodaira City, Tokyo             Hitachi, Ltd. LSI System             Inside (72) Inventor Ryo Koshimizu             5-20-1, Josuihoncho, Kodaira-shi, Tokyo             Hitachi, Ltd. Semiconductor Group (72) Inventor Kazuyuki Umezu             5-20-1, Josuihoncho, Kodaira-shi, Tokyo             Hitachi, Ltd. Semiconductor Group F term (reference) 5F048 AA05 AC01 BA09 BB01 BB05                       BC07 BE09                 5F110 AA01 AA13 BB12 BB20 CC02                       DD05 DD13 DD24 EE09 EE24                       FF02 FF26 GG02 GG12 GG24                       GG60 HM12

Claims (1)

1. A semiconductor substrate having a semiconductor layer of a first conductivity type formed on a semiconductor substrate with an insulating layer interposed therebetween, and a MISFET formed on the semiconductor layer. The MISFET includes a second conductivity type channel diffusion layer formed in the semiconductor layer, a first conductivity type source diffusion layer formed in the channel diffusion layer, and a semiconductor diffusion layer separated from the channel diffusion layer. A first conductivity type drain electric field relaxation layer formed; a first conductivity type drain diffusion layer formed on the drain electric field relaxation layer; and a gate formed on the channel diffusion layer with a gate insulating film interposed therebetween. An electrode, wherein the channel diffusion layer and the source diffusion layer are fixed in potential at the same potential, wherein the semiconductor layer is formed with a thickness of 3 μm or more, and the insulating layer is formed with a thickness of 1 μm or more. By Wherein a being made.