JP2003086731A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JP2003086731A JP2003086731A JP2001272091A JP2001272091A JP2003086731A JP 2003086731 A JP2003086731 A JP 2003086731A JP 2001272091 A JP2001272091 A JP 2001272091A JP 2001272091 A JP2001272091 A JP 2001272091A JP 2003086731 A JP2003086731 A JP 2003086731A
- Authority
- JP
- Japan
- Prior art keywords
- csp
- chip
- rewiring
- semiconductor device
- bonding pad
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、チップサイズパッ
ケージ（ＣＳＰ；Chip Size Package）を用いた半導体
装置に係り、特にＣＳＰ内における再配線を利用するこ
とにより回路設計の柔軟性を高めることが可能な半導体
装置に関する。本発明は、特にＣＳＰに実装されたボル
テージレギュレータの位相補償回路やＣＳＰに実装され
たその他の各種のアナログ回路に適用可能である。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device using a chip size package (CSP), and in particular, it is possible to enhance flexibility in circuit design by utilizing rewiring in the CSP. Semiconductor device. The present invention is particularly applicable to a phase compensation circuit of a voltage regulator mounted on a CSP and various other analog circuits mounted on a CSP.
【０００２】[0002]
【従来の技術】ＬＳＩチップのパッケージには多くの種
類が知られているが、近年、パッケージのより一層の小
型化を図るために、チップとほぼ同サイズのパッケー
ジ、すなわちチップサイズパッケージ（ＣＳＰ；Chip S
ize Package）が開発されている。2. Description of the Related Art Many types of LSI chip packages are known, but in recent years, in order to further reduce the size of the package, a package of approximately the same size as the chip, that is, a chip size package (CSP; Chip S
ize Package) is being developed.
【０００３】図１１は、従来の各種ＣＳＰの製造工程を
示す図であり、同図（ａ）はリードフレームパッケージ
の製造工程、同図（ｂ）はＦＢＧＡ（Fine-pitch Ball
GridArray）の製造工程、同図（ｃ）はウェハーレベル
ＣＳＰの製造工程を示している。FIG. 11 is a diagram showing a manufacturing process of various conventional CSPs. FIG. 11A is a manufacturing process of a lead frame package, and FIG. 11B is a FBGA (Fine-Pitch Ball) manufacturing process.
Grid Array) manufacturing process, and FIG. 7C shows a wafer level CSP manufacturing process.
【０００４】図１１（ａ）のリードフレームパッケージ
と図１１（ｂ）のＦＢＧＡは、基本的に従来と同じ工程
（チップに切断Ａ１、ダイボンディングＡ２、ワイヤボ
ンディングＡ３、封止Ａ４、リード形成Ａ５／リード表
面処理固片化Ａ６または電子処理固片化Ａ７）、すなわ
ち前処理を終わったウェハーから個々のチップをダイシ
ングにより切り出して、それをパッケージに組み立てる
ものであるが、本発明に係るウェハーレベルＣＳＰは、
図１１（ｃ）に示すように、前処理の終わったウェハー
に直接パッケージ処理（Ｐｉ膜形成Ａ１１、再配線処理
Ａ１２、ポスト形成Ａ１３、封止Ａ１４、研削端子処理
Ａ１５）を行い、その後で個々のチップに切り分ける
（ダイシングＡ１６）ものである。The lead frame package of FIG. 11 (a) and the FBGA of FIG. 11 (b) are basically the same as the conventional process (chip cutting A1, die bonding A2, wire bonding A3, sealing A4, lead formation A5. / Lead surface treatment fragmentation A6 or electronic treatment fragmentation A7), that is, individual chips are cut out by dicing from a pre-processed wafer and assembled into a package. CSP is
As shown in FIG. 11C, the pre-processed wafer is directly packaged (Pi film formation A11, rewiring process A12, post formation A13, sealing A14, grinding terminal process A15), and then individually processed. It is divided into chips (dicing A16).
【０００５】図１２は、ウェハーレベルＣＳＰ技術を用
いて作製したチップの詳細断面を示す図である。同図に
おいて、Ｂ１はＩＣチップ（シリコンチップ）、Ｂ２は
ＩＣチップＢ１のパッド上に設けられたアルミ電極、Ｂ
３はバリアメタル層、Ｂ４はバリアメタル層Ｂ３上に設
けられた再配線層（銅Ｃｕ）、Ｂ５は銅で形成されたポ
スト、Ｂ６は銅のポスト上に載せられたハンダバンプ
（ハンダボール）、Ｂ７はパッシベーション膜、Ｂ８は
モールド（エポキシなどの封止樹脂）である。FIG. 12 is a view showing a detailed cross section of a chip manufactured by using the wafer level CSP technology. In the figure, B1 is an IC chip (silicon chip), B2 is an aluminum electrode provided on the pad of the IC chip B1, and B is
3 is a barrier metal layer, B 4 is a rewiring layer (copper Cu) provided on the barrier metal layer B 3, B 5 is a post made of copper, B 6 is a solder bump (solder ball) placed on the copper post, B7 is a passivation film, and B8 is a mold (sealing resin such as epoxy).
【０００６】以上が従来のウェハーレベルＣＳＰの構成
の説明であるが、従来のウェハーレベルＣＳＰでは、Ｉ
Ｃのパッドおよびその上に設けられたアルミ電極Ｂ２と
銅ポストＢ４およびハンダバンプ（ハンダボール）Ｂ６
とは、できるだけ抵抗の小さい再配線Ｂ４により１対１
の関係で接続されるのが前提とされていた。The above is the description of the structure of the conventional wafer level CSP. In the conventional wafer level CSP, I
C pad and aluminum electrode B2 and copper post B4 and solder bump (solder ball) B6 provided thereon
Is one-to-one with the rewiring B4 having the smallest resistance.
It was supposed to be connected because of the relationship.
【０００７】[0007]
【発明が解決しようとする課題】しかしながら、ＩＣの
パッドおよびその上に設けられたアルミ電極Ｂ２と銅ポ
ストＢ４およびハンダバンプ（ハンダボール）Ｂ６とを
抵抗のできるだけ小さい再配線層により１対１で接続す
ることを前提にした場合は、ＣＳＰ自体の仕様や性能は
ＩＣチップの構造によって制限されるという問題があ
る。However, the pad of the IC and the aluminum electrode B2 provided thereon, the copper post B4 and the solder bump (solder ball) B6 are connected in a one-to-one manner by a rewiring layer having a resistance as small as possible. However, there is a problem in that the specifications and performance of the CSP itself are limited by the structure of the IC chip.
【０００８】本発明の目的は、上記問題を解消し、ＩＣ
チップが本来有する仕様や性能を拡張することが可能で
柔軟性を有する半導体装置（請求項１〜３）、特に発振
の抑止が容易なボルテージレギュレータ回路を含む半導
体装置（請求項４，５）を提供することにある。An object of the present invention is to solve the above problems and to provide an IC
A semiconductor device (Claims 1 to 3) having flexibility that can expand the specifications and performances originally possessed by the chip (Claims 1 to 3), and in particular, a semiconductor device including a voltage regulator circuit that easily suppresses oscillation (Claims 4 and 5) To provide.
【０００９】本発明は、上記目的を達成するために、次
のような構成を採用した。すなわち、請求項１記載の発
明は、チップ上に再配線層が形成されるＣＳＰを備える
半導体装置であって、チップ上の一つのボンディングパ
ッドとＣＳＰの複数の端子との間をＣＳＰ内の再配線に
より接続したことを特徴とし、請求項２記載の発明は、
さらに、チップ上の一つのボンディングパッドとＣＳＰ
の複数の端子との間を接続する再配線の抵抗値を所望の
値になるようにレイアウトしたことを特徴とし、請求項
３記載の発明は、再配線の所望の抵抗値は、再配線層の
幅、長さ、材質の少なくとも一つを変えてレイアウトす
ることにより得ることを特徴としている。In order to achieve the above object, the present invention employs the following configurations. That is, the invention according to claim 1 is a semiconductor device including a CSP in which a rewiring layer is formed on a chip, wherein a reconnection in the CSP is performed between one bonding pad on the chip and a plurality of terminals of the CSP. The invention according to claim 2 is characterized in that they are connected by wiring.
In addition, one bonding pad on the chip and CSP
In the invention according to claim 3, the rewiring for connecting the plurality of terminals is arranged so that the resistance of the rewiring has a desired value. It is characterized by being obtained by laying out by changing at least one of the width, the length and the material.
【００１０】また、請求項４記載の発明は、上記チップ
としてボルテージレギュレータ回路を含むチップを用
い、再配線のうち、抵抗値が低い再配線が接続されてい
る端子に出力負荷を接続し、抵抗値が高い再配線が接続
されている端子に位相補償用のコンデンサを接続するこ
とを特徴とし、請求項５記載の発明は、位相補償用のコ
ンデンサに接続された再配線の抵抗値を１０ｍΩ〜１０
Ωにしたことを特徴としている。According to a fourth aspect of the present invention, a chip including a voltage regulator circuit is used as the chip, and an output load is connected to a terminal to which a rewiring having a low resistance value is connected among rewirings, A capacitor for phase compensation is connected to a terminal to which a rewiring having a high value is connected, and the invention according to claim 5 has a resistance value of the rewiring connected to the capacitor for phase compensation of 10 mΩ to 10
The feature is that it is set to Ω.
【００１１】[0011]
【発明の実施の形態】（第１の実施例）図１は、本発明
の第１の実施例を説明するための図であり、ＩＣチップ
のボンディングパッドと複数のハンダバンプ（ＣＳＰの
出力端子）を再配線層を介して接続した例を示してい
る。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS (First Embodiment) FIG. 1 is a diagram for explaining a first embodiment of the present invention, in which a bonding pad of an IC chip and a plurality of solder bumps (output terminals of CSP) are provided. Shows an example in which is connected via a rewiring layer.
【００１２】同図（ａ）（ｂ）は、ＩＣチップの一つの
ボンディングパッド１とＣＳＰの出力端子である２つの
ハンダバンプ２，３を再配線層４ａ，４ｂによって接続
した構成例およびその等価回路図であり、同図（ｃ）
（ｄ）は、ＩＣチップの一つのボンディングパッド１１
とＣＳＰの出力端子である３つのハンダバンプ１２〜１
４を再配線層１５ａ〜１５ｃによって接続した構成例お
よびその等価回路図である。同様にして一つのボンディ
ングパッドと４つ以上のハンダバンプを再配線層によっ
て接続する構成も可能であることはいうまでもない。FIGS. 1A and 1B show a configuration example in which one bonding pad 1 of an IC chip and two solder bumps 2 and 3 which are output terminals of a CSP are connected by rewiring layers 4a and 4b and an equivalent circuit thereof. It is a figure, the figure (c)
(D) shows one bonding pad 11 of the IC chip
And three solder bumps 12 to 1 which are output terminals of the CSP
4 is a configuration example in which 4 is connected by rewiring layers 15a to 15c and an equivalent circuit diagram thereof. Similarly, it goes without saying that one bonding pad and four or more solder bumps may be connected by a rewiring layer.
【００１３】この構成を採用することにより、所望の位
置に複数のハンダバンプを設け、それらのハンダバンプ
と任意のボンディングパッドを再配線層で接続すること
により、任意のボンディングパッドの信号を所望の位置
に設けた複数のハンダバンプから取り出すことが可能と
なり、ＣＳＰの適用範囲を大幅に広げることができる。By adopting this configuration, a plurality of solder bumps are provided at desired positions, and these solder bumps and arbitrary bonding pads are connected by a rewiring layer, so that signals of arbitrary bonding pads can be moved to desired positions. It is possible to take out from a plurality of solder bumps provided, and the application range of CSP can be greatly expanded.
【００１４】（第２の実施例）上記第１の実施例では、
再配線層の抵抗を考慮しなかった（もしくは抵抗０を前
提にした）が、第２の実施例は、任意のボンディングパ
ッドとそれぞれのハンダバンプの間を接続する再配線層
の抵抗を所定の抵抗値に設計するようにしたものであ
る。(Second Embodiment) In the first embodiment,
Although the resistance of the redistribution layer is not taken into consideration (or the resistance of 0 is assumed), the second embodiment sets the resistance of the redistribution layer that connects between any bonding pad and each solder bump to a predetermined resistance. It is designed to be a value.
【００１５】図２は、第２の実施例を説明するための図
であり、同図（ａ）は、図１（ａ）において一つのボン
ディングパッド１と２つのハンダバンプ２，３を接続し
た再配線４の抵抗値を、それぞれ、例えば抵抗値０、抵
抗値ｒ１にした場合の等価回路図であり、同図（ｂ）
は、図１（ｃ）において一つのボンディングパッド１１
と３つのハンダバンプ１２〜１４を接続する再配線層１
５ａ〜１５ｃの抵抗値を、それぞれ、例えば抵抗値０、
抵抗値ｒ２，ｒ３にした場合の等価回路図である。それ
ぞれの再配線層の抵抗値をいかなる値にするかは、対象
とする回路がどのような回路かによって決める設計事項
である。この構成を採用することにより、ＣＳＰの適用
範囲を第１の実施例に比較してさらに広げることができ
る。FIG. 2 is a diagram for explaining the second embodiment. FIG. 2A shows a structure in which one bonding pad 1 and two solder bumps 2 and 3 are connected in FIG. 1A. It is an equivalent circuit diagram when the resistance value of the wiring 4 is set to, for example, a resistance value of 0 and a resistance value of r1, respectively.
Is one bonding pad 11 in FIG.
And a rewiring layer 1 for connecting the three solder bumps 12 to 14
The resistance values of 5a to 15c are respectively set to, for example, a resistance value of 0,
It is an equivalent circuit diagram when it is set to resistance values r2 and r3. The value of the resistance value of each redistribution layer is a design item determined by what kind of circuit the target circuit is. By adopting this configuration, the applicable range of the CSP can be further widened as compared with the first embodiment.
【００１６】（第３の実施例）本発明は、一般的な各種
アナログ回路や各種半導体装置に適用可能であるが、こ
こでは第３の実施例としてボルテージレギュレータに適
用した例を説明する。図３は、一般的なボルテージレギ
ュレータの使用状態の回路図である。同図においては、
ボルテージレギュレータ２０の外付け素子として、Ｖｉ
ｎ−ＧＮＤ間、Ｖｏｕｔ−ＧＮＤ間に入力電圧および出
力電圧を安定させるためのコンデンサ２１を挿入してい
る。Ｖｏｕｔ端子に接続されるコンデンサ２１について
はコンデンサ自身の内部抵抗であるＥＳＲ（Equivalent
Series Resistance；等価直列抵抗）も記してある。(Third Embodiment) The present invention can be applied to various general analog circuits and various semiconductor devices. Here, an example in which the present invention is applied to a voltage regulator will be described as a third embodiment. FIG. 3 is a circuit diagram of a general voltage regulator in use. In the figure,
As an external element of the voltage regulator 20,
A capacitor 21 for stabilizing the input voltage and the output voltage is inserted between n-GND and Vout-GND. Regarding the capacitor 21 connected to the Vout terminal, ESR (Equivalent
Series Resistance) is also shown.
【００１７】図４は、一般的なボルテージレギュレータ
の内部の構成を示す図である。同図に示すように、一般
的なボルテージレギュレータ３０は、定電圧源３１、差
動増幅器３２、出力トランジスタ３３および抵抗３４，
３５による負帰還回路によって構成されているため発振
のおそれがある。FIG. 4 is a diagram showing an internal configuration of a general voltage regulator. As shown in the figure, a general voltage regulator 30 includes a constant voltage source 31, a differential amplifier 32, an output transistor 33 and a resistor 34,
Since it is composed of the negative feedback circuit of 35, there is a possibility of oscillation.
【００１８】すなわち、通常のボルテージレギュレータ
は、差動増幅器（２段で構成の場合あり）と出力トラン
ジスタで計２〜３つのポール（ゲインが２０ｄＢ下が
る、位相が９０度遅れる周波数）を持っているので、図
５に示すような周波数特性になる。同図（ａ）は周波数
−ゲインの関係、同図（ｂ）は、周波数−位相遅れの関
係を示す図である。従って位相が図５（ｂ）に示すよう
に１８０度以上遅れ、発振する可能性がある。そのた
め、位相補償を行って発振を抑止する必要がある。That is, a normal voltage regulator has a total of 2 to 3 poles (gain is reduced by 20 dB, phase is delayed by 90 degrees) with a differential amplifier (which may be configured in two stages) and an output transistor. Therefore, the frequency characteristic is as shown in FIG. The figure (a) is a figure which shows the frequency-gain relationship, and the figure (b) is a figure which shows the frequency-phase delay relationship. Therefore, the phase may be delayed by 180 degrees or more as shown in FIG. Therefore, it is necessary to perform phase compensation to suppress oscillation.
【００１９】位相補償はボルテージレギュレータ２０の
内部回路でも行なっているが、出力端子に付けるコンデ
ンサ２１の容量とＥＳＲの抵抗で発生するゼロ（ポール
の逆）も利用している。そのため、図３の状態ではゼロ
が１／（２π・Ｃｏｕｔ・ＥＳＲ）［Ｈｚ］で現れるた
め、図６に示すように位相を進め図中のＣ点での位相の
遅れが１８０度をこえないようにすることが可能とな
る。これにより発振を防止することが可能になる。Although the phase compensation is also performed in the internal circuit of the voltage regulator 20, the capacity of the capacitor 21 attached to the output terminal and the zero (reverse of the pole) generated by the resistance of the ESR are also used. Therefore, in the state of FIG. 3, zero appears at 1 / (2π · Cout · ESR) [Hz], so the phase is advanced as shown in FIG. 6 and the phase delay at point C in the figure does not exceed 180 degrees. It becomes possible to do so. This makes it possible to prevent oscillation.
【００２０】ボルテージレギュレータ２０に使われるコ
ンデンサ２１としては、タンタルコンデンサやセラミッ
クコンデンサがある。これらのコンデンサのＥＳＲ（Eq
uivalent Series Resistance；等価直列抵抗）は、タン
タルコンデンサが数Ω程度、セラミックコンデンサが数
十ｍΩ程度である。As the capacitor 21 used in the voltage regulator 20, there is a tantalum capacitor or a ceramic capacitor. ESR (Eq of these capacitors
The uivalent series resistance is about several Ω for tantalum capacitors and several tens of mΩ for ceramic capacitors.
【００２１】タンタルコンデンサを使用する場合は、現
在一般的に使われている容量値（数μＦ程度）では、ゼ
ロのできる周波数がゲインが０ｄＢになる周波数付近
（位相は高周波になるほど遅れていくので必然と０ｄＢ
付近が位相余裕がなくなる）にできることが多いため、
位相補償が比較的容易である。When a tantalum capacitor is used, at a capacitance value (about several μF) which is generally used at present, the frequency at which zero can be obtained is near the frequency at which the gain becomes 0 dB (the phase becomes delayed as the frequency becomes higher). Inevitably 0 dB
Since there is often no phase margin in the vicinity),
Phase compensation is relatively easy.
【００２２】しかしながら、セラミックコンデンサにお
いて同じ容量値を使った場合、ＥＳＲがタンタルコンデ
ンサより小さいため、ゼロが高周波側にできてしまい、
位相補償の効果が薄れ、その結果位相補償が困難とな
る。逆に考えると、何らかの方法でセラミックコンデン
サのＥＳＲを補ってタンタルコンデンサのように大きく
できれば位相補償が容易になることになる。However, when the same capacitance value is used in the ceramic capacitor, the ESR is smaller than that of the tantalum capacitor, so that zero is formed on the high frequency side,
The effect of phase compensation is weakened, and as a result, phase compensation becomes difficult. In other words, if the ESR of the ceramic capacitor can be supplemented by some method to make it larger like a tantalum capacitor, phase compensation will be facilitated.
【００２３】そこで、ボルテージレギュレータを第１の
実施例や第２の実施例で説明した如きＣＳＰに実装する
ようにすれば、ＣＳＰ内の再配線の配線抵抗を利用して
セラミックコンデンサのＥＳＲを補うことができ、ボル
テージレギュレータの位相補償を容易に行うことが可能
となる。Therefore, if the voltage regulator is mounted on the CSP as described in the first and second embodiments, the ESR of the ceramic capacitor is supplemented by utilizing the wiring resistance of the rewiring in the CSP. Therefore, the phase compensation of the voltage regulator can be easily performed.
【００２４】以下、ボルテージレギュレータをＣＳＰに
実装する例を具体的に説明する。図１１を用いて先に説
明したように、ＣＳＰは、ＩＣチップＢ１のパッシベー
ション膜Ｂ７の上に保護膜を積層し、その上にボンディ
ングパッド部のアルミ電極Ｂ２からＣＳＰの出力端子と
なるハンダバンプの下に形成される銅ポストＢ５までの
間を銅を使用した再配線を施した後、封止樹脂Ｂ８で封
止を行い、その上にハンダバンプ（ハンダボール）をの
せた形状となっている。Hereinafter, an example of mounting the voltage regulator on the CSP will be specifically described. As described above with reference to FIG. 11, in the CSP, the protective film is laminated on the passivation film B7 of the IC chip B1, and the aluminum electrode B2 of the bonding pad portion is formed on the protective film to form the solder bump of the CSP. After rewiring using copper is performed up to a copper post B5 formed below, sealing is performed with a sealing resin B8, and solder bumps (solder balls) are placed on the sealing resin B8.
【００２５】前述したように、セラミックコンデンサの
位相補償を容易にするにはＥＳＲを補う必要があるが、
そのためには出力端子に小さい値であるが抵抗を追加し
なければならない。しかし、抵抗を追加すると負荷電流
を流した場合にこの追加した抵抗によって電圧降下を起
こして特性が劣化することになり、好ましくない。As described above, it is necessary to supplement the ESR to facilitate the phase compensation of the ceramic capacitor.
For that purpose, it is necessary to add a resistor to the output terminal although the value is small. However, if a resistor is added, a voltage drop will occur due to the added resistor when a load current flows, and the characteristics will deteriorate, which is not preferable.
【００２６】しかし、図２（ａ）で説明したように、Ｉ
Ｃチップの一つのボンディングパッドと２つのハンダバ
ンプ（出力端子）をそれぞれ異なる再配線層を用いて接
続することにより上記問題を解決することができる。However, as explained in FIG. 2A, I
The above problem can be solved by connecting one bonding pad of the C chip and two solder bumps (output terminals) using different rewiring layers.
【００２７】すなわち、図７に示すように、出力負荷４
７を接続する端子（ハンダバンプ）４２と容量（コンデ
ンサ）４５を接続する端子（ハンダバンプ）４３を別々
に設けて、出力負荷４７を接続する端子４２とＩＣチッ
プのボンディングパッド４１との間になるべく配線抵抗
がつかないようにするとともに、コンデンサ４５を接続
する端子４３とＩＣチップのボンディングパッド４１と
の間にはＥＳＲ４６を補うための配線抵抗Ｒｏｕｔ（数
百ｍΩ程度）４４が形成されるようにわざと配線長を長
くしたり配線の幅を細くなるように銅の再配線層をレイ
アウトをする。これにより、電流を流した時の電圧降下
を防ぎながらＥＳＲ４６の抵抗値を補うことができ、そ
の結果位相補償を容易に行なうことが可能となる。That is, as shown in FIG. 7, the output load 4
A terminal (solder bump) 42 for connecting 7 and a terminal (solder bump) 43 for connecting a capacitor (capacitor) 45 are separately provided, and wiring is provided as much as possible between the terminal 42 for connecting the output load 47 and the bonding pad 41 of the IC chip. The wiring resistance Rout (about several hundred mΩ) 44 for compensating the ESR 46 is intentionally formed between the terminal 43 connecting the capacitor 45 and the bonding pad 41 of the IC chip so as to prevent the resistance from being applied. The copper redistribution layer is laid out so as to increase the wiring length and the wiring width. As a result, the resistance value of the ESR 46 can be supplemented while preventing a voltage drop when a current is passed, and as a result, phase compensation can be easily performed.
【００２８】またこの場合、ＣＳＰであるため端子数を
増やすことによって実装面積が増えることもない。さら
にコンデンサ接続用のピンを、再配線層の抵抗値を変え
て複数個取り出すことによって使用するコンデンサに対
し最適な値のＥＳＲを付加した状態で使用することも可
能になる。上記の内容を実現した再配線パターンの断面
図および上面図を、図８および図９に示す。Further, in this case, since it is a CSP, the mounting area does not increase by increasing the number of terminals. Furthermore, by changing the resistance value of the rewiring layer and extracting a plurality of pins for connecting a capacitor, it is possible to use the pin with an optimum ESR value added to the capacitor used. 8 and 9 are a cross-sectional view and a top view of a rewiring pattern that realizes the above contents.
【００２９】ここで、図７の回路構成における再配線層
によって形成される配線抵抗Ｒｏｕｔ４４の値について
検討する。一般的に使用されている出力端子に接続する
コンデンサの容量値は０．１μＦ〜１０μＦ程度である
ことおよび出力端子を複数に分けるために出力端子に挿
入する抵抗Ｒｏｕｔを大きくすることができるため、図
７の回路構成の場合、ボルテージレギュレータの出力と
コンデンサ間に追加する抵抗値Ｒｏｕｔは１０ｍΩ〜１
０Ω程度の抵抗値にするのが適当と思われる。図１０
は、このときの抵抗値Ｒｏｕｔと回路の安定度の関係を
示す図である。１０Ω以上の抵抗値でも発振を止めるこ
とができるが、再配線層でそのような抵抗を作るのはス
ペースが多く必要になるため現実的でないので、本実施
例では１０ｍΩ〜１０Ωの範囲にした。Here, the value of the wiring resistance Rout44 formed by the rewiring layer in the circuit configuration of FIG. 7 will be examined. Since the capacitance value of the capacitor connected to the output terminal that is generally used is about 0.1 μF to 10 μF, and the resistance Rout inserted in the output terminal in order to divide the output terminal into a plurality can be increased, In the case of the circuit configuration of FIG. 7, the resistance value Rout added between the output of the voltage regulator and the capacitor is 10 mΩ to 1
It seems appropriate to set the resistance value to about 0Ω. Figure 10
FIG. 4 is a diagram showing the relationship between the resistance value Rout and the circuit stability at this time. Oscillation can be stopped even with a resistance value of 10 Ω or more, but it is not realistic to make such a resistance in the redistribution layer because it requires a lot of space, so in this embodiment, the range is set to 10 mΩ to 10 Ω.
【００３０】第３の実施例ではＣＳＰにセラミックコン
デンサ対応のボルテージレギュレータを実装した場合
に、ＣＳＰで位相補償を行って発振を抑止するようにし
た例を示したが、ＩＣチップ上の一つのボンディングパ
ッドから再配線層を利用してＣＳＰの複数のハンダバン
プ（出力端子）に出力を取り出せるようにした本発明
は、ボルテージレギュレータに限らず、様々な機能を有
する各種アナログ回路を実装する場合にも適用できるこ
とはいうまでもない。In the third embodiment, when a voltage regulator corresponding to a ceramic capacitor is mounted on the CSP, the CSP performs phase compensation to suppress oscillation, but one bonding on the IC chip is shown. The present invention in which an output can be taken out from a pad to a plurality of solder bumps (output terminals) of a CSP by utilizing a rewiring layer is applied not only to a voltage regulator but also to mounting various analog circuits having various functions. It goes without saying that you can do it.
【００３１】なお、再配線の抵抗値は、再配線層の幅、
長さ、材質の少なくとも一つを変えてレイアウトするこ
とにより所望の値にすることが可能である。The resistance value of the rewiring is the width of the rewiring layer,
A desired value can be obtained by laying out by changing at least one of length and material.
【００３２】以上説明したように、本実施例によれば、
ＣＳＰの製造工程内での回路設計で回路の特性を決める
ことが可能となるため、ウェハーレベルでの回路設計の
自由度が増し、また満足な特性が得られなくてもウェハ
ーレベルでの回路変更をせずに特性の改善が望める。As described above, according to this embodiment,
Since the circuit characteristics can be determined by the circuit design within the manufacturing process of the CSP, the degree of freedom in circuit design at the wafer level is increased, and the circuit change at the wafer level even if the satisfactory characteristics cannot be obtained. It can be expected to improve the characteristics without doing.
【００３３】さらに、ＣＳＰであるためパッケージサイ
ズを大きくせずに端子数を増やせるため、出力端子を用
途別に複数端子出すことが可能となり出力端子側に抵抗
を追加することによる若干生ずる特性劣化のデメリット
をなくすことが可能となる。また、配線抵抗を付加した
端子が複数個あるため位相補償用として使用するコンデ
ンサの種類の幅が広がる。Further, since it is a CSP, the number of terminals can be increased without increasing the package size, so that it is possible to output a plurality of output terminals for each application, and the demerit of characteristic deterioration that occurs slightly due to the addition of resistors on the output terminal side. Can be eliminated. Further, since there are a plurality of terminals to which wiring resistance is added, the range of types of capacitors used for phase compensation is widened.
【００３４】[0034]
【発明の効果】本発明によれば、ＩＣチップが本来有す
る仕様や性能を拡張することが可能で柔軟性を有する半
導体装置（請求項１〜３）、特に発振の抑止が容易なボ
ルテージレギュレータ回路を含む半導体装置（請求項
４，５）を得ることができる。According to the present invention, a semiconductor device (claims 1 to 3) which is flexible and capable of expanding the specifications and performance originally possessed by an IC chip, and particularly a voltage regulator circuit in which oscillation can be easily suppressed It is possible to obtain a semiconductor device including the above (claims 4 and 5).
【００３５】すなわち、チップサイズパッケージ（ＣＳ
Ｐ）の製造工程内で決定できる回路定数（この項目では
配線抵抗）を位相補償に利用しているので、ウェハーレ
ベルでの回路変更せずにＣＳＰ側の修正で特性改善が可
能となる（請求項１〜３）。また、ウェハーレベルでの
設計マージンが広がる（請求項１〜３）。特にセラミッ
クコンデンサ対応の発振しないボルテージレギュレータ
の開発が容易となる（請求項４，５）。That is, the chip size package (CS
Since the circuit constant (wiring resistance in this item) that can be determined in the manufacturing process of P) is used for phase compensation, it is possible to improve the characteristics by modifying the CSP side without changing the circuit at the wafer level (claim). Items 1-3). Further, the design margin at the wafer level is widened (claims 1 to 3). Particularly, it becomes easy to develop a voltage regulator that does not oscillate for a ceramic capacitor (claims 4 and 5).
【図１】本発明の第１の実施例を説明するための図であ
る。FIG. 1 is a diagram for explaining a first embodiment of the present invention.
【図２】本発明の第２の実施例を説明するための図であ
る。FIG. 2 is a diagram for explaining a second embodiment of the present invention.
【図３】一般的なボルテージレギュレータの使用状態の
回路図である。FIG. 3 is a circuit diagram of a general voltage regulator in use.
【図４】一般的なボルテージレギュレータの内部の構成
を示す図である。FIG. 4 is a diagram showing an internal configuration of a general voltage regulator.
【図５】発振を引き起こすボルテージレギュレータの周
波数特性を示す図である。FIG. 5 is a diagram showing frequency characteristics of a voltage regulator that causes oscillation.
【図６】発振を引き起こさないようにしたボルテージレ
ギュレータの周波数特性を示す図である。FIG. 6 is a diagram showing frequency characteristics of a voltage regulator that does not cause oscillation.
【図７】本発明の第３の実施例（ボルテージレギュレー
タ）を説明するための図である。FIG. 7 is a diagram for explaining a third embodiment (voltage regulator) of the present invention.
【図８】図７の再配線パターンの断面図である。および
上面図を、8 is a cross-sectional view of the rewiring pattern of FIG. And the top view
【図９】図７の再配線パターンの上面図である。9 is a top view of the rewiring pattern of FIG. 7. FIG.
【図１０】図７の構成における抵抗Ｒｏｕｔの値と回路
の安定度の関係を示す図である。10 is a diagram showing the relationship between the value of the resistor Rout and the stability of the circuit in the configuration of FIG.
【図１１】従来の各種ＣＳＰの製造工程を示す図であ
る。FIG. 11 is a diagram showing manufacturing processes of various conventional CSPs.
【図１２】ウェハーレベルＣＳＰ技術を用いて作製した
チップの詳細断面を示す図である。FIG. 12 is a view showing a detailed cross section of a chip manufactured by using the wafer level CSP technology.
１，１１，４１：ＩＣチップのボンデングパッド、
２，３，１２，１３，１４，４２，４３：ハンダバンプ
（チップサイズパッケージ（ＣＳＰ；Chip Size Packag
e）の端子）、
４ａ，４ｂ，１５ａ、１５ｂ，１５ｃ：再配線層（また
は再配線）、
２０，３０，４０：ボルテージレギュレータ、
４５：コンデンサ、
４６：ＥＳＲ（Equivalent Series Resistance；等価直
列抵抗）、
４７：出力負荷。1, 11, 41: Bonding pad of IC chip, 2, 3, 12, 13, 14, 42, 43: Solder bump (chip size package (CSP; Chip Size Packag
e) terminal), 4a, 4b, 15a, 15b, 15c: rewiring layer (or rewiring), 20, 30, 40: voltage regulator, 45: capacitor, 46: ESR (Equivalent Series Resistance) , 47: output load.
Claims (5)
を備える半導体装置であって、 前記チップ上の一つのボンディングパッドとＣＳＰの複
数の端子との間をＣＳＰ内の再配線により接続したこと
を特徴とする半導体装置。1. A CSP in which a redistribution layer is formed on a chip
A semiconductor device comprising: one bonding pad on the chip and a plurality of terminals of the CSP are connected by rewiring in the CSP.
ドとＣＳＰの複数の端子との間を接続する再配線の抵抗
値を所望の値になるようにレイアウトしたことを特徴と
する請求項１記載の半導体装置。2. The layout according to claim 1, wherein the resistance value of the rewiring connecting between one bonding pad on the chip and a plurality of terminals of the CSP is set to a desired value. Semiconductor device.
長さ、材質の少なくとも一つを変えてレイアウトするこ
とにより所望の値にすることを特徴とする請求項２記載
の半導体装置。3. The resistance value of the redistribution layer is the width of the redistribution layer,
3. The semiconductor device according to claim 2, wherein at least one of the length and the material is laid out to obtain a desired value.
路を含み、前記再配線のうち、抵抗値が低い再配線が接
続されている端子に出力負荷を接続し、抵抗値が高い再
配線が接続されている端子に位相補償用のコンデンサを
接続したことを特徴とする請求項２記載の半導体装置。4. The chip includes a voltage regulator circuit, wherein an output load is connected to a terminal of the rewiring to which a rewiring having a low resistance value is connected and a rewiring having a high resistance value is connected. 3. The semiconductor device according to claim 2, wherein a capacitor for phase compensation is connected to the terminal.
た再配線の抵抗値が１０ｍΩ〜１０Ωであることを特徴
とする請求項４記載の半導体装置。5. The semiconductor device according to claim 4, wherein the rewiring connected to the phase compensation capacitor has a resistance value of 10 mΩ to 10Ω.
Priority Applications (6)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2001272091A JP4824228B2 (en) | 2001-09-07 | 2001-09-07 | Semiconductor device |
| CNB028175131A CN100367489C (en) | 2001-09-07 | 2002-09-04 | Semiconductor device and voltage regulator |
| EP02760806.6A EP1423876B1 (en) | 2001-09-07 | 2002-09-04 | Semiconductor device and voltage regulator |
| PCT/JP2002/008996 WO2003023851A1 (en) | 2001-09-07 | 2002-09-04 | Semiconductor device and voltage regulator |
| US10/486,885 US7061093B2 (en) | 2001-09-07 | 2002-09-04 | Semiconductor device and voltage regulator |
| US11/331,162 US7550837B2 (en) | 2001-09-07 | 2006-01-13 | Semiconductor device and voltage regulator |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2001272091A JP4824228B2 (en) | 2001-09-07 | 2001-09-07 | Semiconductor device |
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| JP4824228B2 JP4824228B2 (en) | 2011-11-30 |
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Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2003282788A (en) * | 2002-03-25 | 2003-10-03 | Ricoh Co Ltd | Resistive element in csp and semiconductor device equipped with csp |
| JP2007094540A (en) * | 2005-09-27 | 2007-04-12 | Ricoh Co Ltd | Semiconductor device |
| JP2008060423A (en) * | 2006-08-31 | 2008-03-13 | Yamaha Corp | Ic chip, and semiconductor device |
| JP2011503832A (en) * | 2006-12-14 | 2011-01-27 | インテル・コーポレーション | Ceramic package substrate with recessed device |
| JP2011119520A (en) * | 2009-12-04 | 2011-06-16 | Shinko Electric Ind Co Ltd | Method of manufacturing semiconductor device |
| JP2017535054A (en) * | 2014-09-26 | 2017-11-24 | インテル・コーポレーション | Integrated circuit die having backside passive components and methods related thereto |
| JP2018006435A (en) * | 2016-06-28 | 2018-01-11 | 株式会社Ｊｏｌｅｄ | Mounting board |
Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63310139A (en) * | 1987-06-12 | 1988-12-19 | Hitachi Ltd | Semiconductor device and its manufacture |
| JPH09330934A (en) * | 1996-06-12 | 1997-12-22 | Toshiba Corp | Semiconductor device and its manufacture |
| JPH10233401A (en) * | 1997-02-19 | 1998-09-02 | Ricoh Co Ltd | Semiconductor device |
| JP2000183214A (en) * | 1998-12-10 | 2000-06-30 | Sanyo Electric Co Ltd | Chip-sized package and manufacture thereof |
| JP2000353762A (en) * | 1999-06-11 | 2000-12-19 | Toppan Printing Co Ltd | Wiring material and conductor wiring layer using the same |
| JP2001216036A (en) * | 1999-12-23 | 2001-08-10 | Texas Instr Inc <Ti> | Voltage regulator |
| JP2002314028A (en) * | 2001-04-17 | 2002-10-25 | Iep Technologies:Kk | Semiconductor device, manufacturing method therefor, and mounting structure thereof |
-
2001
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Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63310139A (en) * | 1987-06-12 | 1988-12-19 | Hitachi Ltd | Semiconductor device and its manufacture |
| JPH09330934A (en) * | 1996-06-12 | 1997-12-22 | Toshiba Corp | Semiconductor device and its manufacture |
| JPH10233401A (en) * | 1997-02-19 | 1998-09-02 | Ricoh Co Ltd | Semiconductor device |
| JP2000183214A (en) * | 1998-12-10 | 2000-06-30 | Sanyo Electric Co Ltd | Chip-sized package and manufacture thereof |
| JP2000353762A (en) * | 1999-06-11 | 2000-12-19 | Toppan Printing Co Ltd | Wiring material and conductor wiring layer using the same |
| JP2001216036A (en) * | 1999-12-23 | 2001-08-10 | Texas Instr Inc <Ti> | Voltage regulator |
| JP2002314028A (en) * | 2001-04-17 | 2002-10-25 | Iep Technologies:Kk | Semiconductor device, manufacturing method therefor, and mounting structure thereof |
Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2003282788A (en) * | 2002-03-25 | 2003-10-03 | Ricoh Co Ltd | Resistive element in csp and semiconductor device equipped with csp |
| JP2007094540A (en) * | 2005-09-27 | 2007-04-12 | Ricoh Co Ltd | Semiconductor device |
| JP2008060423A (en) * | 2006-08-31 | 2008-03-13 | Yamaha Corp | Ic chip, and semiconductor device |
| JP4561714B2 (en) * | 2006-08-31 | 2010-10-13 | ヤマハ株式会社 | IC chip and semiconductor device |
| JP2011503832A (en) * | 2006-12-14 | 2011-01-27 | インテル・コーポレーション | Ceramic package substrate with recessed device |
| US8264846B2 (en) | 2006-12-14 | 2012-09-11 | Intel Corporation | Ceramic package substrate with recessed device |
| JP2011119520A (en) * | 2009-12-04 | 2011-06-16 | Shinko Electric Ind Co Ltd | Method of manufacturing semiconductor device |
| JP2017535054A (en) * | 2014-09-26 | 2017-11-24 | インテル・コーポレーション | Integrated circuit die having backside passive components and methods related thereto |
| US10790263B2 (en) | 2014-09-26 | 2020-09-29 | Intel Corporation | Integrated circuit die having backside passive components and methods associated therewith |
| JP2018006435A (en) * | 2016-06-28 | 2018-01-11 | 株式会社Ｊｏｌｅｄ | Mounting board |
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| Publication number | Publication date |
|---|---|
| JP4824228B2 (en) | 2011-11-30 |
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