JP2003086106A - Plasma display panel and display method as well as driving circuit and driving method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a plasma display panel capable of high definition display and its display method and its driving circuit and driving method. SOLUTION: A barrier rib 15 is vertically divided at the dimension of unit light emitting region SP and shifted its position half pitch in the horizontal direction. A pixel consisting of combination of the unit light emitting regions SP has a narrow pixel pitch in horizontal direction and thus the apparent horizontal resolution is enhanced. Such pixel can be appropriately displayed by coordinating the 'address' consisting of a sequential order of a sustaining electrode for identifying each unit light emitting regions SP and an address electrode 13 and rearranging the order of the image data.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a plasma display panel for displaying by utilizing plasma discharge and a display method thereof.
Also, the present invention relates to a driving circuit for driving the same and a driving method thereof.

[0002]

2. Description of the Related Art Plasma display (PDP: Plasma)
A display panel) is a display that irradiates a phosphor with vacuum ultraviolet rays generated by gas discharge to emit light, and is expected to be marketed as a thin / large screen display.

FIG. 19 is a schematic diagram showing a conventional plasma display panel for color display. The plasma display panel 100 has a configuration in which a front glass substrate 101 and a rear glass substrate 102 on the display surface side are arranged to face each other with a discharge space therebetween. A pair of sustain electrodes 107 (107X, 107Y) is provided in parallel on front glass substrate 101, and bus electrodes 110X, 110Y are integrally provided on each of sustain electrodes 107X, 107Y to reduce resistance. ing. On the sustain electrode 107, the dielectric layer 108,
The protective layer 109 is provided in order.

On the other hand, the address electrodes 103 are arranged in parallel on the rear glass substrate 102, and the dielectric layer 104 and the partition walls 105 are sequentially provided on the address electrodes 103. The discharge space is partitioned for each address electrode 103 by the partition walls 105 extending in a stripe shape, and red (R; Red), green (G; Green) and blue (B; Blue) are provided inside the partitioned region.
The primary color phosphors 106 are periodically provided. In addition,
Each address electrode 103 is a sustain electrode 1 when viewed from the display surface side.
The electrode matrix is formed in a positional relationship orthogonal to 07.

The plasma display panel 100 includes a sustain electrode 1
07X, 107Y pair discharge and sustain electrode 1
Light emission is performed by the discharge between 07Y and the address electrode 103, and as shown in FIG. 20, the minimum light emission unit is the intersection of the matrix, that is, the pair of the sustain electrodes 107 and the address electrode 103. The light emitting unit area SP ₁₀₀ which is an area is set. Also, phosphor 1
One pixel (pixel) P ₁₀₀ is configured by three adjacent light emitting unit regions (sub-pixels) SP ₁₀₀ , where 06 is red, green and blue, respectively. As can be seen from the figure, the light emitting unit region SP ₁₀₀ is partitioned only by the partition wall 105 in the direction in which the sustain electrodes 107 extend, that is, in the horizontal direction of the display screen, and in the direction in which the address electrodes 103 extend, that is, in the display screen. In the vertical direction, those having the same phosphor 106 sandwiched between the same partition walls 105 are arranged in parallel. The pixels P _100, which are usually square, are thus arranged in a grid pattern at a constant pitch in the horizontal and vertical directions.

[0006]

By the way, recent IT
Due to technological advances and expectations of the future broadband era, extremely high definition is required for personal computers and displays. On the other hand, in order to improve the definition of the plasma display panel 100, the area of each light emitting unit region SP ₁₀₀ is reduced to reduce the pixel P _100.
There is no choice but to narrow the pitch. However, in the past,
Since the negative glow discharge is used for the light emission display, the distance between the electrodes needs to be about 100 μm or more.
₁₀₀ is built in the size according to this. for that reason,
The area of the light emitting unit region SP ₁₀₀ is equal to the sustain electrodes 107X, 1
However, it is difficult to reduce the size due to the size of the electrodes and the number of electrodes, and it is extremely difficult to increase the definition.

The present invention has been made in view of the above problems, and an object thereof is to provide a plasma display panel capable of realizing a high-definition display, a display method thereof, and a drive circuit and a drive method thereof. is there.

[0008]

A plasma display panel according to the present invention is provided with a plurality of light emitting unit regions arranged so that a predetermined number of them are displaced.

In the display method of the plasma display panel according to the present invention, a plurality of light emitting unit areas are arranged so that a predetermined number of light emitting units are displaced, and light emission control of the light emitting unit areas is performed based on an input signal. .

The driving circuit of the plasma display panel according to the present invention is electrically connected to the plasma display panel having a plurality of light emitting unit regions arranged so as to be displaced by a predetermined number and driven by an input signal. Generate a signal for
It is configured to control the light emission of each of the light emitting unit areas based on a driving signal.

According to the driving method of the plasma display panel of the present invention, in order to drive the plasma display panel having a plurality of unit light emitting regions arranged so that a predetermined number of positional deviations occur, driving is performed from an input signal. Signal is generated and the light emission of each light emitting unit area is controlled based on the driving signal.

In the plasma display panel and the display method of the plasma display panel according to the present invention, the pitch of the pixels formed by the combination of the light emitting unit regions in at least one direction in the horizontal direction or the vertical direction is in the conventional pixel array or in the oblique direction of itself. It becomes narrower than the pitch.

According to the driving circuit of the plasma display device and the driving method of the plasma display panel of the present invention, in the plasma display panel of the present invention, the input signal is applied so that the display is properly performed by the pixels having different shapes or arrangements from the conventional one. Based on this, the shape and position of the pixel are controlled.

[0014]

BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

[First Embodiment] FIG. 1 is a schematic diagram showing a plasma display panel according to a first embodiment of the present invention, and FIG. 2 is a plasma display panel shown in FIG. FIG. 3 is a plan view showing a main part configuration viewed from the display surface side of FIG. This plasma display panel 10 (hereinafter referred to as panel 10) is similar to the conventional plasma display panel 100 except that the shape of the partition wall 15 and the relative arrangement of the address electrodes 13 with respect to the partition wall 15 are different. It is composed.

That is, the front glass substrate 11 and the rear glass substrate 12 are arranged so as to face each other with a discharge space interposed therebetween, and are hermetically sealed at the peripheral edge thereof.
A discharge gas made of one or more of rare gases of e, Ne, Ar, Xe, and Kr is enclosed. Further, the front glass substrate 11 needs to be made of a highly transparent material because it is located on the display surface side, and for example, high strain point glass or soda lime glass is used. On the front glass substrate 11, for example, ITO (Indium-Tin Oxi) which is a transparent electrode material is used.
de) multiple sets of sustain electrodes 17 (17X, 17Y)
Is provided. Although not shown, a bus electrode made of a metal such as Al may be attached to each of the sustain electrodes 17X and 17Y in order to reduce electric resistance. Further, a dielectric layer 18 made of, for example, SiO ₂ is provided on the sustain electrode 17, and a protective layer 19 made of, for example, MgO is further provided thereon.

On the other hand, the rear glass substrate 12 is made of, for example, the same material as the front glass substrate 11, on which address electrodes 13 made of a metal thin film such as aluminum (Al) are arranged in parallel. There is. These address electrodes 13 are arranged so that their extension directions are orthogonal to each other when viewed from the display surface side to form a matrix, and each of the regions where the address electrodes 13 and the sustain electrodes 17 intersect is formed. It is a light emitting unit area SP.
The sustain electrode 17Y corresponds to a horizontal scanning line in the panel 10, the extension direction thereof is the horizontal direction of the screen, and the extension direction of the address electrode 13 is the vertical direction of the screen. Therefore, hereinafter, the arrangement and positional relationship of the address electrode 13, the sustain electrode 17, the partition wall 15, the light emitting unit region SP or the pixel P will be expressed by using two directions, horizontal and vertical.

Further, a dielectric layer 14 made of, for example, silicon dioxide (SiO ₂ ) is provided on the address electrode 13, and a partition wall for partitioning the discharge space into each light emitting unit region SP is provided thereon. 15 are provided. In the present embodiment, the partition walls 15 are formed in a straight line that is divided into lengths according to the dimensions of the light emitting unit regions SP, are arranged in parallel in the horizontal direction, and are separated in the vertical direction at each position. The light-emission unit regions SP are arranged so as to be displaced by half the width (half pitch). Thereby, each light emitting unit area SP
Are formed in a rectangular shape, and the arrangement is linear in the horizontal direction, and adjacent ones in the vertical direction are displaced from each other by a half pitch in the horizontal direction.

In addition, phosphors 16 of three primary colors of red (R), green (G) and blue (B) are shown in FIG. 2 in the portion of the partition wall 15 and the dielectric layer 14 facing the discharge space. Is provided. That is, in each light emitting unit region SP divided by the partition wall 15, the phosphors 16 of different colors from those adjacent to each other are arranged.

The address electrodes 13 in the present embodiment are sewn between the partition walls 15 and extend in the vertical direction while changing their relative positions with respect to the respective light emitting unit regions SP, and have a linear shape as a whole. There is. The width and sectional shape of the address electrode 13 and the partition wall 15 are set in the same manner as in the conventional case.

This panel 10 can be manufactured in the same manner as in the usual case except that the shape of the partition wall 15 and the formation position of the address electrode 13 corresponding thereto are different. For example, it is manufactured as follows. To be done.

First, a front glass substrate 11 is prepared, and a transparent electrode material such as ITO is used to form a pattern of, for example, sputtering or screen printing to form a pair of stripe-shaped sustain electrodes 17. Then, along one side edge of these sustain electrodes 17, for example, A
A bus electrode is formed in the same manner as the sustain electrode 17 using a highly conductive metal material such as g, Al, Ni, Cu or Cr. After that, for example, SiO ₂ is CVD (Chemical Vap
or Deposition) method or a printing method to form a dielectric layer 18, and a protective layer 19 made of MgO is formed on the entire surface of the dielectric layer 18 by, for example, an electron beam evaporation method.

Next, a back glass substrate 12 is prepared, and a highly conductive metal material such as Ag, Al, Ni, Cu, Cr is formed on the back glass substrate 12 in a stripe shape by sputtering or screen printing. , Address electrodes 13 are formed. Next, for example, SiO ₂ is deposited by the CVD method or the printing method to form the dielectric layer 14.

Next, a glass paste is patterned in a predetermined area on the dielectric layer 14 by a screen printing method as described above, and is shaped into a stripe shape by a sandblasting method, and then baked. Thus, the partition wall 15 is formed. Originally, the formation of the partition having a minute three-dimensional structure is a difficult step in the panel manufacturing process. However, in this embodiment, since each partition 15 has the same linear shape as the conventional one, it is almost the same as the conventional one. Formed with difficulty.

Next, the phosphors 16 are formed in a predetermined arrangement by printing or applying and exposing, for example, phosphor slurry from the side surfaces of the adjacent partition walls 15 to the dielectric layer 14 between them.

Next, the front glass substrate 11 and the rear glass substrate 12 are assembled. For example, a seal layer made of low melting point glass is formed on the peripheral portion of the front glass substrate 11 by screen printing. After that, the front glass substrate 11 and the rear glass substrate 12 are attached to each other so that the sustain electrodes 17 and the address electrodes 13 are orthogonal to each other, and the seal layer is baked and cured. Further, the discharge space between the front glass substrate 11 and the rear glass substrate 12 is evacuated and the mixed gas is sealed. In practice, the substrates 11 and 12 are displaced and bonded to each other so that the end portions of the electrodes 13 and 17 are led out from the main body portion, and the display drivers 35, which will be described later, are connected to the electrodes 13 and 17 as power supply terminals.

FIG. 3 shows the configuration of the pixel P in the panel 10. Here, among the light emitting unit areas SP extending over two lines, three light emitting unit areas SP that respectively emit light in R, G, and B are combined in a triangular shape to form one pixel P, and this pixel P is horizontal. The directions are opposite to each other. The pixels P have such a shape and arrangement that the partition walls 15 are displaced in the vertical direction as described above, so that the light emitting unit regions SP are displaced by a predetermined number. Derived from. Further, since the light emitting unit area SP has a rectangular shape, the two sides of the pixel P are not straight lines but are stairsteps and not a precise triangle. However, the effect of this pixel shape is as described in the next paragraph. In the present invention, the shape of a pixel is triangular regardless of whether the hypotenuse is a straight line or a step, and the position of each vertex of the triangle is the same as in the present embodiment. Each unit light emitting area SP
Including the case where is arranged. In the following explanation,
The emission color and the pixel P to which each emission unit region SP belongs
In order to indicate the difference between (P1, P2, P3, ...), the suffixes of R1, G1, B1, R2, G2, B2 ,. In addition, the pixel P of the address electrode 13
1 to P3 are individually referred to as address electrodes A1 to A9 in order from the left as illustrated.

The shape and arrangement of the pixels P have the following advantages over the conventional pixel arrangement. In other words, the horizontal pixel pitch becomes narrower than the conventional horizontal pixel pitch or its own diagonal pixel pitch. Even if the number of pixels is the same as in the conventional case, the apparent horizontal resolution is improves. It is known that the human visual system has a higher resolution in the horizontal and vertical directions than in the oblique direction according to the spatial frequency characteristics of natural phenomena, and in the present embodiment, thanks to the visual characteristics of the viewer, Thus, the displayed image can be shown with high definition. It should be noted that such an effect is produced by arranging the light-emission unit regions SP, which are the constituent units of the pixel P, by being displaced by a predetermined number, and the light-emitting unit regions SP may be configured as such. For example, it is exhibited in pixels of any shape.

FIG. 4 is a block diagram showing the configuration of the drive circuit according to the present embodiment. The panel 10 is electrically connected to the drive circuit 30 and performs display in units of pixels P by the drive voltage input from the drive circuit 30. The drive circuit 30 includes an A / D converter 31 that performs analog / digital (hereinafter referred to as “A / D”) conversion on the input video signal SV to generate video data DV, and an A / D converter 31. Image memory 32 for storing video data DV
A timing controller 33 that controls the operation timing of the A / D converter 31, the image memory 32, and the display driver 35, and a scramble circuit 34 that rearranges the video data DV so as to properly correspond to each light emission unit area SP. ,
The display driver 35 mainly outputs a drive voltage corresponding to the input video data DV to each light emitting unit area SP.

Of these, the image memory 32 is a signal storage means capable of storing at least two lines of video data DV for rearranging the video data DV which will be described in detail later. Further, when the drive circuit 30 is operated based on the subfield drive method, a memory for storing the video data DV is always required, and therefore the image memory 3 is stored in this memory.
The drive circuit 30 can be configured without adding a memory separately. The scramble circuit 34 transfers the video data DV to the image memory 3
The scramble circuit 34 is rearranged when writing to or reading from the image memory 2. Here, the scramble circuit 34 is connected between the image memory 32 and the display driver 35, and when the video data DV is read from the image memory 32. Sorting is done.

Next, the panel 10 and the drive circuit 30
The operation of will be described.

Here, it is assumed that the panel 10 is driven by the driving circuit 30 by the subfield driving method. The subfield driving method is a general driving method for such a display panel. One field is time-divided into several subfields, and the light emitting unit area SP is controlled to emit light for each subfield. SP brightness 1
It is a method of adjusting in field units. The selective erasing method will be described here as an example.
Each subfield is usually started by a reset period and divided into three periods of an address period and a display period that follow.

In the reset period, as usual, the display driver 35 controlled by the timing control section 33 applies a predetermined voltage to all the sustain electrodes 17X and 17Y to perform preliminary discharge between the pair of electrodes. As a result, so-called wall charges are formed on the protective layer 19 in the entire light emitting unit region SP.

In the next address period, the display driver 35
Under the control of the timing controller 33, the voltage is sequentially applied to the sustain electrodes 17Y arranged in parallel one after another, and at the same time, the address electrodes 1Y are synchronized with the scanning timing.
The voltage is also applied to 3. The input voltage to the address electrode 13 is based on a signal generated from a video signal SV, which will be described later, and is a light emitting unit region S that does not emit light in the horizontal light emitting unit region SP sharing the sustain electrode 17Y.
It is adapted to be applied to the address electrode 13 belonging to P. In addition, the sustain electrode 17Y and the address electrode 13
The value of the input voltage to is set so that the address discharge occurs only when a voltage is applied to both electrodes. As a result, the wall charges are erased from the light emitting unit region SP that does not emit light.

Next, during the display period, the display driver 35 controlled by the timing control section 33 normally applies an AC pulse voltage between all the sustain electrodes 17X and 17Y during the display period. In the light emitting unit region SP where the wall charge remains at this point, the potential of the wall charge is superimposed on the pulse voltage, and the sustain electrode 1
The discharge start voltage is reached between 7X and 17Y, and sustain discharge occurs. This discharge is a high-frequency discharge, and at the same time, charges are accumulated, so that discharge is continuously generated and the discharge state is maintained. During this time, the fluorescent substance 16 emits light by being irradiated with the ultraviolet rays emitted by the discharge gas. Thus, during the display period, each pixel P is displayed in a predetermined color by selectively causing the light emitting unit area SP to emit light. By superimposing these subfields in time series, the luminance of each light emitting unit region SP corresponding to one field is weighted, and a gradation-controlled image is displayed.

In this series of operations, the color and gradation of each pixel P are controlled by the drive voltage applied to the address electrode 13 during address discharge, more directly during address discharge. In this embodiment, the control operation of the address discharge by the drive circuit 30 is performed as follows.

The A / D converter 31 includes a timing controller 3
The input video signal SV is A / D converted based on the sampling control by 3 and a series of digital signals indicating the brightness of each of the three primary colors for each pixel S, that is, the video data DV
Convert to. The video data DV generated here
Has been converted to data for each subfield.

FIG. 5A shows data strings dR1, dG1, dB1, ... Of the video data DV. Each data d
R, dG, and dB are the respective light emitting unit regions SPR, SPG, S
Video data for PB, and further data dR, d
G and dB form one set, and one pixel P (P1, P2, P
3, ...) and the luminescent color. In this figure, for the sake of simplicity, three pixels P arranged in the horizontal (scanning) direction are arranged.
One set of data is one line of data, and two lines of video data DV are represented.

At this stage, the video data DV is in a state corresponding to the conventional arrangement of the pixels P ₁₀₀ , and the continuous data dR, dG, and dB for each line sequentially constitute data for one pixel. In other words, if line scanning is performed in this order, the light emitting unit area SP is subject to light emission control according to the conventional pixel P ₁₀₀ . For example, if the shaded data in FIG. 5A indicates light emission, a total of nine address electrodes A1 to A9 corresponding to the data dR1, dG1, dB1, ... As shown in FIG. A voltage is applied accordingly to the light-emission unit area SP, and the light-emission unit area SP is subjected to light-emission control corresponding to the data arrangement. However, as described above, the light emitting unit area SP of the panel 10 is different from the conventional one in the light emitting color and the pixel shape, and the array of the data dR1, dG1, dB1, ... Does not correspond to the light emitting unit area SP as it is.

Under the control of the timing control section 33, the image data 32 is stored in the image memory 32 in line units or field units, for example. The stored video data DV is read from the image memory 32 under the control of the timing control unit 33, and further, the scramble circuit 3
4 rearranges the respective data dR, dG and dB of the video data DV according to the shape and arrangement of the pixels P on the panel 10.

The rearrangement is carried out by assigning each data d to the "address" of each light emitting unit region SPR, SPG, SPB identified by the arrangement order of the line (sustain electrode 17Y) and address electrode 13.
This is performed by associating the input timing of R, dG, and dB with the arrangement order. For example, the light emitting unit region SPR1
Is (the order of the lines, the order of the address electrodes 13 counted from the left) = (1,1), and therefore the corresponding data dR1 may be set to be input to the address electrode A1 at the scanning timing of the first line. . Similarly, in order to display the pixels P1 to P6 having the arrangement of the light emitting unit regions SP shown in FIG. 3, the data dR1, dG1, and dB at the scanning timing of the first line with respect to the address electrodes A1 to A9.
2, dR3, dG3, ... At the scanning timing of the second line, data dB1, dR2, dG2, dB3, dR
It can be seen that the voltages corresponding to 4, ... Must be input in order. Therefore, the video data DV is rearranged by the scramble circuit 34 as shown in FIG.

When viewed from the side of the address electrodes A1 to A9, this is dR1, dB1, ... For the first address electrode A1 from the left for each line scan, and dG1, dR2 for the second address electrode A2. , Is a data array to which a voltage corresponding to is input. In this way, the data dR
The array of 1, dG1, dB1, ... Corresponds to the light emitting unit regions SPR, SPG, SPB of the panel 10.

The data dR, dG, and dB may be rearranged in units of two lines that form the pixel P, or for one field of the video data DV read from the image memory 32. You can go all at once. Then, the scramble circuit 34 outputs the video data DV rearranged according to the pixel P to the display driver 35.

The display driver 35 generates a drive voltage for address discharge based on the input video data DV,
It outputs to the panel 10 based on the timing control by the timing control unit 33. FIG. 7 shows a drive voltage waveform based on the rearranged video data DV. In this way, the display driver 35 changes the information of the data dR1, dG1, dB1, ... To the driving voltage and outputs it to the address electrode 13, and the light emitting unit regions SPR, SPG, S that correspond to the data correctly.
The light emission of PB is controlled. Therefore, in the panel 10 driven by the drive circuit 30, the triangular pixels P are properly displayed.

As described above, according to the present embodiment, the partition wall 15 is formed at a position displaced by half the width (half pitch) of the light emitting unit region SP in the vertical direction. The columns of the light emitting unit regions SP are formed such that vertically adjacent ones are shifted from each other by a half pitch in the horizontal direction. Therefore, the emission unit area S of two lines
Pixels P are formed in a triangular shape by combining three light-emission unit regions SP that emit R, G, and B, respectively, over P, and these can be arranged so as to be arranged in opposite directions in the horizontal direction. . In this pixel P, the pixel pitch in the horizontal direction is narrower than the pixel pitch in the conventional pixel array or in the diagonal direction of itself, so that the apparent horizontal resolution is improved without changing the number of pixels. Therefore, it is possible to perform high-definition display based on the physiological characteristics on the viewer side without physically reducing the area of the light emitting unit region SP.

Further, since the partition wall 15 of the panel 10 is in a straight line shape and is constructed in the same manner as the conventional one except for the relative arrangement of the address electrode 13 and the partition wall 15, the manufacturing process conditions are changed. You don't have to. Therefore, it is possible to manufacture while maintaining yield, throughput, manufacturing cost, and the like.

Further, in the present embodiment, the image memory 32
The video data DV read from the scramble circuit 34
Since the pixels are rearranged in accordance with the arrangement of the pixels P, the display by the triangular pixels P can be realized without making a large change in the driving method.

(Modification 1) FIG. 8 is a partial plan view showing the configuration of the panel and the pixel shape in Modification 1 of the first embodiment. In the above-described first embodiment, the partition wall 15 of the panel 10 is vertically divided into each column of the light emission unit areas SP, but in this modification, the partition wall 15 ′ has two rows of the light emission unit areas SP. It is periodically divided every minute, and is horizontally offset from each other by a half pitch in units of two lines in the vertical direction. In addition, the pixel P in this case
As shown in the drawing, the arrangements are adjacent to each other not only in the horizontal direction but also in the vertical direction. Also in this case, the pixel display can be performed by the same driving method as that of the first embodiment, and other configurations, actions, and effects of this modification are the same as those of the first embodiment.

(Modification 2) FIG. 9 is a partial plan view showing a pixel shape in Modification 2 of the first embodiment. In this modified example, the pixel P ′ is displayed on the panel 10. The pixel P ′ is composed of three light emitting unit regions SPR, SPG, and SPB arranged in the horizontal direction as in the conventional case, but two adjacent pixels in the vertical direction are adjacent to each other.
The pixels are arranged so as to be displaced by one pixel (1.5 pitch) in the horizontal direction. In this case, the vertically adjacent pixels P ′
The pixel pitch in the horizontal direction can be narrowed due to the misalignment of the arrangement, and the apparent horizontal resolution is improved. Therefore, also in this modification, the definition of the display image can be improved.

The display of the pixel P'can be easily realized by displacing the address electrodes 13 to which the drive voltage is applied every other line. For that purpose, for example, when the video signal SV is A / D converted by the A / D converter 31, the sampling timing for each line is delayed every other line by a period corresponding to one address electrode, or It is preferable to shift the timing when the voltage signal is input from the display driver 35 to the address electrode 13,
The timing control unit 33 may have such a function. Here, in this way, the data dR, dG, dB
Is rearranged, and the scramble circuit 34 is not particularly provided.

Thus, even if the panel structure is the same, each data dR1, dG1, dB of the video data DV is obtained.
By rearranging 1, dR2, dG2, dB2, ..., It is possible to change the shape and arrangement of the pixels. The other configurations, operations, and effects of this modification are the same as those of the first embodiment.

(Modification 3) FIG. 10 is a partial plan view showing the configuration of a pixel in Modification 3 of the first embodiment. This modified example is a case where the pixel P ′ is selected as in the modified example 2 in the panel described in the modified example 1, and the pixel P ′ is displayed by driving in the same manner as in the modified example 2. Other configurations, actions and effects are
This is the same as the second modification.

(Modification 4) FIG. 11 is a partial plan view showing a pixel configuration and an arrangement of address electrodes in Modification 4 of the first embodiment. Here, in the panel 10 of the first embodiment described above, the address electrodes 13 'are provided in each of the light emitting unit regions SP having different positions in the horizontal direction. Here, the address electrodes 13' are displaced in the horizontal direction. The address electrode 13 'corresponding to the line portion is drawn out. This panel has the same configuration as that of the first embodiment except that the horizontal pitch of the address electrodes 13 'is different from that of the address electrodes 13, and can be manufactured in the same manner. In this case, the driving voltage is alternately input to the two pairs of the address electrodes 13 ′, which are set every other line, and the signal voltage is further inputted as in the first embodiment. By doing so, the display is performed by the triangular pixels P, and by driving in the same manner as in the second modification, it is possible to perform display by the square pixels P ′ having a different arrangement from the conventional one. Therefore, the operation and effect thereof are the same as those of the first embodiment or the modification 2 depending on the pixel shape.

[Second Embodiment] FIG. 12 is a plan view showing a main part of a plasma display panel according to a second embodiment of the present invention. This plasma display panel 20
(Hereinafter, referred to as panel 20) is different from panel 10 in the above-described first embodiment except that address electrode 13 is replaced by address electrode 23 having a different shape and arrangement with respect to light emitting unit region SP. Is configured similarly to. Therefore, in the following description, the same parts as those in the first embodiment are designated by the same reference numerals,
Description is omitted as appropriate.

The address electrodes 23 are located at positions horizontally shifted for each column of the light emitting unit areas SP (here, they are offset by 1.5 pitches), and the light emitting unit areas SP coated with the same type of phosphor 16 are applied. It is formed in a meandering shape so as to penetrate it. Note that the pixel P is displayed in the same manner as in the first embodiment, and the first line and the second line in FIG.
Pixels P by the line are sequentially arranged from the left to pixels P1, P2, P
Set to 3.

The rearrangement of the video data DV here is carried out based on the same idea as in the first embodiment.
In order to display the pixels P1 to P3 shown in FIG. 12, voltages corresponding to the data dB1, dR2, dG2, and dB3 are sequentially input from the left to the address electrodes 23 at the scanning timing of the first line, and the second line is displayed. It can be seen that the voltages corresponding to the data dR1, dG1, dB2, dR3, dG3 must be input at the scanning timing of. Therefore, the video data DV is rearranged in the above order by the scramble circuit 34.

As seen from the address electrode 23 side,
The first from the left is dR1, ... for each line scan, the second is dG1, ..., The third is dB1, dB2, ...
.. The voltage corresponding to is input. In this way, since the voltage corresponding to the light emitting unit region SP of the unique light emitting color is applied to each address electrode 23,
The drive voltage can be set to a voltage value suitable for each color. By the way, as a method for adjusting the color temperature of the emission color of the phosphor in various displays, it is generally known to change the pixel area or the driving voltage according to the color, and the present embodiment It is possible to deal with such a case. Further, in the conventional plasma display panel, since each address electrode 103 belongs only to the light emitting unit region SP ₁₀₀ of a unique light emitting color, the display driver is divided into R, G, and B circuits for each color. The address electrode 103 is managed by the input terminal, and the video data dR, dG, and dB are input to the circuit corresponding to the color of the display driver. On the other hand, the address electrode 2 of the panel unit 20
Since 3 is also wired so as to belong only to the light emitting unit region SP of the unique light emitting color, the change points from the related art in the drive circuit and the control method can be further reduced.

In this case, it is necessary to shift the head address electrode 23 by two lines to the left and right to input the drive voltage for each line scanning, and the display driver 35 applies the voltage to the address electrode 23. The timing control unit 33 performs the input.

Other functions and effects of this embodiment are the same as those of the first embodiment. Further, modified examples of the second embodiment corresponding to modified examples 1 to 3 of the first embodiment are shown in FIGS. 13, 14 and 15, respectively. These driving circuits and driving methods are also set as described in the first embodiment and the modified examples 1 to 3 to which each drawing corresponds.

The present invention is not limited to the above-mentioned embodiments, and various modifications can be made. For example, in the above-described embodiment, a case has been described in which the partition 15 is formed by being displaced, so that the light emitting unit regions SP are displaced and arranged, and the pixel arrangement is displaced in the horizontal direction of the screen.
The light emitting unit region SP is defined as a minimum unit of light emission including a space where the sustain electrode and the address electrode are orthogonal to each other, and the shape thereof is not always completely dependent on the shape of the partition wall 15. As shown by the address electrode 23 in the second embodiment, by deforming the sustain electrode or the address electrode, it is possible to cause the displacement of the light emitting unit region even if the partition shape remains the same. It is possible.

FIG. 16 shows an example thereof. In this panel, the sustain electrode 37 is formed by bending, and the other components, the partition wall 105, the address electrode 103 and the like are all the same as those of the conventional panel 100. In this way, the spacing of the sustain electrodes 37, the shape and arrangement of the pixels are changed, and as described in the first embodiment, when a voltage signal is input and driven according to the pixel to which each sustain electrode 37 belongs, The light emitting unit areas S whose arrangement is displaced with respect to the vertical direction of the display screen
It is possible to display P. In that case, the pixel pitch in the vertical direction is narrowed, and the vertical resolution is improved. As described above, according to the present invention, it is sufficient that the pixel arrangement is shifted in either the horizontal or vertical direction, and the resolution in the horizontal and vertical directions can be improved as compared with the conventional pixel arrangement.

Further, in the above embodiment, the three light emitting unit areas SP are arranged to constitute one pixel P. However, in the case of adopting a system in which each light emitting unit area SP corresponds to the pixel P in a monochrome display or the like. The present invention is also applicable.

Further, in the above-mentioned embodiment, although the linear partition walls 15 and 15 'are provided on the panel 10 or the panel 20, as shown in FIGS. It is possible to provide a cell-shaped partition wall 15 "which is also partitioned in the horizontal direction.

Further, in the above embodiment, the scramble circuit 34 is connected to either the front or the rear of the image memory 32, but the scramble circuit may be provided in any of the drive circuits.

In addition, in the above embodiment, the driving method based on the assumption that scanning is performed for each line has been described. However, for example, a method of scanning every several lines or scanning all the lines at the same time. The driving method of the present invention may be applied to any driving method as long as display by the pixels of the present invention is realized by exchanging image information according to the shape and arrangement of the pixels. Is also applicable.

[0066]

As described above, according to the plasma display panel of the present invention, since the arrangement of the light emitting unit areas is displaced every predetermined number, the pixels formed by the light emitting unit areas are arranged. In, the pitch in at least one of the horizontal and vertical directions of the display screen is narrower than the pitch in the conventional pixel arrangement or the diagonal direction of the display screen, and even if the number of pixels is not changed, it is apparent in at least one of the horizontal and vertical directions. The resolution of is improved. Therefore, high-definition display can be performed based on the physiological characteristics on the viewer side without physically reducing the area of the light emitting unit region. Further, the plasma display panel of the present invention can be realized by simply changing a part of the partition wall shape, the electrode wiring, and the drive circuit in the conventional plasma display panel according to the shape and arrangement of the pixels, so that high definition is achieved. However, it is possible to manufacture while maintaining the yield, the throughput, the manufacturing cost, and the like, which are comparable to those in the past. In particular, since the partition wall has a linear shape, it can be easily manufactured.

Further, according to the display method of the plasma display panel of the present invention, in the plasma display panel of the present invention, the light emission control of the light emission unit area is performed based on the input signal. Pixels in which the pitch in at least one direction is narrower than the conventional pixel array or the pitch in the diagonal direction of the pixel array are displayed. Therefore, even if the number of pixels is not changed, the apparent resolution in at least one of the horizontal and vertical directions can be improved, and high-definition display can be realized.

Further, according to the driving circuit and the driving method of the plasma display panel of the present invention, the driving circuit is electrically connected to the plasma display panel of the present invention to generate the driving signal from the input signal, and to drive the signal. Since the light emission of each light emitting unit region is controlled based on the above, it becomes possible to properly perform display by the pixels having a different shape or arrangement from the conventional one in the plasma display panel of the present invention.

[Brief description of drawings]

FIG. 1 is a perspective view showing a schematic configuration of a plasma display panel according to a first embodiment of the present invention.

FIG. 2 is a partial plan view showing a main configuration of the plasma display panel shown in FIG.

FIG. 3 is a configuration diagram for explaining an array of pixels in the plasma display panel shown in FIG.

FIG. 4 is a block diagram of a driving circuit of the plasma display panel shown in FIG.

5 is an explanatory diagram for explaining a data array of video data in the drive circuit shown in FIG. 4, where (A) is video data immediately after being converted from a video signal, and (B) is data rearrangement. The video data after is shown.

FIG. 6 is a diagram showing a driving sequence of the plasma display panel based on the image data of the array shown in FIG.

7 is a diagram showing a driving sequence of the plasma display panel based on the image data of the array shown in FIG. 5 (B).

FIG. 8 is a partial plan view showing a main configuration of a plasma display panel according to Modification 1 of the first embodiment.

FIG. 9 is a partial plan view showing a main configuration of a plasma display panel according to a modified example 2 of the first embodiment.

FIG. 10 is a partial plan view showing a main configuration of a plasma display panel according to Modification 3 of the first embodiment.

FIG. 11 is a partial plan view showing a main configuration of a plasma display panel according to Modification 4 of the first embodiment.

FIG. 12 is a partial plan view showing a configuration of a main part of a plasma display panel according to a second embodiment of the present invention.

FIG. 13 is a partial plan view showing a main configuration of a plasma display panel according to a modified example of the second embodiment.

FIG. 14 is a partial plan view showing a main configuration of a plasma display panel according to a modification of the second embodiment.

FIG. 15 is a partial plan view showing a main configuration of a plasma display panel according to a modified example of the second embodiment.

FIG. 16 is a partial plan view showing the configuration of the main part of another plasma display panel of the present invention.

FIG. 17 is a partial plan view showing a main configuration of a plasma display panel according to a modified example of the first embodiment.

FIG. 18 is a partial plan view showing a main configuration of a plasma display panel according to a modified example of the second embodiment.

FIG. 19 is a perspective view showing a basic structure of a conventional plasma display panel.

20 is a configuration diagram for explaining an array of pixels in the conventional plasma display panel shown in FIG.

[Explanation of symbols]

10, 20 ... Plasma display panel, 11 ... Front glass substrate, 12 ... Back glass substrate, 13, 13 ', 23 ... Address electrode, 14 ... Dielectric layer, 15, 15', 15 "... Partition wall, 16 ... Phosphor , 17, 37 ... Sustain electrodes, 18 ... Dielectric layer, 19 ... Protective layer, 30 ... Driving circuit, 31 ... A / D converter, 32 ... Image memory, 33 ... Timing control unit, 3
4 ... Scramble circuit, 35 ... Display driver.

─────────────────────────────────────────────────── ─── Continuation of front page (51) Int.Cl. ⁷ Identification code FI theme code (reference) G09G 3/20 680 G09G 3/20 680H 3/28 H04N 5/66 101A H04N 5/66 101 G09G 3/28 J E (72) Inventor Hironobu Abe 6-35 Kita-Shinagawa, Shinagawa-ku, Tokyo F-term (reference) within Sony Corporation 5C040 FA01 GB03 GB14 GC01 GC11 GF11 GF16 GG02 5C058 AA11 AB01 BA25 5C080 AA05 BB05 CC03 DD07 EE28 FF12 HH05 JJ02 JJ04 JJ06

Claims (24)

[Claims] 1. A first substrate and a second substrate which are arranged to face each other, and a plurality of linear barrier ribs provided to partition a discharge space between the first substrate and the second substrate. A plurality of sustain electrodes provided on the first substrate; a plurality of address electrodes provided on the second substrate so as to extend in a direction orthogonal to the sustain electrodes; A plasma display panel comprising: a plurality of light-emission unit regions, which are provided so as to include a phosphor in an intersecting region of an electrode and an address electrode and are arranged so as to be displaced by a predetermined number. 2. The displacement is generated in the light emitting unit region by arranging the plurality of barrier ribs so as to be displaced by a predetermined length, and the light emitting unit region is displaced.
The plasma display panel described. 3. The plasma display panel according to claim 2, wherein the barrier ribs are arranged so as to be displaced by a half of an interval between the barrier ribs adjacent to each other at a predetermined length. 4. The plasma display panel according to claim 2, wherein each of the barrier ribs is formed in a linear shape divided into predetermined lengths. 5. The plasma display panel according to claim 2, wherein the address electrodes are linearly formed. 6. The address electrode is formed in a non-linear shape according to the positional deviation so that the phosphors belong to the light emitting unit regions of the same type as the light emitting colors. The plasma display panel described. 7. The light emitting unit regions having different emission colors of the phosphor are adjacent to each other.
The plasma display panel described. 8. The plasma display panel according to claim 1, wherein the light emitting unit region has a substantially rectangular shape. 9. A first substrate and a second substrate which are arranged to face each other, and a plurality of linear barrier ribs provided to partition a discharge space between the first substrate and the second substrate. A plasma display panel display method comprising: a plurality of sustain electrodes provided on the first substrate;
A plurality of address electrodes are provided on the substrate so as to extend in a direction orthogonal to the sustain electrodes, and a plurality of address electrodes are arranged so that a predetermined number of misalignments occur in the intersection region of the sustain electrodes and the address electrodes. A method of displaying a plasma display panel, comprising arranging light emitting unit areas, and controlling light emission of the light emitting unit areas based on an input signal. 10. The display method of the plasma display panel according to claim 9, wherein one pixel is formed by combining the plurality of light emitting unit regions. 11. The display method of the plasma display panel according to claim 10, wherein the pixels are configured to include the light emitting unit regions arranged in different columns. 12. The display method of the plasma display panel according to claim 11, wherein the pixels are formed in a triangular shape. 13. The display method of the plasma display panel according to claim 11, wherein the pixels are arranged so as to have shapes opposite to those of the adjacent pixels. 14. The display method of a plasma display panel according to claim 10, wherein the pixel is formed in a rectangular shape. 15. The display method of the plasma display panel as claimed in claim 10, wherein the pixel is arranged so as to be displaced relative to an adjacent pixel by a half of its width. 16. A first substrate and a second substrate arranged to face each other.
Substrate, a plurality of linear barrier ribs provided to partition a discharge space between the first substrate and the second substrate, and a plurality of sustain electrodes provided on the first substrate. A plurality of address electrodes provided on the second substrate so as to extend in a direction orthogonal to the sustain electrodes, and provided at intersection regions of the sustain electrodes and the address electrodes, and at a predetermined number. Is electrically connected to a plasma display panel having a plurality of light emitting unit areas arranged so as to cause positional deviation, and generates a drive signal from an input signal, and emits the light based on the drive signal. A driving circuit of a plasma display panel, which is configured to control light emission of each unit area. 17. A pixel is configured by combining the light emitting unit regions, and light emission control of each light emitting unit region is performed according to the shape and arrangement of the pixels. 16. A plasma display panel drive circuit according to item 16. 18. A signal array changing means for generating the driving signal by rearranging input signals corresponding to each of the light emitting unit areas according to a shape and an array of the pixels. The drive circuit of the plasma display panel according to claim 17. 19. The driving circuit of the plasma display panel according to claim 18, further comprising a signal storage unit for storing, for rearrangement, input signals corresponding to each of the light emitting unit regions. 20. The driving signal is input to the address electrode, and timing control means for shifting the timing of inputting the driving signal to the address electrode according to the shape and arrangement of the pixels is provided. 18. The driving circuit for the plasma display panel according to claim 17, wherein the driving circuit is a plasma display panel. 21. A first substrate and a second substrate which are arranged to face each other.
Substrate, a plurality of linear barrier ribs provided to partition a discharge space between the first substrate and the second substrate, and a plurality of sustain electrodes provided on the first substrate. A plurality of address electrodes provided on the second substrate so as to extend in a direction orthogonal to the sustain electrodes; A method of driving a plasma display panel, comprising: a plurality of unit light emitting regions arranged so that a position shift occurs in the plasma display panel, wherein a driving signal is generated from an input signal, and the light emission is performed based on the driving signal. A method of driving a plasma display panel, comprising controlling light emission of each unit area. 22. The plasma display panel according to claim 21, wherein one pixel is formed by combining the light emitting unit regions, and light emission control of each light emitting unit region is performed according to the shape and arrangement of the pixels. Driving method. 23. The plasma according to claim 22, wherein the driving signals are generated by rearranging the input signals corresponding to each of the light emission unit regions according to the shape and arrangement of the pixels. Driving method of display panel. 24. The driving method of the plasma display panel according to claim 22, wherein the driving signal is input to the address electrode and the input timing is shifted according to the shape and arrangement of the pixels.