JP2003085153A - Control register and processor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To avoid a state where a sub-processor waits for a determination of a host processor while consuming unnecessary electric power. SOLUTION: This control register 203 has a hold request bit (IDL-REQ) 31 and an interrupt request bit (INT-REQ) 37. The hold request bit (IDL-REQ) 31 can be set and reset by the host processor 100, and is set when requiring stoppage of operation of the sub-processor 200. The interrupt request bit (INT-REQ) 37 can be set and reset by the sub-processor 200, and is set when requiring interrupt to the host processor 100 from the sub-processor 200. Here, when setting the interrupt request bit (INT-REQ) 37, the hold request bit (IDL-REQ) 31 is also set by the sub-processor 200.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a technique for setting availability of a sub processor in a system including a host processor and a sub processor.

[0002]

2. Description of the Related Art There is a system in which a sub processor is also used as an integrated circuit for performing a specific process to assist a host processor. Conventionally, the control of the operation of the sub processor has been triggered by an interrupt request from the sub processor to the host processor or by the host processor polling the internal state of the sub processor.

[0003]

It takes time from when the sub processor issues an interrupt request to the host processor until the host processor acknowledges the interrupt. Also, when the host processor polls the internal state of the sub processor, it takes time for the inside of the sub processor to grasp whether or not the sub processor is in a state in which it can be stopped. During these times, the sub processor consumes unnecessary power.

A system whose system processing performance is desired to be high,
In a battery-driven system such as a portable information terminal, such unnecessary power consumption becomes a very serious problem.

The present invention has been made in view of the above circumstances, and an object thereof is to avoid a situation in which a sub-processor consumes unnecessary electric power and waits for a judgment of a host processor.

[0006]

[Means for Solving the Problems] Claim 1 of the present invention
The control register is provided with a hold request unit and an interrupt request unit. The hold request unit can be set / reset by the host processor and is set when the stop of the operation of the sub processor is requested. The interrupt request unit can be set / reset by the sub processor and is set when the sub processor requests an interrupt from the host processor. When the interrupt request unit is set, the hold request unit is also set by the sub processor.

According to claim 2 of the present invention,
The control register according to claim 1, wherein an approval for a request to stop the operation of the sub-processor is indicated, and the hold approval is set / reset by the sub-processor in correspondence with the set / reset of the hold request unit. Further comprises a unit. When the host processor requests restart of the operation of the sub processor, the hold request unit is reset by the host processor.

According to claim 3 of the present invention,
The control register according to claim 2, further comprising an interrupt acknowledge unit that can be set / reset by the host processor and that indicates an acknowledge for an interrupt from the sub-processor. Then, the interrupt approval unit is set upon the elapse of a predetermined period after the hold approval unit is set, and the interrupt request unit is reset corresponding to the setting of the interrupt approval unit.

According to claim 4 of the present invention,
The control register according to claim 3, wherein after the interrupt request unit is reset, the hold request unit is reset by the host processor.

According to claim 5 of the present invention,
3. The control register according to claim 1, further comprising a busy state unit set when the interface ports of the sub processor other than the interface ports of the sub processor and the host processor are in a busy state. When both the flag set when the interface port is used in the operation of the next cycle of the sub-processor and the busy state unit are set, the hold request unit is also set by the sub-processor. To be done.

According to claim 6 of the present invention,
The control register according to claim 5, wherein when either the flag or the busy state unit is reset,
The hold request unit can be reset by the sub processor.

According to claim 7 of the present invention,
The control register according to claim 5, wherein when both the flag and the busy state unit are set, the interrupt request unit is set, and the flag and the busy state unit are reset. In some cases, the interrupt request unit is not reset.

According to claim 8 of the present invention,
The control register according to claim 7, further comprising an interrupt acknowledge unit that can be set / reset by the host processor and that indicates an acknowledge for an interrupt from the sub-processor. Then, the interrupt request unit is reset corresponding to the set of interrupt approval units.

According to claim 9 of the present invention,
9. The control register according to claim 8, wherein the hold request unit is reset by the host processor after the interrupt request unit is reset.

According to a tenth aspect of the present invention, there is provided a control register according to any one of the first to fourth aspects, which is set when a reset of the sub-processor is requested. A request unit is further provided. When the reset request unit is set, the hold request unit is also set by the sub processor.

The invention according to claim 11 is a processor which functions as a sub-processor for the host processor, wherein the control register according to any one of claims 1 to 10 is provided. A sub-control register accessible from the host processor and a dedicated path for matching the stored contents of the control register and the sub-control register with each other are provided.

A twelfth aspect of the present invention is a processor which functions as a sub-processor to a host processor, and suspends its own operation when the host processor requests a reset for itself. .

According to a thirteenth aspect of the present invention, in the processor according to the twelfth aspect, the operation of the host processor and the sub-processor is stopped even when reset is requested to both the host processor and the sub-processor. .

[0019]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiment 1. 1 is a block diagram illustrating the configuration of a system according to a first embodiment of the present invention. The host processor 100 and the sub processor 200 are connected to each other via the external bus 6.

The sub-processor 200 has an internal bus 202,
The interface port 205 and the control register 203 are provided. The internal bus 202 is the interface port 20
5, the internal bus 202 connects the interface port 205 and the control register 203. Therefore, the control register 203 has the internal bus 20
2 from the inside of the sub processor 200, and further from the host processor 100 via the external bus 6 and the interface port 205.

The sub-processor 200 further includes an interface port 206 connected to the internal bus 202. The interface port 205 has a function of an interface port with the host processor 100, for example, and the interface 206 does not have a function of an interface with the host processor 100.

As an example of the configuration of the control register 203, a case where it has nine bits as a unit for presenting information is illustrated. That is, in the control register 203, the reset request bit (RST-REQ) 30 and the hold request bit (IDL-RE) are arranged in order from the lowest order.
Q) 31, interrupt acknowledge bit (INT-ACK) 3
2, general-purpose acknowledge bit (GEN-ACK) 33, processor busy bit (BUSY1) 34, interface port busy bit (BUSY2) 35, hold acknowledge bit (HLD-ACK) 36, interrupt request bit (I
NT-REQ) 37, and the highest general-purpose request bit (GEN-REQ) 38 are provided.

Reset request bit (RST-REQ) 3
0, hold request bit (IDL-REQ) 31, interrupt acknowledge bit (INT-ACK) 32, and general-purpose acknowledge bit (GEN-ACK) 33 can all be set / reset by the host processor 100. Processor busy bit (BUSY1) 34, hold acknowledge bit (HLD-ACK) 36, interrupt request bit (INT-REQ) 37, general-purpose request bit (GEN-REQ)
38 can be set in the sub processor 200. Interface port busy bit (BUSY2) 35
Can be set from the interface port 206.

When a reset of the sub processor 200 is requested, a reset request bit (RST-REQ) 30
Is set. Further, when it is requested to stop the operation of the sub processor 200, the hold request bit (IDL-
REQ) 31 is set. As will be described later, the bit 31 is also set in the sub processor 200.

Interrupt acknowledge bit (INT-ACK)
32 indicates that the sub processor 200 is the host processor 10
The interrupt request issued to the host processor 0
Set when 00 has approved. The general-purpose acknowledge bit (GEN-ACK) 33 is set when the host processor 100 acknowledges a request (excluding an interrupt request: hereinafter referred to as “general-purpose request”) made by the sub-processor 200 to the host processor 100. To be done. The processor busy bit (BUSY1) 34 is the sub processor 2
When 00 is busy, the interface port busy bit (BUSY2) 35 is set when the interface port 206 is busy. The hold acknowledge bit (HLD-ACK) 36 is
It is set when the subprocessor 200 approves the request to stop the operation of the subprocessor 200. The interrupt request bit (INT-REQ) 37 and the general-purpose request bit (GEN-REQ) 38 are both sub-processor 2
00 is set when making an interrupt request and a general-purpose request, respectively.

FIG. 2 is a diagram showing the transition of the status of each bit 30 to 38 of the control register 203 when the operation of the sub processor 200 is stopped and restarted. However, in order to avoid complication of the drawing, the reference numerals 30 to 38 are omitted, and the names of each bit are RST-REQ, IDL-REQ, INT-ACK, GEN-ACK, BUSY1, B.
It is shown using USY2, HLD-ACK, INT-REQ, and GEN-REQ. When each name is shaded, the bit corresponding to the name is set, and when not shaded, the bit corresponding to the name is reset. Indicates that. In the following description, it is assumed that the host processor 100 does not request the sub processor 200 to stop its operation unless otherwise specified. Further, in the present invention, even in the case of “stopping the operation” of the sub processor 200, the operation of setting / resetting to the control register 203 and reading the content thereof is performed.

FIG. 2A shows the host processor 100,
The sub-processor 200 is operating together,
All bits are reset.

FIG. 2B shows a state when an interrupt request is issued from the sub processor 200 to the host processor 100. In this case, the hold request bit (IDL-REQ) as well as the interrupt request bit (INT-REQ) is set by the sub processor 200. That is, the sub-processor 200 requests the hold request bit (ID
L-REQ) is also set.

FIG. 2 (c) shows a state corresponding to the state of FIG. 2 (b), which is changed by the transition of the next operation clock. In response to the hold request bit (IDL-REQ) being set in the state shown in FIG. 2B, the hold acknowledge bit (HLD-AC)
K) is set by the sub-processor 200. After that, the sub processor 200 stops the operation according to the internal instruction and reduces the power consumption. Then, as described below, the suspension of the operation of the sub processor 200 continues until the processing for restarting the operation is performed again from the host processor 100.

Through the above processing, the host processor 10
The operation of the sub processor 200 can be stopped by the sub processor 200 itself without waiting for the interrupt request polling by 0. This brings about an effect of saving the power of the entire system while suppressing the performance deterioration of the entire system including both the host processor 100 and the sub processor 200.

FIG. 2D shows a state when the host processor 100 requests the restart of the operation of the sub processor 200. In this case, the interrupt acknowledge bit (INT-ACK) is set by the host processor 100.

FIG. 2 (e) shows a state corresponding to the state of FIG. 2 (d), which is changed by the transition of the next operation clock. In response to the setting of the interrupt acknowledge bit (INT-ACK) in the state shown in FIG. 2D, the interrupt request bit (INT-RE)
Q) is reset.

FIG. 2 (f) shows a changed state triggered by the transition of the operation clock after the state of FIG. 2 (e). The interrupt acknowledge bit (INT-ACK) and the hold request bit (IDL-REQ) are reset by the host processor 100. In response to the hold request bit (IDL-REQ) being reset,
The hold acknowledge bit (HLD-ACK) is reset by the sub processor 200. As a result, the control register 203 returns to the state shown in FIG.

When the host processor 100 resets the hold request bit (IDL-REQ) 31, the acknowledge bit (HLD-ACK) 36 is reset and the operation of the sub processor 200 is restarted. Moreover, the host processor 100 causes the hold request bit (ID
L-REQ) 31 is reset when the sub processor 2
After the interrupt request bit (INT-REQ) is reset by 00. Therefore, the host processor 10
A process in which 0 requests restart of the operation of the sub processor 200 does not conflict with a request by the sub processor 200 itself to stop the operation of the sub processor 200.

The setting of the interrupt acknowledge bit (INT-ACK) 32 by the host processor 100 is carried out when a predetermined period elapses after the hold acknowledge bit (HLD-ACK) 36 is set by the sub processor 200. Therefore, the host processor 100
Automatically restarts the operation of the sub-processor 200 without polling. The elapse of the predetermined period can be timed based on, for example, the number of pulses of the operation clock.

In the above description, depending on the host processor 100, the hold request bit (IDL-RE
Q) The case where 31 was not set was illustrated. However, in addition to the interrupt request from the sub processor 200, the host processor 100
There are also situations that require the suspension of the operation of. In this case, the host processor 100 sets the hold request bit (IDL-REQ) 31. Therefore, for example, when the set is represented by “1” and the reset is represented by “0”,
The logical sum of the logical value of the interrupt request bit (INT-REQ) 37 and the logical value of the data to be written in the hold request bit (IDL-REQ) 31 by the host processor 100 is the hold request bit (IDL-REQ) 31.
It is desirable to be written in. The function of the logical sum can be provided in the sub processor 200.

Embodiment 2. FIG. 3 is a block diagram illustrating the configuration of the system 300 according to the second embodiment of the present invention. The system 300 includes the host processor 100 and the sub processor 200 shown in the first embodiment. The OR gate 211 that fulfills the function of the logical sum described in the first embodiment is typically the sub processor 20.
It is provided within 0.

However, in the present embodiment, the OR gate 21
1 indicates not only the logical value of the interrupt request bit (INT-REQ) 37 and the logical value of the data to be written into the hold request bit (IDL-REQ) 31 by the host processor 100, but also the entire reset of the system 300. The logical sum of the logical value of the power-on reset (POR) and the logical value of the reset request bit (RST-REQ) 30 is taken. However, here, the logical value "1" / corresponds to assertion / negate of power-on reset (POR), respectively.
Use "0".

In the configuration shown in FIG. 3, when the sub-processor 200 itself requests the suspension of the operation of the sub-processor 200 as described in the first embodiment, and when the entire system 300 is reset, The hold request bit (IDL-REQ) 31 is set even when the host processor 100 requests the suspension of the operation of the sub processor 200 and when the host processor 100 requests the reset of the sub processor 200.

According to this embodiment, the sub processor 2
00 to the host processor 100 as well as the sub processor 20 by the host processor 100.
The operation of the sub processor 200 is also stopped by a chip reset for 0 or a power-on reset (POR) for the entire system 300. That is, sub processor 2
By requesting 00 to be reset, the subsequent processing of the host processor 100 is not required,
The operation of the sub processor 200 can be stopped. Further, similarly to the first embodiment, the operation of the sub processor 200 can be restarted without the polling processing by the host processor 100.

Embodiment 3. FIG. 4 is a block diagram illustrating the configuration of the system according to the third embodiment of the present invention. In this embodiment, in addition to the configuration of the first embodiment, an interface port 205 is characteristically configured.

In this embodiment, the interface port 2
05 includes a sub control register 204. The sub control register 204 is connected to the control register 203 via a dedicated path 207.

The sub control register 204 is the control register 20.
Bits 40-4 corresponding to bits 30-38 of 3
Have eight. The control register 203 can be accessed using the internal bus 202 as in the first embodiment, but cannot be directly accessed from the host processor 100. The sub-control register 204 can be accessed from the host processor 100, but cannot be accessed using the internal bus 202.

The dedicated path 207 has a function of matching the stored contents of the control register 203 and the sub control register 204 with each other. The function is at least the control register 203.
It is exhibited when the stored content in at least one of the sub-control register 204 and the sub-control register 204 changes. For example, the dedicated path 207 matches the stored contents of the control register 203 and the sub-control register 204 with each other at every transition of the operation clock.

The internal bus 202 is used not only for accessing the control register 203 but also for executing internal instructions, for example. In that case, access from the host processor 100 to the control register 203 using the internal bus 202 needs to wait. However, the host processor 100
When accessing the sub control register 204 whose stored content matches that of the control register 203, the internal bus 202
No such wait is needed since no. Further, the sub control register 20 changed by the host processor 100
4 is copied to the control register 203, and the stored content of the control register 203 changed by the sub processor 200 is copied to the sub control register 204. Therefore, the host processor 100,
The sub processor 200 can perform the same operation as that of the first embodiment.

As described above, the sub processor 200
The contents stored in the control register 203 can be indirectly changed from the host processor 100, regardless of the usage status of the internal bus 202 of FIG. Therefore, it is possible to avoid spending unnecessary free time for the host processor 100 to grasp the operation status of the sub processor 200 or to request the host processor 100 to stop the operation of the sub processor 200.

In contrast to the second embodiment, the sub control register 2
It is obvious and easy that the second embodiment can be modified by adopting No. 04.

Fourth Embodiment FIG. 5 is a diagram showing the transition of the status of each bit of the control register 203 when the operation of the sub processor 200 is stopped and restarted in the fourth embodiment of the present invention. However, unless otherwise noted, it is assumed that the host processor 100 does not request the sub processor 200 to stop operating.

In this embodiment, the operation when the interface port 206 is in the busy state in the configuration shown in FIG. 1 will be described. FIG. 5A shows a state in which the interface port busy bit (BUSY2) is set.

The sub-processor 200 uses a known technique to generate a next cycle output flag which is set when the interface port 206 is predicted to be used in the operation of the next cycle of itself. In the present embodiment, the next cycle output flag and the interface port busy bit (BUSY
If both of 2) are set, the hold request bit (IDL-REQ) is set by the sub-processor 200. FIG. 5B shows a state where the hold request bit (IDL-REQ) is set by the sub processor 200 generating the next cycle output flag in the state shown in FIG. 5A.

Corresponding to the hold request bit (IDL-REQ) being set, as in the first embodiment,
The hold acknowledge bit (HLD-ACK) is set by the sub processor 200. Then, the sub processor 200 stops the operation according to the internal instruction and reduces the power consumption.

FIG. 5D shows a case where the busy state of the interface port 206 is canceled after the state of FIG. 5C, and the interface port busy bit (BU
SY2) has been reset. Host processor 100
Since it is premised that the stop of the operation of the sub processor 200 is not requested, the hold request bit (IDL-REQ) can be reset by the sub processor 200.

FIG. 5 (e) shows a state corresponding to the state of FIG. 5 (d), which is changed by the transition of the next operation clock. Hold request bit (IDL-RE
In response to the reset of Q), the hold acknowledge bit (HLD-ACK) is reset and the operation of the sub processor 200 is restarted. In this way, the sub-processor 200 itself can restart the operation independently of the host processor 100.

As described in the first embodiment,
There is also a situation where the host processor 100 requests the suspension of the operation of the sub-processor 200 separately from whether or not the interface port 206 is in the busy state. In this case, the host processor 100 sets the hold request bit (IDL-REQ). FIG. 6 is a block diagram schematically showing an aspect of executing the setting of the hold request bit (IDL-REQ) 31 from the host processor 100 and the setting based on the busy state of the interface port 206.

The sub processor 200 receives the next cycle output flag FLG and the interface port busy bit (BUSY).
2) It has a function of taking a logical product with the stored contents of 35, and this function is expressed as an AND gate 208 in FIG. Further, the sub processor 200 determines that both the output flag FLG of the next cycle and the stored contents of the interface port busy bit (BUSY2) 35 are set (that is, the output of the AND gate 208 is a logical value "1").
In this case), the host processor 100 also has a function of permitting the hold request bit (IDL-REQ) 31. The function is OR gate 2 in FIG.
It is expressed as 09. However, in FIG. 6 and FIG. 7 described later, “1” and “0” are adopted as the logical values corresponding to the set / reset, respectively.

In FIG. 6, the storage content of the interface port busy bit (BUSY2) 35 is directly input to the AND gate 208, and the output of the OR gate 209 directly gives a value to the hold request bit (IDL-REQ) 31. As shown. But of course, the internal bus 20
It is possible to adopt a configuration in which the stored content is input to the AND gate 208 via 2 and the value is input to the hold request bit (IDL-REQ) 31 via the internal bus 202.

In the present embodiment, the handling of the busy state of the single interface port 206 has been described, but it is obvious and easy to apply even when there are a plurality of interface ports other than the interface port 205. In that case, for example, a plurality of interface port busy bits (BUSY2) 35 may be provided.

It is obvious and easy that the present embodiment can be modified by adopting the sub-control register 204 shown in the third embodiment.

Embodiment 5. As a modification of the fourth embodiment, a case will be described in which the operation of the sub-processor 200 is not restarted without permission from the host processor 100.

FIG. 7 is a block diagram illustrating the configuration of a system according to the fifth embodiment of the present invention. The sub-processor 200 has a function of taking a logical product of the next cycle output flag FLG represented by the AND gate 208 and the stored content of the interface port busy bit (BUSY2) 35. When the logical value output from the AND gate 208 is “1”, the interrupt request bit (INT-RE
Q) 37 is set. However, AND gate 208
Does not have the function of resetting the interrupt request bit (INT-REQ) 37 even if the output logical value is "0".

Further, the sub-processor 200 receives the hold request bit when the output of the AND gate 208 is the logical value "1", when the interrupt request bit (INT-REQ) 37 is set, and when the host processor 100 also performs the hold request bit. It also has the function of setting (IDL-REQ) 31. Further, the output of the AND gate 208 has a logical value "0", and the interrupt request bit (INT-RE
Q) If 37 is reset and the host processor 100 does not request the stop of the operation of the sub processor 200, the hold request bit (IDL-RE
Q) 31 is reset. The function is represented as an OR gate 210 in FIG.

In FIG. 8, the input to the AND gate 208 and the output from the OR gate 209 are directly connected to the control register 20.
3 is shown to take place between the two. But of course
A configuration for inputting and outputting via the internal bus 202 can be adopted.

FIG. 8 is a diagram showing the transition of the status of each bit of the control register 203 when the operation of the sub-processor 200 is stopped and restarted in the present embodiment.
However, unless otherwise noted, it is assumed that the host processor 100 does not request the sub processor 200 to stop operating.

FIG. 8A shows the interface port 206.
Indicates that the interface port is busy and the interface port busy bit (BUSY2) is set. Further, when the sub-processor 200 generates the next cycle output flag, the function expressed by the AND gate 208 causes
As shown in (b), the interrupt request bit (IN
T-REQ) is set. In addition, the function represented by the OR gate 210 causes the hold request bit (IDL-RE
Q) is set.

FIG. 8C shows a state corresponding to the state of FIG. 8B, which is changed by the transition of the next operation clock. Hold request bit (IDL-RE
In response to Q) 31 being set, hold acknowledge bit (HLD-ACK) 36 is set to sub processor 20.
Set by 0. And the sub processor 200
Stops the operation by the internal command.

FIG. 8D shows a case where the busy state of the interface port 206 is canceled after the state of FIG. 8C, and the interface port busy bit (BU
SY2) has been reset. As described above, the function expressed by the AND gate 208 does not fulfill the function of resetting the interrupt request bit (INT-REQ) 37. Therefore, the interrupt request bit (INT-REQ) remains set, and the host processor 10
From 0, it is assumed that the operation stop of the sub processor 200 is not requested, but the hold request bit (IDL-REQ) is still set. Therefore, hold acknowledge bit (HLD-AC
K) is still set.

As described above, in the present embodiment, even if the busy state of the interface port 206 is resolved,
The sub-processor 200 alone cannot restart its own operation. In other words, the operation of the sub processor 200 can be restarted based on a command from the host processor 100. Hereinafter, the restart procedure is the same as that of the first embodiment except the restart timing.

FIG. 8E shows the state when the host processor 100 requests the restart of the operation of the sub processor 200. Interrupt acknowledge bit (INT-ACK)
Are set by the host processor 100. In the first embodiment, the interrupt acknowledge bit (INT-AC
K) is set at the sub processor 200
After the hold acknowledge bit (HLD-ACK) was set by, the lapse of a predetermined period was the trigger. However, the interface port busy bit (BUSY2) may remain set even after the lapse of the predetermined period.
Then, for example, the host processor 100 sets the interrupt acknowledge bit (INT-ACK) after confirming that the interface port busy bit (BUSY2) is reset.

FIG. 8 (f) shows a state corresponding to the state of FIG. 8 (e), which is changed by the transition of the next operation clock. Interrupt acknowledge bit (INT-
The interrupt request bit (INT-REQ) is reset in response to ACK) being set.

FIG. 8 (g) shows a changed state triggered by the transition of the operation clock after the state of FIG. 8 (f). The interrupt acknowledge bit (INT-ACK) and the hold request bit (IDL-REQ) are reset by the host processor 100.

FIG. 8 (h) shows a state corresponding to the state of FIG. 8 (g), which is changed by the transition of the next operation clock. Hold request bit (IDL-RE
In response to the reset of Q), the hold acknowledge bit (HLD-ACK) is reset by the sub processor 200. Then, the operation of the sub processor 200 is restarted.

In the above operation, as in the first embodiment,
The process in which the host processor 100 requests restart of the operation of the sub processor 200 does not conflict with the request by the sub processor 200 itself to stop the operation of the sub processor 200.

It is obvious and easy that this embodiment can be modified by using the sub-control register 204 shown in the third embodiment.

[0074]

According to the control register of the first aspect of the present invention, when the sub processor requests an interrupt from the host processor, a hold request unit is also required to request the stop of its own operation. set. This enables the sub-processor itself to stop the operation without waiting for the interrupt request polling by the host processor. Therefore, while suppressing the performance degradation as a whole including both the host processor and the sub-processor, the power consumption as a whole is saved.

According to the control register of the second aspect of the present invention, when the host processor resets the hold request unit, the hold approval unit is reset and the operation of the sub processor is restarted.

According to the control register of the third aspect of the present invention, the host processor resets the interrupt request of the sub-processor without polling, for example, based on the pulse number of the clock signal on which the operation depends. Let

According to the control register of the fourth aspect of the present invention, the host processor automatically restarts the operation of the sub-processor without polling. Moreover, it does not conflict with the request to stop the operation of the sub processor itself.

According to the control register of the fifth aspect of the present invention, it is foreseen that the interface port is busy in the sub processor and the interface port is used in the operation of the next cycle of the sub processor. If so, the hold request unit is set to request the stop of its own operation. This allows the sub-processor itself to stop its operation independently of the host processor. Therefore, while suppressing the performance degradation as a whole including both the host processor and the sub-processor, the power consumption as a whole is saved.

According to the sixth aspect of the present invention, the control register enables the sub-processor itself to restart the operation independently of the host processor.

According to the control register of the seventh aspect of the present invention, the interface port becomes busy, and after the sub processor sets the hold request unit to request the stop of its own operation, the interface Even if the port is released from the busy state, the interrupt request unit remains set. Therefore, the operation of the sub processor can be restarted based on the command from the host processor.

According to the control register of the eighth aspect of the present invention, the interrupt request of the sub processor can be reset, and the operation of the sub processor can be restarted based on the instruction of the host processor.

According to the control register of the ninth aspect of the present invention, the operation of the sub processor is restarted based on the command of the host processor without colliding with the request for stopping the operation of the sub processor by the sub processor itself. Can be made.

According to the tenth aspect of the present invention, the processor according to the tenth aspect is capable of stopping the operation of the sub-processor without requiring the subsequent processing of the host processor by requesting a reset to the processor. You can

According to the processor of claim 11 of the present invention, the control register can be indirectly accessed from the host processor via the sub control register without using the internal bus of the sub processor. . Therefore, it is possible to avoid spending unnecessary free time for the host processor to grasp the operation status of the sub processor and to request the sub processor to stop the operation from the host processor.

Of the present invention, claim 12 and claim 13
According to this processor, by requesting the sub-processor to be reset, the operation of the sub-processor can be stopped without the need for subsequent processing by the host processor.

[Brief description of drawings]

FIG. 1 is a block diagram illustrating a configuration of a first embodiment of the present invention.

FIG. 2 is a diagram showing a transition of an operation according to the first embodiment of the present invention.

FIG. 3 is a block diagram illustrating a configuration of a second embodiment of the present invention.

FIG. 4 is a block diagram illustrating a configuration of a third embodiment of the present invention.

FIG. 5 is a diagram showing a transition of an operation according to the fourth embodiment of the present invention.

FIG. 6 is a block diagram illustrating a configuration of a fourth embodiment of the present invention.

FIG. 7 is a block diagram illustrating a configuration of a fifth embodiment of the present invention.

FIG. 8 is a diagram showing a transition of an operation according to the fifth embodiment of the present invention.

[Explanation of symbols]

30 reset request bit (RST-REQ), 31 hold request bit (IDL-REQ), 32 interrupt acknowledge bit (INT-ACK), 36 hold acknowledge bit (HLD-ACK), 37 interrupt request bit (INT-REQ), 100 host processor, 2
00 sub-processor, 203 control register, 204
Sub control register, 205, 206 interface port, 207 dedicated path.

   ─────────────────────────────────────────────────── ─── Continued front page    (72) Inventor Junko Ohara             2-3 2-3 Marunouchi, Chiyoda-ku, Tokyo             Inside Ryo Electric Co., Ltd. F-term (reference) 5B013 DD03 EE01                 5B045 FF03 GG06 HH01                 5B054 AA11 BB06 CC06                 5B098 AA10 BB01 BB05

Claims (13)

[Claims] 1. A hold request unit that can be set / reset by a host processor and is set when a stop of operation of a sub processor is requested; and a set / reset can be performed by the sub processor, An interrupt request unit set when an interrupt is requested from the sub processor to the host processor, and when the interrupt request unit is set, the hold request unit is also set by the sub processor register. 2. A hold approval unit, which indicates approval for a request to stop the operation of the sub-processor, and further comprises a hold approval unit set / reset by the sub-processor in correspondence with the set / reset of the hold request unit, respectively. The control register according to claim 1, wherein the hold request unit is reset by the host processor when the host processor requests restart of the operation of the sub processor. 3. Set / set by said host processor
The interrupt approval unit is resettable, and further comprises an interrupt approval unit indicating approval of an interrupt from the sub-processor, and the interrupt approval unit is set when a predetermined period elapses after the hold approval unit is set, The control register according to claim 2, wherein the interrupt request unit is reset in response to a set of interrupt acknowledge units. 4. The control register according to claim 3, wherein the hold request unit is reset by the host processor after the interrupt request unit is reset. 5. A busy state unit that is set when the interface ports of the sub processor other than the interface ports of the sub processor and the host processor are in a busy state, further comprising: 3. The control according to claim 1, wherein when both the flag set when the interface port is used and the busy state unit are set, the hold request unit is also set by the sub processor. register. 6. The control register according to claim 5, wherein when either the flag or the busy state unit is reset, the hold request unit can be reset by the sub processor. 7. The interrupt request unit is set when both the flag and the busy state unit are set, and the interrupt request is caused by the reset of the flag and the busy state unit. The control register of claim 5, wherein the unit is not reset. 8. Set / set by said host processor
8. The control according to claim 7, further comprising an interrupt acknowledge unit that can be reset and that indicates an acknowledge for an interrupt from the sub-processor, and the interrupt request unit is reset corresponding to the set of interrupt acknowledge units. register. 9. The control register according to claim 8, wherein the hold request unit is reset by the host processor after the interrupt request unit is reset. 10. A reset request unit that is set when requesting reset of the sub-processor is provided, and when the reset request unit is set, the hold request unit is also set by the sub-processor. The control register according to any one of claims 1 to 4. 11. The control register according to claim 1, a sub-control register accessible from the host processor, and contents stored in the control register and the sub-control register mutually. A dedicated path for matching, which functions as the sub-processor with respect to the host processor. 12. A processor that functions as a sub-processor for a host processor and stops its own operation when the host processor requests a reset for itself. 13. The processor according to claim 12, which suspends its operation even when a reset is requested to both the host processor and the sub-processor.