JP2003078913A - Mpeg 2 ts multiplexer - Google Patents

Abstract

PROBLEM TO BE SOLVED: To attain more detailed adjustment for delays caused by an MPEG ENCODER and a modulator with a simple circuitry even when coded delays differ from each other. SOLUTION: A demultiplexer section 5 receives a TS signal 1 and outputs demultiplexed outputs 47 to 49. A delay buffer 6 for a PID No.1 delays the demultiplexed output 47 by using a delay control signal 45 to provide an output of a delay buffer output 41. A delay buffer 7 for a PID No.2 delays the demultiplexed output 48 by using the delay control signal 45 to provide an output of a delay buffer output 42. A delay buffer 8 for a PID No.M delays the demultiplexed output 49 by using the delay control signal 45 to provide an output of a delay buffer output 43. A multiplexer section 50 receives delay buffer outputs 41 to 43 and delay buffer outputs 41n to 43n and provides an output of the result as a multiplexer output 44.

Description

Detailed Description of the Invention

[0001]

TECHNICAL FIELD The present invention relates to MPEG2 (Mov
ing Picture Experts Group
2) TS (Transport Stream) multiplexer, particularly MPEG2 T having a delay compensation function
S-multiplexer.

[0002]

2. Description of the Related Art Recently, CS digital television broadcasting, B
Digitalization of broadcasting is progressing due to S digital television broadcasting and terrestrial digital television broadcasting.

FIG. 8 is a system diagram showing an example of digital broadcasting using a conventional MPEG2 TS multiplexer.

Generally, in digital broadcasting, a video / audio signal 3
1. Video / audio signal 32 and video / audio signal 33 are MPEG
ENCODER20, MPEG ENCODER21,
Each of them is compression-encoded by the MPEG ENCODER 22, and these compression-encoded output signals 34, 35, 36 are M
It is multiplexed by the PEG2 TS multiplexer 23. MPEG
The multiplexed signal 37 output from the 2 TS multiplexer 23 is modulated by the modulator 24 and transmitted as a modulated signal 38.

According to the video encoding method in MPEG ENCODER, MPEG2 480i, 480p, 72
In addition to the 0p and 1080i formats, MPEG1 and MPEG4 are also used.

It should be noted that the MPEG2 TS multiplexer is an MP
It is also called an EG2 TS MUX (Multiplexer).

These MPEG ENCODER 20,
In 21 and 22, processing time for compression encoding occurs, and therefore encoding delay occurs. The coding delay is generally about 0.
It takes about 1 to 1 second, but it depends on the video coding method or MPEG.
It depends on the model of ENCODER.

Therefore, the MPEG ENCODER 20,
When the modulated signal 38 is transmitted using 21, 22, even if the same video / audio signals 31, 32, 33 are input, the transmission delay differs due to the different encoding delay depending on the MPEG ENCODER used, and thus the receiver. A phenomenon occurs that the timing of the video / audio signal demodulated by (not shown) is different.

On the other hand, the modulator 24 is capable of hierarchical transmission and the like, and can use different transmission parameters for each layer. Particularly, in the ISDB-T system, which is a terrestrial digital television system, transmission can be performed in three layers of A, B, and C at the maximum, and different parameter settings can be set for each layer. 1 of those parameter settings
As one of them, there is a setting of the length of time interleave, and a difference in the delay amount between layers occurs at a maximum of about 0.5 seconds depending on the setting.

That is, the timing at which the demodulator (not shown) of the receiver outputs the video / audio signals 31, 32, and 33 that are simultaneously input to the modulator 24 is about a maximum depending on the layer used for transmission. A phenomenon occurs that the difference is 0.5 seconds.

For these phenomena, the conventional MPEG2
The following measures are taken in the TS multiplexer.

First, regarding the delay generated in the MPEG ENCODER, a method of adjusting the delay time by inserting a delay buffer into the input or output of the MPEG ENCODER is adopted. However, MPEG
If the ENCODER model or manufacturer is different, the adjustment range will be exceeded.

Since the delay time is always adjusted to the maximum delay, the delay amount becomes large.

Furthermore, as an example of a delay compensation technique generated in a modulator, a "transmitter having a delay compensation function" described in Japanese Patent Laid-Open No. 2000-115149 is known, and is described in this publication. There is also a proposal to perform delay compensation of each layer with a modulator when performing hierarchical transmission of a terrestrial digital broadcasting system, but it is necessary to compensate for delay when switching the layer transmission due to an increase in the circuit amount of the modulator. If not, the control of the modulator becomes complicated.

FIG. 9 is a block diagram showing a conventional MPEG2 TS multiplexer.

Referring to FIG. 9, a conventional MPEG2 T
The S multiplexer inputs the TS signal 1 output from MPEG ENCODER or the like into the delay buffer 4 included in the TS signal circuit 25, and outputs the delay buffer output 26 output from the delay buffer 4 to the multiplexer 2.

Similarly, the TS signal 1n output from the MPEG ENCODER or the like is input to the delay buffer 4n included in the TS signal circuit 25n, and this delay buffer 4n is input.
And outputs the delay buffer output 26n output from the multiplexer 2 to the multiplexer 2.

The multiplexer 2 outputs the delay buffer outputs 26, 26.
n is multiplexed and output as a multiplexer output 27. The delay control signal 28 output from the delay buffer control unit 3 is output to the delay buffer 4 and the delay buffer 4n to control the delay time.

It is assumed that the delay buffers are provided as many as the input TS signals. For example, MPEG ENC
When there are n TS signals from the ODER and the like, that is, the TS signals 1 to 1n, n delay buffers are provided.

For other TS signals except the TS signal 1n from the TS signal 1 from MPEG ENOCDER, etc.,
The configuration is similar to that of the S signal circuits 25 and 25n.

Next, the operation will be described. MPEG ENC
TS signal 1 from ODER etc. is TSP (Transpo
rt Stream Packet). The TSP from the TS signal 1 is input to the delay buffer 4, delayed by the delay control signal 28 for the time designated by the delay buffer control unit 3, and then delayed by the delay buffer 4.
Is output to the multiplexing unit 2 as the delay buffer output 26. The multiplexer output 27 of the multiplexer 2 becomes the output of the MPEG2 TS multiplexer having the delay compensation function. Similarly, T
The TSP input from the S signal 1n is also input to the delay buffer 4n, delayed by the delay control signal 28 for the time designated by the delay buffer control unit 3, and then the delay buffer 4n.
It is output from n to the multiplexing unit 2.

FIG. 10 is a time chart showing the operation of FIG.

These operations will be described in more detail with reference to FIGS. 9 and 10.

As shown in FIG. 10 (a), the TS signal 1 is TSP1, TSP2, TSP3, TSP4, TSP.
5, it is assumed that the format is TSP6. In that case, the delay buffer output 2 output from the delay buffer 4
As shown in FIG. 10B, 6 is delayed by the delay time D1 (= the delay time of the delay buffer 4 of the TS signal 1).

On the other hand, the TS signal 1n is, as shown in FIG. 10C, TSP0, TSP1, TSP2, TSP.
3, TSP4 and TSP5 are input at timing different from the signal of the TS signal 1. In that case, the delay buffer output 26n output from the delay buffer 4n
Is output with a delay of DN, as shown in FIG.

Through the above operation, TS1TSP1 and TSNTSP1 input from the TS signal 1 are output from the respective delay buffers at the same timing.
By multiplexing these TSPs in the multiplexer 2, a delay-compensated multiplexer output 27 is obtained as shown in FIG.

[0027]

DISCLOSURE OF THE INVENTION The conventional MPE described above
The G2 TS multiplexer has a drawback in that the encoding delay differs depending on the MPEG ENCODER used even if the same video / audio signal is input, and therefore the transmission timing is different and the timing of the video / audio signal in the receiver is also different.

The modulator is capable of hierarchical transmission and the like, and different transmission parameters can be set for each layer. One of the parameter settings is the length of time interleave. Since the difference in the delay amount of the above occurs due to these settings, there is a drawback that the timing output from the demodulator of the receiver with respect to the signals input to the modulator at the same time depends on the layer used for transmission. There is.

Furthermore, when a delay buffer is inserted into the input or output of the MPEG ENCODER to adjust the delay time, the delay time is always adjusted to the maximum delay when the model and manufacturer of the MPEG ENCODER are different. Has a drawback that the modulator becomes large and the circuit amount of the modulator increases, and control of the modulator becomes complicated depending on the necessity of delay compensation when switching the hierarchical transmission.

The object of the present invention is to achieve timing synchronization of video and audio at the receiver even if the coding delay is different, and the timing output from the demodulator of the receiver does not depend on the layer used for transmission. MPEG EN with a simple circuit configuration
MPEG2 TS that comprehensively manages the delay generated in the CODER and the modulator and enables finer delay adjustment
It is to provide a multiplex device.

[0031]

[MEANS FOR SOLVING THE PROBLEMS] MPEG2 T of the present invention
The S multiplexer is an MPEG2 (Mo
Ving Picture Experts Grou
p2) A TS (Transport Stream) multiplexer, which inputs a TS signal which is encoded stream data, and outputs m (m is an integer of 2 or more) delay buffer outputs by controlling delay control signals. n (n
Is an integer of 2 or more); a delay buffer control unit for outputting the delay control signal; a total of m × n delay buffer outputs are input, and these are multiplexed and output as a multiplexer output. And a multiplexing unit for
A signal circuit receives the TS signal and outputs m demultiplexed outputs; each of the m demultiplexed outputs is delayed by the delay control signal, and the m delay buffer outputs are output. M output delay buffers for PID, and
It is characterized by having.

An MPEG2 TS multiplexer for digital broadcasting, in which a first TS signal which is encoded stream data is input, a first separation output, a second separation output,
A first demultiplexing unit that outputs a third demultiplexed output; a first demultiplexing unit that delays the first demultiplexed output by a delay control signal and outputs a first delay buffer output. A first delay buffer; a second P that delays the second separated output by the delay control signal and outputs a second delay buffer output.
ID No. A second delay buffer; a third PID No. that delays the third separated output by the delay control signal, and outputs a third delay buffer output. M delay buffer;
And a second demultiplexing unit for inputting the second TS signal and outputting a fourth separation output, a fifth separation output, and a sixth separation output; A fourth PID No. that delays the fourth separated output by the delay control signal and outputs the fourth delay buffer output. A first delay buffer; a fifth PIDN which delays the fifth separated output by the delay control signal and outputs a fifth delay buffer output
o. A second delay buffer; a sixth PID No. that delays the sixth separated output by the delay control signal, and outputs a sixth delay buffer output. A second TS signal circuit having an M delay buffer; a delay buffer control section for outputting the delay control signal; the first to third delay buffer outputs and the fourth to sixth delays; And a multiplexer for inputting the buffer outputs and multiplexing them for output as a multiplexer output.

An MPEG2 TS multiplexer for digital broadcasting, which receives a TS signal as encoded stream data and outputs L (L is an integer of 2 or more) delay buffer outputs under the control of a delay control signal n (N is an integer of 2 or more) TS signal circuits; a delay buffer control unit that outputs the delay control signal; a total of L × n delay buffer outputs are input, and these are multiplexed to output a multiplexer. And a multiplexer / demultiplexer for outputting the TS signal to the TS signal circuit and outputting L separated outputs; and the delay control for each of the L separated outputs. And L program delay buffers for delaying by a signal and outputting the L delay buffer outputs, respectively.

An MPEG2 TS multiplexer for digital broadcasting, in which a first TS signal which is encoded stream data is input, a first separated output, a second separated output,
A first demultiplexing unit that outputs a third demultiplexed output; a first program 1 delay buffer that delays the first demultiplexed output by a delay control signal and outputs a first delay buffer output; A second delay buffer for program 2, which delays the second separated output by the delay control signal and outputs a second delay buffer output; and delays the third separated output by the delay control signal, A first TS signal circuit having a third program L delay buffer for outputting a delay buffer output of the second program signal; and a second TS signal,
A second demultiplexing unit that outputs a fourth demultiplexed output, a fifth demultiplexed output, and a sixth demultiplexed output; delaying the fourth demultiplexed output by the delay control signal, and providing a fourth delay buffer output A fourth delay buffer for program 1, which outputs; a fifth delay buffer for program 2, which delays the fifth separated output by the delay control signal and outputs a fifth delay buffer output; the sixth delay buffer A second TS signal circuit having a sixth program L delay buffer for delaying the separated output by the delay control signal and outputting a sixth delay buffer output; and a delay for outputting the delay control signal. A buffer control unit; and a multiplexing unit that inputs the first to third delay buffer outputs and the fourth to sixth delay buffer outputs, multiplexes them, and outputs them as a multiplexer output. As .

An MPEG2 TS multiplexer for digital broadcasting, which receives a TS signal which is encoded stream data and outputs k (k is an integer of 2 or more) delay buffer outputs under the control of a delay control signal. (N is an integer of 2 or more) TS signal circuits; a delay buffer control unit that outputs the delay control signal; a total of k × n delay buffer outputs are input, and these are multiplexed to output a multiplexer. A multiplexer / demultiplexer for outputting the TS signal to the TS signal circuit and outputting k separated outputs; and the delay control for each of the k separated outputs. A delay buffer for k layers, which is delayed by a signal and outputs the output of each of the k delay buffers.

An MPEG2 TS multiplexer for digital broadcasting, in which a first TS signal which is encoded stream data is input, a first separation output, a second separation output,
A first demultiplexing section for outputting a third demultiplexed output; a first layer A delay buffer for delaying the first demultiplexed output with a delay control signal and outputting a first delay buffer output; A second layer B delay buffer for delaying a second separated output by the delay control signal and outputting a second delay buffer output; a third separated output delayed by the delay control signal, and a third A first TS signal circuit having a third layer C delay buffer for outputting a delay buffer output; and a second TS signal, and a fourth separation output,
A fifth demultiplexing unit for outputting a fifth demultiplexing output and a sixth demultiplexing output; a fourth layer for delaying the fourth demultiplexing output by the delay control signal and outputting a fourth delay buffer output A delay buffer for A; a fifth layer B delay buffer that delays the fifth separated output by the delay control signal and outputs a fifth delay buffer output; and a delay control for the sixth separated output A second TS signal circuit having a sixth layer C delay buffer that delays by a signal and outputs a sixth delay buffer output; a delay buffer control unit that outputs the delay control signal; The present invention is characterized by comprising a first to third delay buffer outputs and a multiplexer for inputting the fourth to sixth delay buffer outputs and multiplexing them to output as a multiplexer output.

An MPEG2 TS multiplexer for digital broadcasting, in which a first TS signal which is encoded stream data is input, and a first separated output, a second separated output,
A first demultiplexing section that outputs a third demultiplexed output; a second TS signal that is input, a fourth demultiplexed output, a fifth demultiplexed output,
A second demultiplexing unit for outputting a sixth demultiplexed output; a first demultiplexed output and a fourth demultiplexed output,
A layer A multiplexer that outputs a multiplexed output of the layer B; a layer B multiplexer that multiplexes the second demultiplexed output and the fifth demultiplexed output and outputs a second multiplexed output; Layer C multiplexer for multiplexing the demultiplexed output and the sixth demultiplexed output and outputting a third multiplexed output; a delay control signal for delaying the first multiplexed output, and a first delay buffer A delay buffer for layer A that outputs an output; a delay buffer for layer B that delays the second multiplexed output by the delay control signal and outputs a second delay buffer output; the third multiplexed output Is delayed by the delay control signal,
A delay buffer for layer C that outputs the delay buffer output; a delay buffer control unit that outputs the delay control signal; and inputs the first to third delay buffer outputs, multiplexes them, and outputs them as a multiplexer output. A multiplexing unit for:
It is characterized by having.

The above-mentioned MPEG2 TS multiplexer is characterized in that it is applied to a digital broadcast in which a plurality of video / audio signals are compression-encoded by a plurality of MPEG ENCODERs, multiplexed and transmitted.

[0039]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of an MPEG2 TS multiplexer according to the present invention.

The embodiment shown in FIG. 1 is a TS (Transport Stream) which is encoded stream data.
am) The signal 1 is input, the separated output 47, the separated output 48,
The demultiplexing unit 5 which outputs the demultiplexed output 49, and the demultiplexed output 47
Is delayed by the delay control signal 45, and the delay buffer output 41
Output PID No. 1 delay buffer 6 and PID No. 1 which outputs the delay buffer output 42 by delaying the separated output 48 by the delay control signal 45. 2 delay buffer 7,
The PID No. which delays the separated output 49 by the delay control signal 45 and outputs the delay buffer output 43. The TS signal circuit 40 having the M delay buffer 8 and the TS signal 1n are input, and the separation output 47n, the separation output 48n, and the separation output 49 are input.
n for outputting the demultiplexing unit 5n, and the demultiplexing output 47n for delaying the demultiplexing signal 47n by the delay control signal 45 and outputting the delay buffer output 41n. 1 delay buffer 6n and the separated output 48n are delayed by the delay control signal 45 to output the delay buffer output 42n. 2 delay buffer 7n
PID No. which delays the separated output 49n by the delay control signal 45 and outputs the delay buffer output 43n. A TS signal circuit 40n having an M delay buffer 8n, a delay buffer control unit 46 outputting a delay control signal 45, delay buffer outputs 41 to 43, and a delay buffer output 41.
n to 43n are input to multiplex them, and a multiplexing unit 50 which outputs as a multiplexer output 44 is configured.

For details of the MPEG2-TS signal, refer to ISO (International Organization).
localization for Standardizatat
Ion, International Organization for Standardization / IEC (Internat)
Ional Electrotechnical Co
(Mission, International Electrotechnical Commission) 13818-
1 (1994 edition), for example p. 22-p. 23.

Referring to FIG. 1, the MPEG2 TS multiplexer inputs the TS signal 1 from an MPEG ENCODER (not shown) or the like into the demultiplexer 5 of the TS signal circuit 40, and the demultiplexer 5 separates the TS signal 1. Separate output 47, 48, 4
9 for PID No. 1 delay buffer 6, PIDN
o. 2 delay buffer 7, PID No. The delay buffer outputs 41, 42, 43 output to the M delay buffer 8 and further delayed by the delay control signal 45 are multiplexed by the multiplexer 50 and output as the multiplexer output 44.

The operation of the TS signal circuit 40n is TS
Since it is the same as the signal circuit 40, its explanation is omitted.

The delay control signal 45 output from the delay buffer control unit 46 is the PID No. 1 delay buffer 6, PI
DNo. 2 delay buffer 7, PID No. The delay amount is output to the M delay buffer 8 and the delay amount is controlled.

The demultiplexing unit 5, PID No. 1 delay buffer 6, PID No. 2 delay buffer 7, PI
DNo. TS signal circuit 4 having M delay buffer 8
A circuit having the same configuration as that of 0 corresponds to the number of TS signals to be input, TS signal circuits 40 to T corresponding to TS signal 1 to TS signal 1n.
It is provided as an S signal circuit 40n.

Here, "PID (Packet ID)"
Indicates information for identifying a high bit rate channel and a low bit rate channel, an independent audio channel, or the like. For example, on the broadcast station side, the same program content is encoded at several bit rates, and different PIs are set for each.
Broadcast with D added. That is, it means that one PID broadcasts at a high bit rate, and the content to which another PID is added broadcasts at a low bit rate. The receiver side operates so as to select a receivable PID according to the reception condition. This is because radio waves from satellites are weak in BS digital broadcasting, etc.
This is because it is not always possible to receive high bit rate contents. When switching PIDs depending on conditions while receiving the same content, smooth switching cannot be expected if the timing of video and audio is different.
As shown in, adjustment is performed so that the timing does not shift between contents of different PIDs.

For details of the PID, see "ARIB S
Program arrangement information used for TD-B10 digital broadcasting 1.
2nd edition May 27, 1999 (The Association of Radio Industries and Businesses) "
No. P32, P42.

FIG. 2 is a time chart showing the operation of FIG.

Next, the operation of the present embodiment will be described in more detail with reference to FIGS.

The TS signal 1 is as shown in FIG.
TSP1, TSP2, TSP3, TSP4, TSP5,
It is assumed that the formats are TSP6 and TSP7.

Further, each TSP has a PID (Pac
There are two types of ket ID), and PID = 0x100 (1
Hexadecimal number 100) and PID = 0x200 (hexadecimal number 200) are shown.

When the TS signal 1 is input to the demultiplexer 5, the PID No. A TSP having a PID of 0x100 is output to the delay buffer 6 for 1 and a PID No. It is said that the TSP having a PID of 0x200 is output to the 2 delay buffer 7, so that the demultiplexing unit 5 uses the TSP having a different PID.
The separated outputs 47, 48, 49 of different PID Nos. 1
Delay buffer 6, PID No. 2 delay buffer 7,
PID No. It operates so as to output to the M delay buffer 8.

PID No. The signal input to the 1 delay buffer 6 is as shown in FIG.
o. The signal output from the 1 delay buffer 6 is output with a delay of D1 as shown in FIG.

On the other hand, PID No. The signal input to the 2 delay buffer 7 is as shown in FIG.
DNo. The signal output from the second delay buffer 7 is shown in FIG.
As shown in (e) of, the output is delayed by a delay time of D2.

By the above operation, from the TS signal 1 to PI
No. of D = 0x100. 1 TSP and PID = 0x2
No. 00. Even if the TSP of No. 1 is input at different timing, the PID No. 1 delay buffer 6 and PI
DNo. It is output from the second delay buffer 7 at the same timing. By multiplexing these TSPs by the multiplexer 50, the delay-compensated multiplexer output is obtained as the multiplexer output 44, as shown in FIG.

These operations in the TS signal circuit 40 are similarly performed in the TS signal circuit 40n provided for each TS signal.

Similar to the TSP of the TS signal circuit 40, the delay time is compensated by the TSP of the TS signal circuit 40n. Therefore, T from TS signal 1 to TS signal 1n
The delay time will be compensated for SP.

That is, for each of the input TS signal 1 to TS signal 1n, the delay time is compensated in PID units.

FIG. 3 is a block diagram showing a second embodiment of the MPEG2 TS multiplexer of the present invention.

In FIG. 3, components corresponding to those shown in FIG. 1 are designated by the same reference numerals or symbols, and their explanations are omitted.

In the present embodiment shown in FIG. 3, the demultiplexing section 9 which receives the TS signal 1 and outputs the demultiplexed output 53, the demultiplexed output 54 and the demultiplexed output 55, and the demultiplexed output 53 are delayed by the delay control signal 59. The delay buffer 10 for the program 1 which outputs the delay buffer output 56, the delay buffer 11 for the program 2 which delays the separation output 54 by the delay control signal 59 and outputs the delay buffer output 57, and the delay control signal 59 which outputs the separation output 55. The delay buffer 12 for the program L, which is delayed by
The S signal circuit 60, the demultiplexing unit 9n which receives the TS signal 1n and outputs the demultiplexed output 53n, the demultiplexed output 54n and the demultiplexed output 55n, and the demultiplexed output 53n are delayed by the delay control signal 59 to obtain the delay buffer output 56n. The delay buffer 10n for program 1 to output, the delay buffer 11n for program 2 which delays the separated output 54n by the delay control signal 59 and outputs the delay buffer output 57n, and the separated output 5
A circuit 60n for TS signal having a delay buffer 12n for program L for delaying 5n by a delay control signal 59 and outputting a delay buffer output 58n, a delay buffer controller 61 for outputting a delay control signal 59, and a delay buffer output 56. -58 and delay buffer outputs 56n-58n are input, multiplexed, and output as a multiplexer output 51.

Referring to FIG. 3, the MPEG2 TS multiplexer inputs the TS signal 1 from the MPEG ENCODER (not shown) or the like into the demultiplexer 9 of the TS signal circuit 60, and the demultiplexer 9 separates the TS signal 1. Separate output 53, 54, 5
5, the delay buffer 10 for program 1, the delay buffer 11 for program 2, and the delay buffer 1 for program L
The delay buffer outputs 56, 57, and 58, which are output to the output terminal 2 and further delayed by the delay control signal 59, are multiplexed by the multiplexer 52 and output as the multiplexer output 51.

The operation of the TS signal circuit 60n is TS
Since it is the same as the signal circuit 60, its explanation is omitted.

The delay control signal 59 output from the delay buffer control section 61 is output to the delay buffer 10 for program 1, the delay buffer 11 for program 2, and the delay buffer 12 for program L to control the delay amount.

The TS signal circuit 6 having the demultiplexing unit 9, the delay buffer 10 for program 1, the delay buffer 11 for program 2, and the delay buffer 12 for program L
Circuits having the same configuration as 0 are provided as TS signal circuits 60 to TS signal circuits 60n corresponding to the number of input TS signals 1 to TS signals 1n.

Here, the "program" indicates information corresponding to a channel (identifying a television station) in a television receiver. At first glance, the function of separating the TS signals and adjusting the mutual timing based on the program number is
Although it is considered meaningless because the broadcast contents of different broadcasting stations are mutually timed, this function is intended to be effective in the following situations.

That is, at present, a broadcasting station (hereinafter, simply “station”)
In some cases, both television and radio are broadcast. Such stations usually broadcast different programs on television and radio, but for example, in a baseball relay program, the same game may be broadcast live on both television and radio at the same time. The high school baseball Koshien tournament is a typical example. Among the viewers of such programs, there are those who listen to the sound on the radio while watching the television of the relay image. For such a viewer, unless the transmission timing between programs is adjusted by applying the configuration shown in FIG. 3, there is a disadvantage that the video and audio being viewed are separated from each other.

Terrestrial digital broadcasting (BS
In digital broadcasting (including digital broadcasting), television broadcasting and radio broadcasting do not necessarily have the same modulation method and data transmission rate (generally, they are broadcast at different data transmission rates). Therefore, the MPEG2 encoder depends on the difference in data transmission rate. The signal processing at the modulator and the modulator is different, and the signal delay time at the encoder and the modulator is different due to the difference in the processing.
As a result, even if the same sound of the same baseball stadium (for example, the hitting sound of a certain batter) is broadcast live on the TV and the radio, the video / audio output by the TV at the viewer's house and the audio output by the radio are the same. Deviations occur. This deviation is perceived as a phenomenon such as "a picture appears delayed with respect to sound" for a viewer who is listening to radio while watching television. A viewer who feels uncomfortable with this phenomenon complains to the station, and the station adjusts the audio output timing on the viewer side in order to deal with such a complaint.

In the embodiment shown in FIG. 3, even the content TS signals broadcast from the same broadcasting station are separated by utilizing the fact that the program numbers are different between the television and the radio, and the respective transmission timings are separated. Are adjusted to have a predetermined relationship. This “predetermined relationship” is
It is obtained from the amount of misalignment that can be specified by the control state of the PEG encoder and the modulation method of each layer. At this time, if the signal processing delay on the receiver side differs depending on the modulation method, data transmission rate, etc., this difference will also be taken into consideration. However, at present, the signal processing delay time on the receiver side is considered to be constant for each modulation method and data transmission rate.

Therefore, even for the above-mentioned viewers, it is possible to perform the broadcasting after adjusting the timings of the television and radio programs.

For details of the program number,
"ARIB STD-B10 Program Sequence Information 1.2 version used for digital broadcasting May 27, 1999 (corporate corporation
Radio Industry Association) "P32, P88.

FIG. 4 is a time chart showing the operation of FIG.

Next, the operation of the present embodiment will be described in more detail with reference to FIGS. 3 and 4.

As shown in FIG. 4 (a), the TS signal 1 is TSP1, TSP2, TSP3, TSP4, TSP.
5, the TSP6 and the TSP7 have the format configuration.

It is also assumed that those TSPs belong to either program 1 or program 2.

In MPEG, the mapping between the program numbers and the program elements forming them is defined in PMT (Program Map Table). Normally, a plurality of program elements are used for one program, and each program element uses one PID.

When the TS signal 1 is input to the demultiplexer 9, the TSP belonging to the program 1 is output to the delay buffer 10 for the program 1, and the TSP belonging to the program 2 is output to the delay buffer 11 for the program 2. As described above, the demultiplexing unit 9 operates so as to output the demultiplexed outputs 53, 54, 55 of the TSPs belonging to different programs to the different program 1 delay buffers 10 to program L delay buffers 12.

The signal input to the program 1 delay buffer 10 is as shown in FIG. 4B, and the signal output from the program 1 delay buffer 10 is D1 as shown in FIG. 4C. (= Program 1 of TS signal 1
The output is delayed by a delay time (delay time of the delay buffer 10).

On the other hand, the signal input to the program 2 delay buffer 11 is as shown in FIG. 4D, and the signal output from the program 2 delay buffer 11 is shown in FIG.
As shown in (e), the output is delayed by the delay time D2 (= the delay time of the delay buffer 11 for the program 2 of the TS signal 1).

By the above operation, the TSP belonging to the program 1 and the TSP belonging to the program 2 from the TS signal 1
Program 1
The delay buffer 10 for program and the delay buffer 11 for program 2 output at the same timing. By multiplexing these TSPs in the multiplexing unit 52, as shown in FIG. 4 (f), the delay-compensated multiplexing unit 52 is used.
Is obtained as the multiplexer output 51.

These operations in the TS signal circuit 60 are as follows.
The same applies to the TS signal circuit 60n provided for the TS signal 1n.

Similar to the TSP of the TS signal circuit 60, the delay time is compensated by the TSP of the TS signal circuit 60n. Therefore, T from TS signal 1 to TS signal 1n
The delay time will be compensated for SP.

That is, for each input TS signal, the delay time is compensated in program units.

FIG. 5 is a block diagram showing a third embodiment of the MPEG2 TS multiplexer of the present invention.

In FIG. 5, components corresponding to those shown in FIG. 1 are designated by the same reference numerals or symbols, and their description will be omitted.

In the present embodiment shown in FIG. 5, the demultiplexing unit 13 which receives the TS signal 1 and outputs the demultiplexed output 63, the demultiplexed output 64 and the demultiplexed output 65, and the demultiplexed output 63 are delayed by the delay control signal 69. The delay buffer 14 for layer A which outputs the delay buffer output 66, the delay buffer 15 for layer B which delays the separation output 64 by the delay control signal 69 and outputs the delay buffer output 67, and the delay output 65 which outputs the delay control signal 69. Circuit 70 for the TS signal having the delay buffer 16 for layer C which is delayed by
And the demultiplexing unit 13n which receives the TS signal 1n and outputs the separated output 63n, the separated output 64n, and the separated output 65n.
And a delay buffer 14n for layer A that delays the separated output 63n by the delay control signal 69 and outputs the delay buffer output 66n, and a delay for layer B that delays the separated output 64n by the delay control signal 69 and outputs the delay buffer output 67n. A circuit for TS signal 70n having a buffer 15n and a delay buffer 16n for layer C which delays the separated output 65n by a delay control signal 69 and outputs a delay buffer output 68n.
And the delay buffer controller 7 for outputting the delay control signal 69.
1 and the delay buffer outputs 66 to 68 and the delay buffer outputs 66n to 68n to be multiplexed and output as a multiplexer output 72.

Referring to FIG. 5, the MPEG2 TS multiplexer inputs TS signal 1 from MPEG ENCODER (not shown) or the like to the demultiplexing unit 13 of the TS signal circuit 70, and the demultiplexing unit 13 separates it. Separate output 63, 6
4, 65 are output to the delay buffer 14 for layer A, the delay buffer 15 for layer B, and the delay buffer 16 for layer C, respectively.
Further, the delay buffer outputs 66, 67, 68 delayed by the delay control signal 69 are multiplexed by the multiplexer 62 and output as the multiplexer output 72.

The operation of the TS signal circuit 70n is TS
Since it is the same as the signal circuit 70, description thereof will be omitted.

The delay control signal 69 output from the delay buffer control unit 71 is output to the delay buffer 14 for layer A, the delay buffer 15 for layer B, and the delay buffer 16 for layer C to control the delay amount.

A circuit having the same configuration as the TS signal circuit 70 having the demultiplexing unit 13, the layer A delay buffer 14, the layer B delay buffer 15, and the layer C delay buffer 16 receives the input TS signal 1 .. are provided as TS signal circuits 70 to TS signal circuits 70n corresponding to the number of TS signals 1n.

Here, the "layer" is information relating to the modulation operation of the modulator, for example, 64QAM, 16QA for each layer.
This indicates information that is modulated by a modulation method such as M, QPSK, or BPSK. Specifically, H with a high data transmission rate
64QAM modulation is performed in the layer for transmitting DTV programs,
It is said that 16QAM modulation is performed in an SDTV transmission layer that does not require such a high data transmission rate, and that in a certain layer, BPSK modulation that has the highest receivability is used even if the data transmission rate is low as a measure against a reception obstacle factor such as rain attenuation. To operate.

When it is not necessary to adjust the timing due to the broadcast content material (a live broadcast program in a studio or a program material to be sent by a VTR) (when the material sending side has made an adjustment in advance, etc.), It suffices to adjust the delay in each layer unit so that the timings on the receiving side are aligned according to the difference in the signal processing delay time in the modulator due to the difference.

In the embodiment shown in FIG. 5, a delay buffer is provided for each layer in the input circuit of the TS signal. The advantage of this method is that not only can the delay time difference between layers be compensated independently for each TS signal input, but also the input T
It is possible to correct even when there is a timing difference between the S signals (when it is necessary to adjust the timing relationship between the TS signal input 1 and the TS signal input 2, the compensation can be performed). ).

On the other hand, a disadvantage of this method is that the number of buffers increases. According to FIG. 5, since each TS signal input has three delay buffers in hierarchical units,
For example, if there are 10 input TS signals, 30 delay buffers are required.

Incidentally, since the capacity of the delay buffer is obtained by (transmission bit rate) × (delay time), for example, in order to secure the buffer capacity for 2 seconds when the transmission bit rate is 24 Mbps, 24 Mbps × 2 seconds = 48 Mbit.
Approximately 6 Mbytes of memory is required.

FIG. 6 is a time chart showing the operation of FIG.

Next, the operation of the present embodiment will be described in more detail with reference to FIGS. 5 and 6.

As shown in FIG. 6 (a), the TS signal 1 is TSP1, TSP2, TSP3, TSP4, TSP.
5, TSP6, TSP7, TSP8, TSP9, TSP
It is assumed that the format configuration is 10.

Each TSP has a layer A, a layer B, and a layer C.
It belongs to one of the following.

In the terrestrial digital television broadcasting system (ISDB-T system) in Japan, it is possible to carry out hierarchical transmission by a maximum of three layers using A layer, B layer and C layer, and which TSP is transmitted. Belongs to the hierarchy.

When this signal is input to the demultiplexer 13, the layer A delay buffer 14 stores the TS belonging to the layer A.
The demultiplexing unit 13 operates such that P is output, the TSP belonging to layer B is output to the delay buffer 15 for layer B, and the TSP belonging to layer C is output to the delay buffer 16 for layer C.

In this case, the signal input to the delay buffer 14 for layer A is as shown in FIG.
The signal output from the delay buffer 14 for use in FIG.
As shown in (1), the output is delayed by a delay time D1 (= delay time of the layer A delay buffer 14 of the TS signal 1).

On the other hand, the signal input to the layer B delay buffer 15 is as shown in (d) of FIG. 6, and the signal output from the layer B delay buffer 15 is as shown in (e) of FIG. Is output with a delay time of D2.

The same applies to the input / output of the delay buffer 16 for layer C.

By the above operation, the TS signal 1 to the layer A
Even if the TSP belonging to the layer A and the TSP belonging to the layer B are input at different timings, the delay buffer for layer A 14
And the delay buffer 15 for layer B outputs at the same timing. These TSPs are multiplexed by the multiplexing unit 6
By multiplexing at 2, the delay-compensated output of the multiplexer 62 is obtained as the multiplexer output 72 as shown in FIG.

These operations in the TS signal circuit 70 are as follows.
The same applies to the TS signal circuit 70n provided for the TS signal 1n.

Similar to the TSP of the TS signal circuit 60, the delay time is compensated by the TSP of the TS signal circuit 60n. Therefore, T from TS signal 1 to TS signal 1n
The delay time will be compensated for SP.

That is, for each input TS signal, the delay time is compensated for each layer.

FIG. 7 is a block diagram showing a fourth embodiment of the MPEG2 TS multiplexer of the present invention.

In FIG. 7, components corresponding to those shown in FIG. 1 are designated by the same reference numerals or symbols, and the description thereof will be omitted.

In the present embodiment shown in FIG. 7, a TS signal 1 is input and a TS signal circuit 80 having a demultiplexing unit 81 for outputting demultiplexed outputs 91, 92, 93 and a TS signal 1n are input. A TS signal circuit 80n having a demultiplexing unit 81n that outputs demultiplexed outputs 91n, 92n, and 93n, a layer A multiplexing unit 82 that multiplexes the demultiplexed outputs 91 to 91n, and outputs a multiplexed output 94, and a demultiplexed output Layer B multiplexer 83 that multiplexes 92 to demultiplexed output 92n and outputs multiplexed output 95; Layer C multiplexer 84 that multiplexes demultiplexed output 93 to demultiplexed output 93n and outputs multiplexed output 96; Delay buffer 85 for layer A that delays output 94 by delay control signal 100 and outputs delay buffer output 97
A delay buffer 86 for layer B which delays the multiplexed output 95 by the delay control signal 100 and outputs the delay buffer output 98, and a layer C which delays the multiplexed output 96 by the delay control signal 100 and outputs the delay buffer output 99. Delay buffer 87, a delay buffer control section 89 for outputting the delay control signal 100, and a multiplexing section 88 for inputting and multiplexing the delay buffer outputs 97 to 99 and outputting as a multiplexer output 90. .

Referring to FIG. 7, the MPEG2 TS multiplexer inputs the TS signal 1 from MPEG ENCODER (not shown) or the like into the demultiplexing unit 81 of the TS signal circuit 80, and the demultiplexing unit 81 separates it. Separate output 91, 9
2, 93 are layer A multiplexing section 82 and layer B multiplexing section 8 respectively.
3, output to the layer C multiplexing unit 84. Layer A multiplexing unit 8
The second multiplexed output 94 is output to the layer A delay buffer 85, and the delay buffer output 97 is output to the multiplexing unit 88. The multiplexed output 95 of the layer B multiplexer 83 is layer B
Is output to the output delay buffer 86, and the delay buffer output 98 is output to the multiplexing unit 88. Layer C Multiplexing Unit 84
The multiplexed output 96 is output to the layer C delay buffer 87, and the delay buffer output 99 is output to the multiplexer 88.

The output of the multiplexer 88 is output as the multiplexer output 90.

The delay control signal 100 output from the delay buffer control unit 89 is output to the layer A delay buffer 85, the layer B delay buffer 86, and the layer C delay buffer 87 to control the delay amount.

A circuit having the same configuration as the TS signal circuit 80 having the demultiplexing unit 81 is connected to the input TS signals 1 to
TS signal circuits 80 to TS corresponding to the number of TS signals 1n
It is provided as a signal circuit 80n.

The fourth embodiment shown in FIG. 7 is obtained by reducing the number of buffers as compared with the third embodiment of FIG. In FIG. 5, the input TS signal is once separated and multiplexed for each layer used for transmission, and a delay buffer is provided for each layer to adjust the timing. In this method, the number of delay buffers is minimized, but the adjustment of delay time is limited to each layer.

7 and 5 can be selected and implemented according to the timing adjustment requirements of the broadcasting system. Therefore, the delay time of the input TS signal is compensated for each layer, and at the same time, the number of layer delay buffers can be reduced.

In the above description, the operation when the TSP input from each TS signal input at a different timing operation is output at the same timing has been described, but the following timing operation is also possible. .

That is, first, an operation of outputting TSP input at different timings with a certain timing difference, second, operation of outputting TSP input at the same timing with a certain timing difference, and third operation. The TSP input at the same timing can be output at the same timing.

In the present invention, M having a delay compensation function is used.
Although the PEG2 TS multiplexer is used, it may be used as a simple delay compensator instead of the multiplexer.

As described above, the delay compensation function can be provided by using the delay buffer in the MPEG2 TS multiplexer.

In digital broadcasting, MPEG EN
A CODER, an MPEG2 TS multiplexer, a modulator, etc. are used. When using a plurality of types of MPEG ENCODER, the encoding delay may differ for each MPEG ENCODER, and delay compensation may be necessary. .

When hierarchical transmission is performed using an MPEG2 TS multiplexer or modulator, there is a difference in delay amount between layers and delay compensation may be necessary.

Therefore, the MPEG2 T having the delay reward function
A delay buffer is provided for each TS signal of the S multiplex device, and the delay amount is controlled by the delay buffer control unit and then multiplexed by the multiplexing unit, whereby delay compensation is possible.

The above-mentioned MPEG2 TS multiplexing apparatus converts a plurality of video / audio signals into a plurality of MPEG ENCOD signals.
It is applied to a digital broadcasting system that compresses and codes by ER, multiplexes and transmits.

[0127]

As described above, the MPEG of the present invention is used.
2 The TS multiplexer inputs the TS signal from the MPEG ENCODER or the like into the delay buffer and outputs the output by the multiplexing unit, so that the TSP input from each TS signal input at the different timing is the same. This has the effect that finer delay compensation for outputting at the timing can be performed with a simple circuit configuration.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of an MPEG2 TS multiplexer of the present invention.

FIG. 2 is a time chart showing the operation of FIG.

FIG. 3 is a block diagram showing a second embodiment of an MPEG2 TS multiplexer of the present invention.

FIG. 4 is a time chart showing the operation of FIG.

FIG. 5 is a block diagram showing a third embodiment of an MPEG2 TS multiplexer of the present invention.

FIG. 6 is a time chart showing the operation of FIG.

FIG. 7 is a block diagram showing a fourth embodiment of an MPEG2 TS multiplexer of the present invention.

FIG. 8 is a system diagram showing an example of digital broadcasting using a conventional MPEG2 TS multiplexer.

FIG. 9 is a block diagram showing a conventional MPEG2 TS multiplexer.

FIG. 10 is a time chart showing the operation of FIG.

[Explanation of symbols]

1, 1n TS signal 2 multiplexer 3 delay buffer controller 4, 4n delay buffer 5, 5n demultiplexer 6, 6n PIDNo. 1 delay buffer 7, 7n PID No. 2 delay buffer 8, 8n PID No. M delay buffer 9, 9n demultiplexing unit 10, 10n program 1 delay buffer 11, 11n program 2 delay buffer 12, 12n program L delay buffer 13, 13n demultiplexing unit 14, 14n layer A delay buffer 15, 15n Layer B delay buffer 16, 16n Layer C delay buffer 20, 21, 22 MPEG ENCODER 23 MPEG2 TS multiplexer 24 Modulator 25, 25n TS signal circuit 26, 26n Delay buffer output 27 Multiplexer output 28 Delay control signal 31, 32, 33 Video and audio signals 34, 35, 36 Compressed coded output signal 37 Multiplexed signal 38 Modulated signal 40, 40n TS signal circuit 41, 42, 43, 41n, 42n, 43n Delay buffer output 44 Multiplexer output 45 delay control signal 46 delay buffer control 47, 48, 49, 47n, 48n, 49n Separation output 50 Multiplexer 51 Multiplexer output 52 Multiplexer 53, 54, 55, 53n, 54n, 55n Separation output 56, 57, 58, 56n, 57n, 58n Delay Buffer output 59 Delay control signal 60, 60n TS signal circuit 61 Delay buffer control unit 62 Multiplexing unit 63, 64, 65, 63n, 64n, 65n Separation output 66, 67, 68, 66n, 67n, 68n Delay buffer output 69 Delay control signal 70, 70n TS signal circuit 71 Delay buffer control section 72 Multiplexer output 80, 80n TS signal circuit 81, 81n Demultiplexing section 82 Layer A multiplexing section 83 Layer B multiplexing section 84 Layer C multiplexing section 85 Layer A Delay Buffer 86 Layer B Delay Buffer 87 Layer C Delay Buffer 88 Multiplexer 89 Delay Bar Buffer control unit 90 Multiplexer output 91, 92, 93, 91n, 92n, 93n Separate output 94, 95, 96 Multiplexed output 97, 98, 99 Delay buffer output 100 Delay control signal

Continued front page    F term (reference) 5C059 KK34 MA00 RB02 RC08 SS02                       UA02 UA34 UA35 UA38                 5C063 AA01 AB03 AB07 AC01 CA23                       CA36 DA07 DA13                 5K028 AA01 AA06 BB04 CC05 DD01                       DD02 EE03 EE08 KK01 KK03                       KK23 SS05 SS24

Claims (8)

[Claims] 1. MPEG2 (Mo
Ving Picture Experts Grou
p2) A TS (Transport Stream) multiplexer, which receives a TS signal which is encoded stream data, and outputs m (m is an integer of 2 or more) delay buffers under the control of delay control signals. n (n is an integer of 2 or more)
A number of TS signal circuits; a delay buffer control unit that outputs the delay control signal; a multiplexer that inputs a total of m × n delay buffer outputs, multiplexes them, and outputs them as a multiplexer output; The TS signal circuit inputs the TS signal and outputs m demultiplexed outputs; and delays each of the m demultiplexed outputs by the delay control signal. MPEG delay stream output device for outputting P delay buffers for each of PIDs; 2. MPEG2 TS in digital broadcasting
A first multiplexer / demultiplexer, which is a multiplexer and which inputs a first TS signal which is encoded stream data and outputs a first separated output, a second separated output, and a third separated output; The first PID No. which delays the first separated output by the delay control signal and outputs the first delay buffer output. A delay buffer for 1; delays the second separated output by the delay control signal;
Of the second PID No. A second delay buffer; a third PID No. that delays the third separated output by the delay control signal, and outputs a third delay buffer output. A first TS signal circuit having an M delay buffer; and a second TS signal which is input and outputs a fourth separation output, a fifth separation output, and a sixth separation output. Demultiplexer;
Delaying the fourth separated output by the delay control signal,
The fourth PID No. that outputs the fourth delay buffer output.
A first delay buffer for delaying the fifth separated output by the delay control signal and outputting a fifth delay buffer output. A second delay buffer; a sixth PID No. that delays the sixth separated output by the delay control signal, and outputs a sixth delay buffer output. A second TS signal circuit having an M delay buffer; a delay buffer control section for outputting the delay control signal; the first to third delay buffer outputs and the fourth to sixth
And a multiplexer for inputting the output of the delay buffer of 1. and multiplexing them for output as a multiplexer output. 3. MPEG2 TS in digital broadcasting
A multiplexer, which receives a TS signal which is encoded stream data and outputs L (L is an integer of 2 or more) delay buffer outputs under the control of a delay control signal (n is an integer of 2 or more) T's
An S signal circuit; a delay buffer control section for outputting the delay control signal; and a multiplexing section for inputting a total of L × n delay buffer outputs and multiplexing them for output as a multiplexer output. A circuit for the TS signal receives the TS signal and outputs a demultiplexing output of L lines; delays each of the demultiplexing outputs of the L lines by the delay control signal, and delays the L lines. An MPEG2 TS multiplexer having L program delay buffers each outputting a buffer output; 4. MPEG2 TS in digital broadcasting
A first multiplexer / demultiplexer, which is a multiplexer and which inputs a first TS signal which is encoded stream data and outputs a first separated output, a second separated output, and a third separated output; A first program 1 delay buffer for delaying the first separated output by a delay control signal and outputting a first delay buffer output; and a second separated output for delaying the second separated output by the delay control signal. A second program 2 delay buffer that outputs a delay buffer output; a third program L delay buffer that delays the third separated output by the delay control signal and outputs a third delay buffer output; A first TS signal circuit having: and a second demultiplexing unit which inputs the second TS signal and outputs a fourth demultiplexed output, a fifth demultiplexed output, and a sixth demultiplexed output;
Delaying the fourth separated output by the delay control signal,
Fourth program 1 for outputting the fourth delay buffer output
A delay buffer for program; a fifth delay buffer for program 2, which delays the fifth separation output by the delay control signal and outputs a fifth delay buffer output; and a sixth separation output for the delay control signal. A second TS signal circuit having a sixth program L delay buffer that outputs a sixth delay buffer output after being delayed by a delay buffer control unit that outputs the delay control signal; First to third delay buffer outputs and the fourth to sixth
And a multiplexer for inputting the output of the delay buffer of 1. and multiplexing them for output as a multiplexer output. 5. MPEG2 TS in digital broadcasting
A multiplexer, which receives a TS signal which is encoded stream data and outputs k (k is an integer of 2 or more) delay buffer outputs under the control of a delay control signal (n is an integer of 2 or more) T's
An S signal circuit; a delay buffer control section for outputting the delay control signal; and a multiplexing section for inputting a total of k × n delay buffer outputs and multiplexing them for output as a multiplexer output. A circuit for the TS signal, which inputs the TS signal and outputs k demultiplexed outputs; and delays each of the k demultiplexed outputs by the delay control signal, An MPEG2 TS multiplexer, comprising: k layer delay buffers each outputting a buffer output; 6. MPEG2 TS in digital broadcasting
A first multiplexer / demultiplexer, which is a multiplexer and which inputs a first TS signal which is encoded stream data and outputs a first separated output, a second separated output, and a third separated output; A first layer A delay buffer for delaying a first separated output by a delay control signal and outputting a first delay buffer output; a second separated output delayed by the delay control signal, and a second A second layer B delay buffer for outputting a delay buffer output;
Delaying the third separated output by the delay control signal,
A first TS signal circuit having a third layer C delay buffer that outputs a third delay buffer output; and a second TS signal are input, and a fourth separation output and a fifth separation are provided. An output, a second demultiplexer for outputting a sixth demultiplexed output;
Delaying the fourth separated output by the delay control signal,
A fourth layer A delay buffer that outputs a fourth delay buffer output; and a fifth layer B delay that delays the fifth separated output by the delay control signal and outputs a fifth delay buffer output A second TS signal circuit having a buffer; and a sixth layer C delay buffer that delays the sixth separated output by the delay control signal and outputs a sixth delay buffer output; A delay buffer control unit for outputting a delay control signal, the first to third delay buffer outputs and the fourth to sixth delay buffer outputs
And a multiplexer for inputting the output of the delay buffer of 1. and multiplexing them for output as a multiplexer output. 7. MPEG2 TS in digital broadcasting
A first multiplexer / demultiplexer which is a multiplexer and which inputs a first TS signal which is encoded stream data and outputs a first separated output, a second separated output, and a third separated output; A second demultiplexing unit that inputs the second TS signal and outputs a fourth demultiplexed output, a fifth demultiplexed output, and a sixth demultiplexed output; and the first demultiplexed output and the fourth demultiplexed output. A layer A multiplexer that multiplexes and outputs a first multiplexed output; a layer B multiplexer that multiplexes the second demultiplexed output and the fifth demultiplexed output and outputs a second multiplexed output A layer C multiplexer that multiplexes the third demultiplexed output and the sixth demultiplexed output and outputs a third multiplexed output; and delays the first multiplexed output with a delay control signal, A delay buffer for layer A, which outputs a first delay buffer output; A delay buffer for layer B that is delayed by the delay control signal and outputs a second delay buffer output; a layer C that delays the third multiplexed output by the delay control signal and outputs a third delay buffer output A delay buffer for outputting a delay control signal; a delay buffer control section for outputting the delay control signal;
A multiplexer for inputting the output of the delay buffer of 1. and multiplexing them for output as a multiplexer output; 8. The MP according to any one of claims 1 to 7.
A digital broadcasting system, wherein the EG2 TS multiplexer is applied to a digital broadcasting in which a plurality of video / audio signals are compression-encoded by a plurality of MPEG ENCODERs, multiplexed and transmitted.