JP2003078399A5 - Signal control circuit and image forming apparatus - Google Patents
Signal control circuit and image forming apparatus Download PDFInfo
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請求項１記載の発明は、
多段接続された複数の遅延素子により、基準クロック信号を遅延させ、各段毎に遅延基準クロック信号として出力する第１の遅延手段と、
多段接続された複数の遅延素子により、被制御信号を遅延させ、各段毎に遅延被制御信号として出力する第２の遅延手段と、
前記遅延基準クロック信号に基づいて、前記基準クロック信号の所定分解能である遅延量を演算する遅延量演算手段と、
前記遅延量演算手段により演算された遅延量に基づいて、前記遅延被制御信号の内から択一的に信号を選択し、選択した信号を外部出力する信号選択手段と、
を備えることを特徴としている。
The invention according to claim 1 is
First delay means for delaying the reference clock signal by a plurality of delay elements connected in multiple stages, and outputting each as a delayed reference clock signal for each stage;
Second delay means for delaying the controlled signal by a plurality of delay elements connected in multiple stages and outputting the delayed controlled signal for each stage;
On the basis of the delayed reference clock signal, and the delay amount calculating means for calculating a delay amount is a predetermined resolution of the reference clock signal,
Signal selection means for alternatively selecting a signal from among the delayed controlled signals based on the delay amount calculated by the delay amount calculation means, and outputting the selected signal to the outside;
It is characterized by having.
請求項１記載の発明によれば、遅延基準クロック信号に基づいて基準クロック信号の所定分解能である遅延量を演算する。そして、この遅延量に基づいて遅延被制御信号の内から択一的に選択した信号を外部出力する。従って、基準クロック信号の周波数の変化に関わらず、基準クロック信号に対して所定の分解能で被制御信号を遅延させることができる。このため、被制御信号のタイミングを高精度で制御できる。また、基準クロック信号と、被制御信号とを別々に遅延させるため、同時に制御することができ、リアルタイムに被制御信号を遅延させることができる。
請求項２記載の発明は、請求項１記載の発明において、
所定信号を外部入力する入力手段と、
前記入力手段により入力された所定信号と同期する前記遅延基準クロック信号に基づいて、前記基準クロック信号の１周期分に係る前記遅延素子の段数を検出する検出手段と、
を備え、
前記遅延量演算手段は、前記検出手段により検出された段数に基づいて、前記遅延量を演算することを特徴としている。
請求項２に記載の発明によれば、例えば、パルス信号やステップ信号等の所定信号と同期する遅延基準クロック信号に基づいて、基準クロック信号の１周期分に係る遅延素子の段数を検出し、この段数に基づいて遅延量を演算する信号制御回路が実現される。
According to the first aspect of the invention , the delay amount which is the predetermined resolution of the reference clock signal is calculated based on the delay reference clock signal. Then, based on the delay amount, a signal selectively selected from among the delay controlled signals is externally output. Therefore, the controlled signal can be delayed with a predetermined resolution with respect to the reference clock signal regardless of the change in the frequency of the reference clock signal. Therefore, the timing of the controlled signal can be controlled with high accuracy. Further, since the reference clock signal and the controlled signal are separately delayed, they can be simultaneously controlled, and the controlled signal can be delayed in real time.
The invention described in claim 2 is the invention described in claim 1
An input unit for externally inputting a predetermined signal;
Detection means for detecting the number of stages of the delay elements related to one cycle of the reference clock signal based on the delay reference clock signal synchronized with the predetermined signal input by the input means;
Equipped with
The delay amount calculating means is characterized in that the delay amount is calculated based on the number of stages detected by the detecting means.
According to the second aspect of the present invention, for example, the number of stages of delay elements related to one cycle of the reference clock signal is detected based on the delay reference clock signal synchronized with a predetermined signal such as a pulse signal or step signal. A signal control circuit that calculates the delay amount based on the number of stages is realized.
請求項３記載の発明は、請求項１又は２記載の信号制御回路において、前記第１の遅延手段と前記第２の遅延手段は同一の回路構成であることを特徴としている。 The invention according to claim 3 is characterized in that in the signal control circuit according to claim 1 or 2 , the first delay means and the second delay means have the same circuit configuration.
請求項３記載の発明によれば、基準クロック信号に基づいて被制御信号の遅延量を演算することが容易にできる。 According to the third aspect of the invention, it is possible to easily calculate the delay amount of the controlled signal based on the reference clock signal.
請求項４記載の発明は、請求項１〜３の何れか一項に記載の信号制御回路において、前記遅延量演算手段は、前記第１の遅延手段の遅延特性を前記第２の遅延手段の遅延特性に合わせるために、遅延量を補正する補正手段を有することを特徴としている。 A fourth aspect of the present invention is the signal control circuit according to any one of the first to third aspects, wherein the delay amount calculating means is configured to compare the delay characteristic of the first delay means with the second delay means. In order to adjust to the delay characteristic, it is characterized by having a correction means for correcting the delay amount.
請求項４記載の発明によれば、第１の遅延手段の遅延特性と、第２の遅延手段の遅延特性とが異なっても、遅延特性を同一にすることができ、基準クロック信号と、被制御信号との遅延量を同一にできるため、基準クロック信号に基づいて演算された遅延量を被制御信号の遅延量に適用することができる。 According to the fourth aspect of the present invention, even if the delay characteristics of the first delay means and the delay characteristics of the second delay means are different, the delay characteristics can be made the same. Since the delay amount with the control signal can be made identical, the delay amount calculated based on the reference clock signal can be applied to the delay amount of the controlled signal.
請求項５記載の発明によれば、
多段接続された複数の遅延素子により基準クロック信号または被制御信号を遅延させ、各段毎に遅延基準クロック信号または遅延被制御信号として出力する遅延手段と、
前記遅延基準クロック信号に基づいて、前記基準クロック信号の所定分解能である遅延量を演算する遅延量演算手段と、
前記遅延量演算手段により演算された遅延量に基づいて、前記遅延被制御信号の内から択一的に信号を選択し、選択した信号を外部出力する信号選択手段と、
を備え、
前記遅延手段に入力する基準クロック信号と被制御信号とを切り替え、切り替えた信号に応じて、前記遅延手段、前記遅延量演算手段及び前記信号選択手段を作用させることを特徴としている。
According to the invention of claim 5 ,
Delay means for delaying a reference clock signal or a controlled signal by a plurality of delay elements connected in multiple stages and outputting the delayed reference clock signal or delayed controlled signal for each stage;
Delay amount calculating means for calculating a delay amount which is a predetermined resolution of the reference clock signal based on the delay reference clock signal;
Signal selection means for alternatively selecting a signal from among the delayed controlled signals based on the delay amount calculated by the delay amount calculation means , and outputting the selected signal to the outside;
Equipped with
The reference clock signal and the controlled signal input to the delay means are switched, and the delay means , the delay amount calculation means, and the signal selection means are operated according to the switched signal.
請求項５記載の発明によれば、１つの遅延手段により基準クロック信号と、被制御信号とを遅延させる。また、遅延基準クロック信号に基づいて基準クロック信号の所定分解能である遅延量を演算する。そして、この遅延量に基づいて遅延被制御信号の内から択一的に選択した信号を外部出力する。したがって、基準クロック信号の周波数の変化に関わらず、基準クロック信号に対して所定の分解能で、被制御信号を遅延させることができる。このため、被制御信号のタイミングを高精度で制御できる。また、同一の遅延手段により基準クロック信号と、被制御信号とを遅延させるので、基準クロック信号に基づいて演算した遅延量を被制御信号の遅延にそのまま適用することができる。
請求項６記載の発明は、請求項５記載の信号制御回路において、
所定信号を外部入力する入力手段と、
前記入力手段により入力された所定信号と同期する前記遅延基準クロック信号に基づいて、前記基準クロック信号の１周期分に係る前記遅延素子の段数を検出する検出手段と、
を有し、
前記遅延量演算手段は、前記検出手段により検出された段数に基づいて、前記遅延量を演算し、
前記遅延手段に入力する基準クロック信号と被制御信号とを切り替え、切り替えた信号に応じて、前記遅延手段、前記検出手段、前記遅延量演算手段及び前記信号選択手段を作用させることを特徴としている。
請求項６記載の発明によれば、例えば、パルス信号やステップ信号等の所定信号と同期する遅延基準クロック信号とに基づいて基準クロック信号の１周期分に係る遅延素子の段数を検出し、この段数に基づいて遅延量を演算する信号制御回路が実現される。
また、請求項７記載の発明のように、請求項１〜６の何れか一項に記載の信号制御回路において、前記被制御信号を、画像形成装置の書き出しのタイミングを制御するインデックス信号としてもよい。
また、請求項８記載の発明のように、請求項７記載の信号制御回路を備え、前記信号選択手段から外部出力される信号により前記書き出しタイミングが制御される画像形成装置を実現してもよい。
According to the invention of claim 5, the reference clock signal and the controlled signal are delayed by one delay means. Also, based on the delay reference clock signal, a delay amount which is a predetermined resolution of the reference clock signal is calculated. Then, based on the delay amount, a signal selectively selected from among the delay controlled signals is externally output. Therefore, the controlled signal can be delayed with a predetermined resolution with respect to the reference clock signal regardless of changes in the frequency of the reference clock signal. Therefore, the timing of the controlled signal can be controlled with high accuracy. Further, since the reference clock signal and the controlled signal are delayed by the same delay means, the delay amount calculated based on the reference clock signal can be applied as it is to the delay of the controlled signal.
The invention according to claim 6 is the signal control circuit according to claim 5.
An input unit for externally inputting a predetermined signal;
Detection means for detecting the number of stages of the delay elements related to one cycle of the reference clock signal based on the delay reference clock signal synchronized with the predetermined signal input by the input means;
Have
The delay amount calculation means calculates the delay amount based on the number of stages detected by the detection means;
The reference clock signal and the controlled signal input to the delay means are switched, and the delay means, the detection means, the delay amount calculation means, and the signal selection means are operated according to the switched signal. .
According to the invention described in claim 6, for example, the number of stages of delay elements related to one cycle of the reference clock signal is detected based on the delay reference clock signal synchronized with a predetermined signal such as a pulse signal or a step signal. A signal control circuit that calculates a delay amount based on the number of stages is realized.
Further, as in the invention according to claim 7, in the signal control circuit according to any one of claims 1 to 6, the controlled signal is also used as an index signal for controlling the writing start timing of the image forming apparatus. Good.
According to an eighth aspect of the present invention, an image forming apparatus may be realized, comprising the signal control circuit according to the seventh aspect, wherein the write start timing is controlled by a signal externally output from the signal selection means. .
請求項２記載の発明によれば、例えば、パルス信号やステップ信号等の所定信号と同期する遅延基準クロック信号に基づいて、基準クロック信号の１周期分に係る遅延素子の段数を検出し、この段数に基づいて遅延量を演算する信号制御回路が実現される。
請求項３に記載の発明によれば、基準クロック信号に基づいて被制御信号の遅延量を演算することが容易にできる。
According to the second aspect of the present invention, the number of stages of delay elements associated with one cycle of the reference clock signal is detected, for example, based on the delay reference clock signal synchronized with a predetermined signal such as a pulse signal or step signal. A signal control circuit that calculates a delay amount based on the number of stages is realized.
According to the third aspect of the present invention, it is possible to easily calculate the delay amount of the controlled signal based on the reference clock signal.
請求項４記載の発明によれば、基準クロック信号と、被制御信号との遅延量を同一にできるため、基準クロック信号に基づいて演算された遅延量を被制御信号の遅延量に適用することができる。 According to the fourth aspect of the invention, since the delay amounts of the reference clock signal and the controlled signal can be made identical, the delay amount calculated based on the reference clock signal is applied to the delay amount of the controlled signal. Can.
請求項５記載の発明によれば、基準クロック信号の周波数の変化に関わらず、基準クロック信号に対して所定の分解能で、被制御信号を遅延させることができる。このため、被制御信号のタイミングを高精度で制御できる。また、同一の遅延手段により基準クロック信号と、被制御信号とを遅延させるので、基準クロック信号に基づいて演算した遅延量を被制御信号の遅延にそのまま適用することができる。
請求項６に記載の発明によれば、例えば、パルス信号やステップ信号等の所定信号と同期する遅延基準クロック信号とに基づいて基準クロック信号の１周期分に係る遅延素子の段数を検出し、この段数に基づいて遅延量を演算する信号制御回路が実現される。
請求項７記載の発明によれば、画像形成装置の書き出しタイミングを制御するインデックス信号を被制御信号とする信号制御回路が実現される。
請求項８記載の発明によれば、インデックス信号を遅延させた遅延被制御信号の内から選択された信号によって書き出しタイミングが制御される画像形成装置を実現できる。
According to the fifth aspect of the present invention, the controlled signal can be delayed with a predetermined resolution with respect to the reference clock signal regardless of the change in the frequency of the reference clock signal. Therefore, the timing of the controlled signal can be controlled with high accuracy. Further, since the reference clock signal and the controlled signal are delayed by the same delay means, the delay amount calculated based on the reference clock signal can be applied as it is to the delay of the controlled signal.
According to the invention described in claim 6, for example, the number of stages of delay elements related to one cycle of the reference clock signal is detected based on the delay reference clock signal synchronized with a predetermined signal such as a pulse signal or a step signal; A signal control circuit that calculates the delay amount based on the number of stages is realized.
According to the seventh aspect of the present invention, a signal control circuit is realized in which an index signal for controlling the write start timing of the image forming apparatus is a controlled signal.
According to the eighth aspect of the present invention, it is possible to realize an image forming apparatus in which the write start timing is controlled by the signal selected from the delay controlled signals obtained by delaying the index signal.
Claims (8)
多段接続された複数の遅延素子により、被制御信号を遅延させ、各段毎に遅延被制御信号として出力する第２の遅延手段と、
前記遅延基準クロック信号に基づいて、前記基準クロック信号の所定分解能である遅延量を演算する遅延量演算手段と、
前記遅延量演算手段により演算された遅延量に基づいて、前記遅延被制御信号の内から択一的に信号を選択し、選択した信号を外部出力する信号選択手段と、
を備えることを特徴とする信号制御回路。First delay means for delaying the reference clock signal by a plurality of delay elements connected in multiple stages, and outputting each as a delayed reference clock signal for each stage;
Second delay means for delaying the controlled signal by a plurality of delay elements connected in multiple stages and outputting the delayed controlled signal for each stage;
On the basis of the delayed reference clock signal, and the delay amount calculating means for calculating a delay amount is a predetermined resolution of the reference clock signal,
Signal selection means for alternatively selecting a signal from among the delayed controlled signals based on the delay amount calculated by the delay amount calculation means, and outputting the selected signal to the outside;
A signal control circuit comprising:
前記入力手段により入力された所定信号と同期する前記遅延基準クロック信号に基づいて、前記基準クロック信号の１周期分に係る前記遅延素子の段数を検出する検出手段と、
を備え、
前記遅延量演算手段は、前記検出手段により検出された段数に基づいて、前記遅延量を演算することを特徴とする請求項１記載の信号制御回路。 An input unit for externally inputting a predetermined signal;
Detection means for detecting the number of stages of the delay elements related to one cycle of the reference clock signal based on the delay reference clock signal synchronized with the predetermined signal input by the input means;
Equipped with
2. The signal control circuit according to claim 1, wherein the delay amount calculating means calculates the delay amount based on the number of stages detected by the detecting means .
前記遅延基準クロック信号に基づいて、前記基準クロック信号の所定分解能である遅延量を演算する遅延量演算手段と、
前記遅延量演算手段により演算された遅延量に基づいて、前記遅延被制御信号の内から択一的に信号を選択し、選択した信号を外部出力する信号選択手段と、
を備え、前記遅延手段に入力する基準クロック信号と被制御信号とを切り替え、切り替えた信号に応じて、前記遅延手段、前記遅延量演算手段及び前記信号選択手段を作用させることを特徴とする信号制御回路。Delay means for delaying a reference clock signal or a controlled signal by a plurality of delay elements connected in multiple stages and outputting the delayed reference clock signal or delayed controlled signal for each stage;
On the basis of the delayed reference clock signal, and the delay amount calculating means for calculating a delay amount is a predetermined resolution of the reference clock signal,
Signal selection means for alternatively selecting a signal from among the delayed controlled signals based on the delay amount calculated by the delay amount calculation means, and outputting the selected signal to the outside;
And switching the reference clock signal and the controlled signal input to the delay means , and operating the delay means , the delay amount calculation means, and the signal selection means according to the switched signal. Control circuit.
前記入力手段により入力された所定信号と同期する前記遅延基準クロック信号に基づいて、前記基準クロック信号の１周期分に係る前記遅延素子の段数を検出する検出手段と、 Detection means for detecting the number of stages of the delay elements related to one cycle of the reference clock signal based on the delay reference clock signal synchronized with the predetermined signal input by the input means;
を備え、 Equipped with
前記遅延量演算手段は、前記検出手段により検出された段数に基づいて、前記遅延量を演算し、 The delay amount calculation means calculates the delay amount based on the number of stages detected by the detection means;
前記遅延手段に入力する基準クロック信号と被制御信号とを切り替え、切り替えた信号に応じて、前記遅延手段、前記検出手段、前記遅延量演算手段及び前記信号選択手段を作用させることを特徴とする請求項５記載の信号制御回路。 The reference clock signal and the controlled signal input to the delay means are switched, and the delay means, the detection means, the delay amount calculation means, and the signal selection means are operated according to the switched signal. The signal control circuit according to claim 5.
前記信号選択手段から外部出力される信号により前記書き出しタイミングが制御されることを特徴とする画像形成装置。 An image forming apparatus, wherein the write start timing is controlled by a signal externally output from the signal selection unit.
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| JP2001266051A JP3760822B2 (en) | 2001-09-03 | 2001-09-03 | Signal control circuit and image forming apparatus |
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| JP2001266051A JP3760822B2 (en) | 2001-09-03 | 2001-09-03 | Signal control circuit and image forming apparatus |
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