JP2003078113A - Semiconductor device and its drive method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an MFMIS semiconductor device having a device structure capable of operating optimally, taking the polarization of a dielectric body into consideration. SOLUTION: A semiconductor device is composed of a control voltage feeding unit 10, a MOS transistor Tr1 equipped with a gate electrode 9, a drain electrode 4a, a source region 4b, and a gate insulating film 7 of thickness 3 nm, and a capacitor MFM1 equipped with an intermediate electrode 14 interposed between the gate electrode 9 of the MOS transistor Tr1 and the control voltage feeding unit 10, an upper electrode 19, and a ferroelectric film 16. Provided that the residual dielectric polarization and maximum polarization of the capacitor MFM1 are represented by Pr and Pmax respectively, the area ratio of the MOS transistor Tr1 to the capacitor MFM1 is designed so as to make the ratio Pr/Pmax large and not to cause a dielectric breakdown to the gate insulating film, so that the semiconductor device of this design can be set small in ON-state resistance.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device using an MFMIS type ferroelectric gate transistor.

[0002]

2. Description of the Related Art In recent years, with the progress of multimedia, the increase in capacity of semiconductor memories capable of handling large amounts of digital information at high speed has been further accelerated. At the same time, as the demand for portable products has increased, “non-volatility”, in which memory is retained even after power-off, has become more important than ever.

Under such a background, a non-volatile memory device having a ferroelectric film is a semiconductor memory in which the area per bit is theoretically the smallest, and at the same time, the writing speed which has been a problem in the flash memory. Is also said to be the ultimate semiconductor memory because it has a speed comparable to that of a conventional dynamic random access memory (approximately several nanoseconds).

As a prior art example of a semiconductor element functioning as such a non-volatile memory device, there is a "non-volatile semiconductor memory device and its manufacturing method" described in JP-A-10-27856.

FIG. 17 is a sectional view showing the structure of a conventional semiconductor element that functions as a non-volatile memory device. As shown in the same figure, the conventional semiconductor device has Me in order from the top.
tal / Ferroelectric / Metal / In
It is a semiconductor element which is generally called an MFMIS type ferroelectric gate transistor because it has a structure of a "sulator / Semiconductor".

That is, the conventional semiconductor device has, for example, p
Semiconductor substrate 101 containing type impurities, and semiconductor substrate 101
An element isolation insulating film 105 provided on the gate insulating film 105 and a gate oxide film 1 made of SiO ₂ provided on the semiconductor substrate 101.
02, a gate electrode 106 made of a conductor that is a floating gate provided on the gate oxide film 102,
The lower electrode 107, the ferroelectric film 108, and the upper electrode 109 which are provided on the gate electrode 106 and constitute the MFM capacitor, and the gate electrode 106 of the semiconductor substrate 101.
Drain regions 1 provided on both sides of the drain and including n-type impurities
03 and source region 104 and MFM on the gate electrode
The sidewall 110 made of an insulator provided on the side surface of the capacitor, the insulating film 111 made of an insulator covering the substrate, and the insulating film 111 are opened to form the drain region 10.
3, wirings 112a, 112b, and 112c provided on the source region 104 and the upper electrode 109, respectively. The area of the MFM capacitor is suppressed to 5 to 30% of the area of the gate oxide film 102.

In such an MFMIS type semiconductor element, since a drain current can be controlled by applying a voltage to the upper electrode through the wiring 112c and controlling the polarization of the ferroelectric film 108, information is retained. Can function as a memory.

Further, as can be seen from FIG. 17, the conventional M
The FMIS-type semiconductor element has an M that sandwiches the gate oxide film 102.
It can be expressed in a circuit diagram as a series connection of an IS capacitor and an MFM capacitor sandwiching a ferroelectric film. Therefore, the drive voltage applied to the upper electrode 109 is distributed to the MIS capacitor and the MFM capacitor.

In general, a ferroelectric substance has a much higher dielectric constant than SiO _2. Therefore, even if a driving voltage is applied to the upper electrode 109, the voltage distributed to the MFM capacitor is small, and the polarization inversion of the ferroelectric substance is caused. There was a problem that was not performed well. In order to solve this problem, in the above-mentioned conventional example, the capacitance of the ferroelectric capacitor does not exceed twice the capacitance of the gate oxide film capacitor, that is, the electrode area of the ferroelectric capacitor is the electrode of the gate oxide film capacitor. It is configured to be about 5 to 30% of the area.

In consideration of such a distribution voltage to the MFM capacitor, in the conventional semiconductor element designing method, the coupling ratio (Cox) between the capacitance Cf of the ferroelectric capacitor and the capacitance Cox of the gate oxide film capacitor is used. / (C
f + Cox)). That is, the capacitance C of the flat plate capacitor sandwiching the insulator is the area S of the electrode,
Using the electrode spacing d and the dielectric constant ε of the insulator, C = ε × S / d
Therefore, in order to reduce the capacitance C, the dielectric constant ε and the electrode area S may be reduced or the electrode interval d may be increased.

[0011]

However, in a ferroelectric material, its effective permittivity greatly changes due to polarization reversal or the like. An example is shown in FIG.

FIG. 18 shows the effective relative permittivity of the PZT film when an applied voltage is scanned within ± 20 [V] in an MFM capacitor having a lead zirconate titanate (hereinafter PZT) layer having a thickness of 500 nm. Is the result of measurement.
Generally, the relative permittivity of PZT is said to be about a little less than 1000, but it can be seen from FIG. 18 that this value shows a value near an applied voltage of 0 [V]. Further, it is understood that the effective relative permittivity has a maximum value at the voltage at which the polarization is most inverted, and the value at that time is an extremely high value of around 4000. The same trend is observed with other ferroelectric materials.

As described above, since the effective relative permittivity of a ferroelectric material greatly differs depending on the polarization state, it is unclear what value Cf should be set in the conventional semiconductor element designing method, and the performance is not clear. It has been extremely difficult to design a semiconductor device that is optimized.

It is a well known fact that the effective capacitance of the MIS capacitor changes due to depletion of the semiconductor layer. That is, MFMIS
In a semiconductor device of the conventional type, the capacitance of any capacitor is non-linear, and therefore, the coupling ratio was only an approximation by the simple calculation method used in the conventional semiconductor device design method.

Therefore, the conventional semiconductor element has not been configured to obtain a truly optimum operation by taking a large margin for preventing the gate insulating film from dielectric breakdown. In addition, little consideration has been given to the drive voltage for obtaining the optimum operation.

It is an object of the present invention to provide an MFMIS type semiconductor element having a device structure capable of obtaining an optimum operation by clarifying guidelines when designing a semiconductor device.

[0017]

The semiconductor device of the present invention comprises:
A control voltage supply unit, a substrate, a gate electrode provided above the substrate, a gate insulating film made of an insulator provided between the gate electrode and the substrate, and a gate electrode of the gate electrode in the substrate. A field effect transistor having source / drain regions formed on both sides, and interposed between the control voltage supply section and the gate electrode, and between the upper electrode, the lower electrode, and the upper electrode-lower electrode. A semiconductor element having a ferroelectric capacitor made of a sandwiched ferroelectric film and capable of holding information, wherein a driving voltage is V _OP [V] and a thickness of the gate insulating film is t _I [m ], When the designed maximum electric field strength of the gate insulating film is E _{I (MAX)} [V / m],
The absolute value | V _{F (MAX)} | of the maximum value of the distribution voltage V _F applied to the ferroelectric capacitor at the time of driving is V _OP − (t _I × E
_{I (MAX)} ) ≤ │V _{F (MAX)} │ ≤ V _OP- (t _I × E _{I (MAX)} ) +
The voltage value is in the range calculated by 0.5.

As a result, the driving voltage V is constant.
_{In the case of OP} [V], the semiconductor element can be driven without causing dielectric breakdown of the gate insulating film, taking into consideration variations in the element that occur during manufacturing.

The substrate, the gate insulating film and the gate
The area of the MIS capacitor composed of electrodes is S_I[Μm²],
The area of the ferroelectric capacitor is S_F[Μm²], Above M
Area ratio R of the IS capacitor and the ferroelectric capacitor
_SR_S= S_I/ S_FThen the remanent polarization of the ferroelectric film
Pr [μC / cm²] And the above area ratio R_SRatio of Pr / R _S
Is 1 [μC / cm²] By the above, it is applied
A large drain current can be obtained with respect to the driving voltage. So
Therefore, for example, switches for switching logic circuits and neurons
It can be preferably used as an element.

Further, the field effect transistor and the gate
The same configuration except for the width and the current driving force are the same
Assuming the field effect transistor of
Increase the gate width dimension of the gate electrode of the fruit type transistor.
Dimension W in the gate width direction of the field effect transistor
_FW smaller than [μm]_MOSWhen [μm] is set,
Width expansion ratio R_WR_W= W_F/ W_MOS, Remaining of the above ferroelectric film
Retained polarization is Pr [μC / cm ²], The above area ratio R_SR_S=
S_I/ S_F, Β = Pr / R_SThen, (0.25β-
0.6) ≦ 1 / R_WRelationship of ≦ (0.25β−0.25)
Is established.

As a result, since the gate width is expanded, a drain current of the same magnitude as when using the field effect transistor alone can be obtained, and the remanent polarization Pr is obtained.
The area ratio between the ferroelectric capacitor and the field effect transistor is optimized in consideration of the above.

The maximum design electric field strength is E
_{I (MAX)} [V / m], the gate maximum polarization of P _MAX of the electric field of the specified maximum field strength in the insulating film is induced in the ferroelectric film when such [[mu] C / cm ^2], the vacuum dielectric Rate ε
_O [F / m], where ε _I is the relative permittivity of the ferroelectric film, the relationship of R _S = P _MAX / (ε _O · ε _I · E _{I (MAX)} ) holds Since the polarization Pr / maximum polarization P _MAX is designed to be the largest, almost the maximum drain current can be obtained in the holding state.

[0023]

BEST MODE FOR CARRYING OUT THE INVENTION-Structure of Semiconductor Element- A semiconductor element according to an embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a diagram showing a top view of the semiconductor device of this embodiment. 2 is a cross-sectional view taken along line III-III of the semiconductor device of this embodiment shown in FIG.
FIG. 4 is a sectional view taken along line IV-IV of the semiconductor device of this embodiment shown in FIG. 1.

In FIG. 1, in order to make the diagram easy to see,
Only the topmost components are shown in solid lines. Furthermore, FIG.
Portions that are the same as those in FIG. 3 are omitted for clarity. In addition, in FIGS. 2 and 3, some of the components located at the back of the cross section shown in the drawings are omitted in order to make the drawings easy to see.

As shown in FIGS. 1, 2 and 3, the semiconductor device according to the present embodiment is, for example, a P-type S having an active region.
an i substrate 1, a substrate electrode 8 (not shown) provided on a surface of the Si substrate 1 facing the active region, an element isolation oxide film 5 surrounding the active region provided on the Si substrate 1, A gate insulating film 7 made of SiO ₂ and having a thickness of 3 nm provided on the Si substrate 1, a gate electrode 9 made of polysilicon containing phosphorus provided on the gate insulating film 7, and the Si substrate 1
A drain region 3a and a source region 3b containing N-type impurities provided on both sides of the gate electrode 9, and a first interlayer insulating film 11 made of an insulator such as SiO ₂ provided on the Si substrate 1. , A titanium nitride (TiN) film having a thickness of 20 nm provided on the first interlayer insulating film 11 and a thickness of 50
pad portions 15a and 15b made of a Pt film of 15 nm and the intermediate electrode 14, a plug wiring 13a made of polysilicon for penetrating the first interlayer insulating film 11 and connecting the gate electrode 9 and the intermediate electrode 14, The drain region 3a, the pad portion 15a, and the source region 3b are penetrated through the first interlayer insulating film 11.
From the plug wirings 13b and 13c made of polysilicon for connecting the pad portion 15b and the pad portion 15b, respectively, and 400 nm thick strontium bismuth tantalate (hereinafter referred to as SBT) provided on the first interlayer insulating film 11. A ferroelectric film 16 made of Pt, an upper electrode 19 made of Pt having a thickness of 50 nm provided on the ferroelectric film 16, and a second interlayer insulating film 21 provided on the ferroelectric film 16. , Al that penetrates the second interlayer insulating film 21 and reaches the upper electrode 19
Wiring 25a made of a conductor such as a SiCu alloy, and wirings 25b and 25c made of a conductor such as an AlSiCu alloy penetrating the ferroelectric film 16 and the second interlayer insulating film 21 to reach the pad portions 15a and 15b, respectively. have.

FIG. 5 is an equivalent circuit diagram showing the semiconductor element of this embodiment. As can be seen from the figure, the semiconductor device of this embodiment has a control voltage supply unit 10, a gate electrode 9, a drain region 3a, a source region 3b, and a thickness of 3.
nm MOS transistor Tr having a gate insulating film 7
1, an intermediate electrode 14 and an upper electrode 1 provided between the gate electrode 9 of the MOS transistor and the control voltage supply unit 10.
9 and a capacitor MFM1 having a ferroelectric film 16.

The sizes of the intermediate electrode 14 and the upper electrode 19 are both 0.14 μm × 0.14 μm, the gate length of the gate electrode 9 is 0.14 μm, and the gate width is 0.7 μm.
Is. That is, the area of the capacitor MFM1 is MO
It is one fifth of the area of the gate insulating film 7 of the S transistor Tr1.

According to the semiconductor device of this embodiment, as will be described later in detail, the ferroelectric film 16 having a thickness of 400 nm is used.
When SBT is used as the material of the gate insulating film and SiO ₂ is used as the material of the gate insulating film having a thickness of 3 nm, the polarization of the ferroelectric film 16 is taken into consideration and the capacitor MFM1 and the MOS transistor T
Since the area ratio of r1 to the gate insulating film is optimized,
During operation, the largest holding drain current can be obtained within the breakdown voltage range of the gate insulating film 7. —Method for Manufacturing Semiconductor Element— Next, a method for manufacturing the semiconductor element according to the present embodiment will be described with reference to the drawings.

FIG. 4 is a sectional view taken along line IV-IV in FIG. 1 showing the manufacturing process of the semiconductor device of this embodiment. In addition, about the member which is not shown in FIG. 4, it demonstrates using the code | symbol used in description of FIGS.

First, in the step shown in FIG. 4A, a P-type S
Oxidation of the substrate is performed by using the silicon nitride film (not shown) formed on the i-substrate 1 as a mask to form the element isolation oxide film 5.
Are formed (LOCOS method). Next, the silicon nitride film is removed by using heated phosphoric acid or the like, and then the substrate is heated to 900 ° C.
Then, a SiO ₂ film having a thickness of 3 nm is formed on the Si substrate 1 by pyrooxidation. After that, polysilicon into which an n-type impurity such as phosphorus is introduced is deposited on the SiO ₂ film by the LPCVD method or the like, and then patterned by dry etching to form the gate insulating film 7 and the gate electrode 9.

Then, a p-type impurity such as boron is implanted using the gate electrode 9 as a mask and a heat treatment is performed at 900 ° C. for 30 minutes, whereby the drain region 3a and the drain region 3a are formed on both sides of the gate electrode 9 in the Si substrate 1. The source region 3b is formed. The MOS transistor manufactured by this process has a gate length of 0.14 μm and a gate width of 0.7 μm.
m.

Next, in the step shown in FIG. 4B, SiO ₂ is deposited on the substrate by, for example, the LPCVD method to form the first layer.
The inter-layer insulating film 11 is formed. After that, a resist mask pattern (not shown) is formed on the first interlayer insulating film 11, and the first interlayer insulating film 11 is dry-etched to reach the gate electrode 9, the drain region 3a and the source region 3b. Form contact windows respectively. Then, after depositing polysilicon on the substrate by the LPCVD method or the like, the surface of the substrate is flattened by the CMP method to form plug wirings 13a, 13b, 13c for filling the contact windows, respectively. Next, after depositing 20 nm of TiN on the first interlayer insulating film 11 by the sputtering method, 50 nm of Pt is similarly deposited by the sputtering method. Subsequently, using a hard mask (not shown) formed by patterning the SiO ₂ film deposited by the sputtering method, Pt / TiN
Is patterned by Ar milling to form plug wiring 13
The intermediate electrode 14 is formed on a, the pad portion 15a is formed on the plug wiring 13b, and 15b is formed on the plug wiring 13c. After that, the hard mask is removed with diluted hydrofluoric acid or the like.

Here, the TiN layer is formed to prevent Pt and polycrystalline silicon from forming a silicide and increasing resistance.

Next, in the step shown in FIG. 4C, SBT is deposited on the first interlayer insulating film 11 by the sputtering method under the conditions of a substrate temperature of 600 ° C., an oxygen partial pressure of 20%, and an RF power of 100 W. Then, the ferroelectric film 16 having a thickness of 400 nm is formed.
Then, after depositing Pt on the dielectric layer 16 by the sputtering method, the Pt layer is patterned by Ar milling using a hard mask made of SiO _{2 (} not shown), and the intermediate electrode 14 is sandwiched with the ferroelectric film 16 in between. The upper electrode 19 is formed at a position opposed to. After that, the hard mask is removed with diluted hydrofluoric acid or the like.

In this embodiment, the dimensions of the intermediate electrode 14 and the upper electrode 19 are both 0.14 μm, and the area of the capacitor MFM1 is 5 minutes of the area of the gate insulating film 7 (or gate electrode 9) of the MOS transistor. It is set to 1.

Next, in the step shown in FIG.
After depositing SiO ₂ by plasma CVD using (tetraethoxysilane), the second interlayer insulating film 21 is formed by planarizing by the CMP method. After that, the contact window is formed by dry etching the second interlayer insulating film 21 and the ferroelectric film 16 using the resist mask. Then, AlSiCu is formed by the sputtering method.
After depositing the alloy on the substrate, dry etching is performed using a resist mask to form the wiring 25a from the second interlayer insulating film 21 to the upper electrode 19, the wiring 25b to the pad portion 15a, and the wiring to the pad portion 15b. 25c are formed respectively. The wiring 25a is connected to the control voltage supply unit 10 (not shown). The semiconductor element of this embodiment is manufactured by the above method. -Consideration on Design Method of Semiconductor Element- Next, a clear design guideline for obtaining the optimum operation of the semiconductor element will be considered below.

As shown in FIG. 5, the semiconductor device of this embodiment is represented by an equivalent circuit in which the gate electrode 9 of the MOS transistor Tr1 is connected to the capacitor MFM1 having a ferroelectric film.

On the other hand, as can be seen from FIGS. 2 and 3, in the semiconductor device of this embodiment, the MIS capacitor defined by the gate insulating film 7 and the Si substrate 1 and the gate electrode 9 sandwiching the gate insulating film 7 are provided. Is a capacitor MIS
It can also be considered that 1 has a structure in which the capacitor MFM1 and the capacitor MFM1 are connected in series. Here, in the semiconductor element of the present embodiment, the material of the gate insulating film is SiO 2.
_Since an insulator other than ₂ may be used, in the following examination, a structure similar to that of the present embodiment, that is, a capacitor MFM and a MIS transistor Tr (that is, a capacitor MIS) that are connected in series to the voltage supply unit are provided. An MFMIS type semiconductor device having a structure will be described.

First, in considering the operation of the above-mentioned MFMIS type semiconductor element, in particular, the capacitance of the MIS capacitor (capacitor MIS) is the capacitance of the capacitor M.
As important as FM capacity.

FIG. 6 shows the MFM and the capacitor MFM in more detail in order to explain the sizes thereof.
FIG. 6 is a projection view of a MIS transistor Tr of the IS type semiconductor device when viewed from above.

The area S _I of this capacitor MIS is shown in FIG.
Therefore, if the gate length is L and the gate width is W, then S _I = L ×
W. On the other hand, the area of the capacitor MFM is defined by the size of the overlapping portion of the intermediate electrode and the upper electrode, and here, the sizes of the intermediate electrode and the upper electrode are equal to each other. Therefore, assuming that the vertical dimension a and the horizontal dimension b of the intermediate electrode and the upper electrode are the capacitor MFM.
The area S _{F of} is _calculated by S _F = a × b.

In the semiconductor element of this embodiment, the dimensions of each member are, for example, a gate length L = 0.14 μm, a gate width W = 0.7 μm, and a vertical dimension a of the capacitor MFM.
= 0.14 μm, lateral dimension b of capacitor MFM =
It is 0.14 μm.

Here, the area S _I of the capacitor MIS is
The area ratio R _S between the area S _F and the area S _{F of the} capacitor MFM is defined by the following equation (1).

R _S = S _I / S _F (1) For example, in the semiconductor device of this embodiment, the area ratio R _S =
(0.14 μm × 0.7 μm) / (0.14 μm × 0.
14 μm) = 5.

FIG. 7 is a diagram showing the voltage-polarization characteristic (P-V characteristic) of only the capacitor MFM used in the MFMIS type semiconductor element. Here, the horizontal axis of FIG. 7 represents the voltage applied to the capacitor MFM.

[0047] Incidentally, a maximum polarization value in the scan range of P _MAX is the applied voltage shown in FIG. 7, hereinafter, the maximum polarization P _MAX
It is written as. Similarly, Pr is the polarization value remaining when the voltage is unloaded, and will be referred to as remanent polarization Pr hereinafter. The change in the polarization value draws a counterclockwise hysteresis, and in the capacitor MFM of the present embodiment, the coercive voltage is about 1.5.
[V] and remanent polarization have a characteristic of about 8 [μC / cm ² ]. Here, the coercive voltage is a voltage required to change the polarization state of the majority of the dipoles of the ferroelectric capacitor, and this value changes depending on the type and crystallinity of the ferroelectric material.

FIG. 8 is a diagram showing the correlation between the drive voltage and the drain current when the area ratio of the capacitor MIS and the capacitor MFM is changed in the MFMIS type semiconductor element. Here, the conditions other than the area ratio Rs, such as the thickness of the ferroelectric film, are the same for each measured semiconductor element.

In the semiconductor device of this embodiment, the drain current I _D is controlled by the voltage V _G applied from the voltage supply section. Hereinafter, the voltage applied from the voltage supply unit will be simply referred to as a drive voltage. In the present embodiment, V _G is scanned between −5.4 [V] and 5.4 [V]. The drain - source voltage (V _{D S)}
Is measured as 1.8 [V].

[0050] In Figure 8, the area ratio R _S is shows the V _G -I _D characteristic for each case 3, 5, 10, the above P-V
A counterclockwise hysteresis as well as a characteristic was observed.
Further, from the same figure, it became clear that the smaller the area ratio R _{S, the} larger the drain current.

Although not shown in FIG. 8, in the case of R _S = 1, the gate insulating film is broken down before V _G is scanned to +5.4 [V], and the proper operation as an element is performed. I couldn't get it.

These phenomena can be explained as follows.

The distribution voltage V _F to the capacitor MFM and the distribution voltage V _I to the capacitor MIS when the drive voltage V _G is applied are calculated from the relationship of the voltage distribution of the series capacitors.
It is expressed as the following equations (2) and (3).

V _F = V _G × {C _I / (C _F + C _I )} (2) V _I = V _G × {C _F / (C _F + C _I )} (3) In the above equation, C _F and C _I are the capacitances of the capacitor MFM and the capacitor MIS, respectively. In the conventional semiconductor element design method, these capacitances are regarded as constants, but here they are treated as variables that change depending on the electric field strength, the application history thereof, and the like.

From the definition equation of capacitance, the capacitances C _F and C _I of the capacitor MFM and the capacitor MIS are respectively expressed by the following equations.

[0056]   C_F= (Ε_O・ Ε_F・ S_F) / T_F                                    (4)   C_I= (Ε_O・ Ε_I・ S_I) / T_I                                    (5) In the above equation, ε_F, Ε_IAre the capacitor MFM and the capacitor respectively.
It is the effective relative permittivity of the Pasita MIS. These are constants
Distribution voltage applied to each capacitor and voltage change speed
Degree, then ε_FChanges with the history of applied voltage, etc.
Variable. Also, ε_OIs the dielectric constant of the vacuum,
854 x 10^-12[F / m]. S_F, S _IAre each
The area of the capacitor MFM and the area of the capacitor MIS.
, T_F, t_IAre the ferroelectric film thickness and gate insulation, respectively
The film thickness of the film.

The following relationships are derived by using the relationships of the expressions (1) to (5).

V _F = V _G / {(ε _F · t _I ) / (ε _I · t _F · R _S ) +1} (6) V _I = V _G / {(ε _I · t _F · R _S ) / (Ε _F · t _I ) +1} (7) When R _S is made small, the denominator of the formula (6) becomes large, so the distribution voltage V _F to the capacitor MFM becomes small, and the denominator of the formula (7) becomes small. Therefore, it is understood that the distribution voltage V _I to the capacitor MIS becomes large. That is,
When R _S becomes small, the distribution voltage to V _I increases, and the gate insulating film easily breaks down.

On the other hand, when the MFMIS type semiconductor device of the present embodiment is used as a memory device, the stable polarization information of the ferroelectric film has the highest priority, and the polarization of the capacitor MFM becomes saturated polarization. Closer is desirable. In this case, it is desirable that V _F be as large as possible, and from Expression (6), increasing R _S is an effective method.

Further, the semiconductor device of this embodiment is used as a non-volatile switch for switching logic circuits in an FPGA (Field).
A drain current at the time of ON is large, that is, a MIS transistor when used as a variable resistance element such as a programmable gate array) or a neuron element used in a neuron computer. It is desirable that the on resistance of (a MOS transistor in the semiconductor device of this embodiment) is small. Regarding the on-resistance of the MFMIS type semiconductor element, the interpretation differs slightly depending on the method of holding and reading information.
Here, V _{G is set} to 0 as shown as the holding point in FIG.
[V], that is, the grounded state is the holding state.

With respect to the element structure for reducing the on-resistance of the MFMIS type semiconductor element (that is, increasing the drain current with respect to the driving voltage), there has been no report of a clear guideline. Although the formulas of the distribution voltage to the capacitor MFM and the capacitor MIS have been shown above, the parameters appearing in these formulas, especially ε _F , continue to change depending on the voltage application history, the voltage change speed, and the voltage value at that time. Therefore, the calculation is extremely difficult to handle.
Further, even if a method for calculating each distribution voltage is established, the drain current at the holding point is affected by an ambiguous component such as “easiness of residual polarization” in addition to the voltage distribution amount. Moreover, since no means has been proposed to roughly estimate the effect of the residual polarization amount, it cannot be estimated simply by increasing the distribution voltage to the capacitor MIS. Therefore, in extreme cases, MF
In many cases, the characteristics of the MIS type semiconductor device are not revealed until the device is actually manufactured and measured.

The complexity of such an operation mechanism is a great hurdle for realizing an MFMIS device having a good performance, and at present, even a guideline for designing an element has not been proposed.

Therefore, in order to clarify the guideline necessary for designing the MFMIS type semiconductor element, further study will be made below.

FIG. 9 shows an MF having different ferroelectric films.
FIG. 6 is a diagram showing a relationship between an area ratio R _S at a holding point and a drain current in a MIS type semiconductor element. The structure of the semiconductor element other than the ferroelectric film measured here is the same as that of the semiconductor device of this embodiment, and the voltage at the holding point is 0 [V] as in the measurement shown in FIG. As the material of the ferroelectric film, three types of lead lanthanum titanate (hereinafter referred to as PLT), SBT, and bismuth titanate (hereinafter referred to as BIT) were used.

FIG. 10 is a diagram showing the P-V characteristic of the capacitor having the PLT layer, and FIG. 11 is a diagram showing the P-V characteristic of the capacitor having the BIT layer. In these measurements, the capacitor with the PLT layer has a coercive voltage of 2.3.
The remanent polarization was about 20 [mu] C / cm < ² > at about [V], and the capacitor having the BIT layer exhibited a hysteresis characteristic with a coercive voltage of about 2.0 [V] and a remanent polarization of about 3 [mu] C / cm < ² >.

From FIG. 9, all three types of semiconductor elements are
It can be seen that the drain current at the holding point decreases as the area ratio R _S increases. This can be explained as follows.

When the area ratio R _S is increased, the capacitor M
The distribution voltage V _F to the FM increases and the polarization of the ferroelectric film approaches saturation. On the other hand, the distribution voltage V to the capacitor MIS
_{Since I} becomes smaller, the degree of modulation of the distribution voltage V _I when the drive voltage V _G is changed becomes smaller, and as a result, the distribution voltage V _I at the holding point also becomes smaller, and the drain electrode flows enough to drain the intermediate electrode. The electric potential stops rising. For this reason,
The drain current becomes smaller.

Further, looking at the difference between the semiconductor elements having the respective ferroelectric materials in FIG. 9, it can be seen that the drain current can be obtained with a smaller R _S for the semiconductor element using the material having a smaller remanent polarization. For example, the drain current per unit gate width (hereinafter referred to as I _D / W) is 200 [μA / μm]
The area ratio R _{S at which}
, R _S = 2, SBT R _S = 4, PLT R _S = 1
It is 3.

This is because the material having a larger remanent polarization has a tendency that the effective relative permittivity ε _F is relatively high irrespective of the conditions such as voltage. Therefore, the denominator in Equation 6 becomes large and V _F becomes large.
Is smaller.

However, the maximum drain current values at R _S (that is, R _S just before the dielectric breakdown of the gate insulating film) at which the largest drain current is obtained are, as shown in FIG. 9, PLT, BIT, and SBT in descending order. The present inventors found that the order of the remanent polarization was not the order of the remanent polarization. This means that it is M
The results are quite different from the vague conventional understanding that they are advantageous for FMIS operation.

The guidelines found by the present inventors regarding the ease of securing such a drain current will be described below.

At the holding point, the remanent polarization of the ferroelectric substance causes
Q is the amount of charge induced in the intermediate electrode. _HThen the substrate
Capacitor MIS (yes
Or the voltage V applied to the MIS transistor Tr)_IHIs
It can be expressed by the following formula.

V _IH = Q _H / C _I (8) When the size of the MIS transistor Tr (that is, the size of the capacitor MIS) is determined from the above equation (8), C _I is within the range according to the distribution voltage. Although it changes,
It is understood that it is the value of Q _{H that} dominates V _IH .

FIG. 12 shows a case where the maximum drain current is obtained in the MFMIS type semiconductor element having the same structure as the semiconductor element of the present embodiment and having the ferroelectric film made of SBT, BIT and PLT, respectively. Capacitor M
It is a figure which shows the correlation of the distribution voltage to IS, and the electric charge amount induced by the intermediate electrode. The figure also shows R _S when the maximum I _D was obtained.

It can be seen from FIG. 12 that the maximum V _F values are almost the same, but this is because V _I is defined by the dielectric breakdown voltage of the MIS portion. For example, in the case of the semiconductor element studied here, the maximum voltage that can be applied to the gate insulating film is set to 1.8 [V] in consideration of some safety factor. That is, since the thickness of the gate insulating film is 3 nm, the maximum electric field strength E _ox to the gate insulating film is 6 [MV /
cm].

In this measurement, a maximum of 5.4 [V] is applied to the semiconductor element as V _G , but the maximum value of V _I is 1.8.
Since it is [V], the distribution voltage V _F to the ferroelectric film shown in FIG. 12 has a maximum value of about 3.6 [V].

Further, from FIG. 12, when the distribution voltage V _F to the ferroelectric film is around 0 [V], the intermediate electrode induced charge amount is
It can be seen that the order is PLT, BIT, and SBT in descending order. This is the same as the order of the magnitude of the maximum drain current value shown in FIG. 9, and the amount of the induced charge to the intermediate electrode determines the magnitude of the drain current as described in equation (8). It is confirmed that they have strong control.

Here, when the polarization value of the ferroelectric film at the holding point is P _H , the following equation holds.

Q _H = P _H × S _F (9) Here, from the formula (1), the area S _{F of the} capacitor MFM is
S _F = S _I / R _S and M as described in the description of FIG.
Area S _{I of} IS transistor Tr (capacitor MIS)
Since S _I = L · W, equation (9) can be modified as follows.

Q _H = P _H × (L · W / R _S ) (10) Here, when the on-resistance performance index α is defined as α = P _H / R _S , Q _H = α · (L · W) ( 11) According to the above equation (11), if the size of the field-effect transistor is constant, there is a correlation that the amount of charge Q _H induced in the intermediate electrode at the holding point is proportional to the on-resistance performance index α. I understand. Further, from the equation (8), the voltage V _IH applied to the capacitor MIS at the holding point in the state where the substrate is grounded is also proportional to the on-resistance performance index α.

FIG. 13 is a diagram showing the relationship between the polarization / R _S and the voltage distributed to the capacitor MFM in each of the same MFMIS type semiconductor elements measured in FIG.
In the figure, the horizontal axis represents the ferroelectric film (or the capacitor MF).
The distribution voltage to M) and the vertical axis are values (P / R _S ) obtained by dividing the polarization of the ferroelectric substance by R _S. From the figure, the P / R _S values when V _F is around 0 [V] are PL
T, BIT, and SBT, which are the same as the order in which the maximum drain current value is large.

Strictly speaking, when the drive voltage V _G applied to these MFMIS type semiconductor elements is set to 0 [V], V _F does not become 0 [V] and is expressed by the equation (8). The negative voltage is applied by the amount of the voltage.

In FIG. 13, the voltage range that can be taken at the holding point is shown as the holding point region, but whatever value R _S takes, the voltage distributed to the ferroelectric film is within this range. Fits in. This is because if the negative voltage is too large, the dielectric breakdown strength of the gate insulating film will be exceeded, and since the hysteresis is counterclockwise, it will not exceed 0 [V]. The above-mentioned holding point region is the M used in this study.
In the FMIS type semiconductor element, the area is larger than -1.8 [V] and smaller than 0 [V]. However, since the value of V _F at the time of holding varies depending on the shape of the hysteresis of the ferroelectric material, the area ratio R _{S, and the} like, it is impossible to calculate this value in advance.

[0084] On the other hand, paying attention to FIG. 13 again, in the voltage range V _F can take, and P / R _S value at V _F = 0 [V],
For example, it is understood that the relative relationship with the P / _RS value at V _F = -1.8 [V] shows almost the same tendency although the value changes between the respective materials.

However, assuming that the coercive voltage is V _C , at the time of holding, unless the value of V _{F is in} the range of −V _C <V _F <0, the polarization value becomes 0 and the potential cannot be held. For this reason,
If it has a hysteresis characteristic as shown in Fig. 3, V _F
Is preferably about -1 [V].

From the above examination, the residual polarization value of the ferroelectric capacitor alone is Pr, and the quasi-on resistance performance index β is β.
= Pr / R _S , β is almost the same as α
It can be said that the MIS type semiconductor element is extremely useful as a guideline for showing a low on-state resistance during holding. The remnant polarization value Pr is
Since the value can be measured by the hysteresis of the ferroelectric capacitor, it is possible to design a semiconductor element having a small ON resistance during holding.

FIG. 14 shows the quasi-ON resistance figure of merit β and MFM.
It is a figure which shows the correlation with the characteristic of an IS type semiconductor element. Since the MIS transistor Tr of the MFMIS type semiconductor element used here is connected to the capacitor MFM, the drain current obtained becomes smaller than that obtained when it is driven alone. Therefore, in order to obtain a drain current equivalent to that when the MIS transistor Tr is driven alone, it is necessary to increase the gate width. At that time, assuming a single MIS transistor having the same structure as the MIS transistor Tr except for the gate width, when enlarging the gate width W _F of the MIS transistor Tr so that the current driving force becomes equal to this transistor, defining the _{R W (= W F / Wmos} ) as one of the design parameters for many times the gate width Wmos of a single MIS transistor. Note that the current driving force here means the magnitude of the drain current with respect to the voltage applied to the gate electrode.

In FIG. 14, the horizontal axis represents the quasi-ON resistance performance index β.
The vertical axis is the reciprocal of R _W. From the figure, W _F as R _W approaches 1 approaches Wmos, the area occupied by the MFMIS cell decreases, the area occupied by the cell in the reverse as R _W increases increases.

It should be noted that in FIG. 14, for each of the three types of ferroelectric materials shown in FIG.
All the measurement results of the semiconductor device including the capacitor MFM having the −V characteristic are plotted. Here, for example, the residual polarization is reduced by lowering the film formation temperature of the ferroelectric film, or conversely, the crystallinity is improved by heat treatment in an oxygen atmosphere of, for example, 700 ° C. after the film formation, and the maximum polarization P By changing the film forming conditions of the ferroelectric film and the heat treatment method such as reducing the difference between _MAX and the remanent polarization Pr, a large number of semiconductor devices having capacitors MFM having different PV characteristics were manufactured. .

[0090] The use of the on-resistance performance index α, 1 / R _W
It has been found that the correlation plot with and is almost completely on a straight line (not shown), but from FIG. 14, there is some variation even if the quasi-on resistance figure of merit β is used,
It can be seen that 1 / R _W and good correlation is observed. Also,
The higher the level on-resistance performance index beta 1 / R _W approaches 1 increases, also read the area favorable MFMIS type semiconductor device can be obtained. This is a very important finding, and the superiority or inferiority of the ferroelectric material in constructing the MFMIS type semiconductor element is not simply the P-V characteristic but the P-V characteristic.
It has been clarified that the judgment can be made by evaluating the / _RS- V characteristic.

[0091] Further, from the measurement results shown in FIG. 14, there to the value of the quasi on-resistance performance index beta, by setting the value of 1 / R _W in the range of the following equation, equivalent to the case of the MIS transistor alone The drain current can be obtained.

0.25β-0.6 ≦ 1 / R _W ≦ 0.25β−0.25 (12) This guideline is a very effective design guideline when considering the matching between the MFMIS type semiconductor element and its peripheral circuit. Is.

As described above, the larger the R _{W, the} MF
The gate width of the MIS type semiconductor element becomes large, which is disadvantageous in terms of the area occupied by the cell. Thus 1 / R _W is smaller disadvantageous. For example, less than 10 times the gate width of a single MIS transistor the gate width of the MFMIS semiconductor device, that is, 1 / R _W is to be a 0.1 or more, from 14 as a condition for satisfying this , At least the quasi-ON resistance performance index β is β = Pr / R _S ≧ 1 [μC
/ cm ² ], the conditions for forming the ferroelectric film are determined.

As described above, in obtaining the value of the quasi-ON resistance performance index β, it is extremely important to know the value of R _S (hereinafter referred to as R _SC ) at which the largest drain current is obtained. As a result of the study by the inventors, this R _SC is P of the capacitor MFM.
It has been clarified that the maximum polarization P _MAX obtained by −V measurement can be used. The examination procedure is shown below.

The maximum driving voltage of the MFMIS type semiconductor device having the same structure as the semiconductor device of this embodiment is V _OP ,
If the thickness of the gate insulating film is t _I [m], and the electric field strength that can be tolerated (allowable electric field strength) is E _{I (MAX)} [V / m] considering the safety factor of the gate insulating film, the gate insulation The applied voltage V _{I (MAX)} allowable for the film is expressed by the following equation.

V _{I (MAX)} = E _{I (MAX)} · t _I (13) At this time, the maximum voltage V _{F ( MAX)} distributed to the capacitor MFM when driving this element is expressed by the following equation. To be done.

V _{F (MAX)} = V _OP −V _{I (MAX)} (14) On the other hand, if the amount of charge induced in the intermediate electrode at the time of applying V _OP is Q _MAX , then this Q _MAX is V _{I (MAX)} , C _I ,
It has the following relationship with V _{F (MAX)} and C _F.

Q _MAX = V _{I (MAX)} · C _I = V _{F (MAX)} · C _F (15) On the other hand, the polarization P _MAX of the ferroelectric film at the time of applying V _OP is Q It has the following relationship with _MAX .

Q _MAX = P _MAX · S _F (16) The maximum polarization P _MAX when V _OP is applied is the polarization-voltage hysteresis characteristic of the capacitor MFM in the range of applied voltage ± V _{F (MAX).} Is a value obtained by actually measuring.

The above equations (13) to (16) and the equation (1)
And the relation with the equation (5) are summarized, the following relation is derived.

R _SC = P _MAX / (ε _O · ε _I · E _{I (MAX)} ) (17) By setting the electric field strength allowable in the gate insulating film by the formula (17), Using the relative permittivity ε _I , the optimum R _S , R _SC , can be determined very easily. It should be noted that the maximum polarization P _MAX in the equation (17) is obtained by using V _{F (MAX)} calculated using the equations (13) and (14) as described above, and the P-V hysteresis of the capacitor MFM is measured. This is the value obtained.

FIG. 15 shows an MFMIS type semiconductor device.
And the maximum electric field strength E applied to the element _{OX (MAX)}Each
Optimal area when 2, 4, 6, 8 [MV / cm]
Ratio R_SIt is the figure which showed this by having calculated | required the value of from Formula (17).
It Here, the maximum drive voltage V applied to this element_OPIs V_OP
= 5.4 [V], the gate insulating film material is SiO₂(Ε_I=
3.9), and the thickness of the gate insulating film was 3 nm.
In this case, the maximum distribution voltage V applied to the capacitor MFM
_{F (MAX)}Values of 4.8 and 4.
P of capacitor MFM as 2, 3.6, 3.0 [V]
By measuring -V, the characteristics of the capacitor MFM can be adjusted.
The optimum area ratio R_SCan be determined.

However, the actual MFMIS type semiconductor device
When manufacturing the
Depending on what, an error from the theoretical value occurs. Therefore, drive power
Pressure V _OPAnd the area ratio R mentioned above_SWhere to calculate
If there is an error, the capacitor M
Maximum distribution voltage V on FM_{F (MAX)}With a large
You may stay. Empirically, MFMIS as in this embodiment
In semiconductor type semiconductor devices_{F (MAX)}The maximum error is 0.
Since it is known to be about 5 [V], V_{F (MAX)}
The absolute value of {V_OP-(T_I× E_{I (MAX)})} Above {V_OP
-(T_I× E_{I (MA X)}) +0.5} or less
Good. After that, the optimum area ratio R_S
Can be determined.

[0104] According to this technique, a narrow area ratio it is possible to optimize the device in the range of R _S, the semiconductor device in comparison with which was difficult conventional conditions to narrow down the optimum value of the area ratio R _S It becomes possible to perform the structural design and device manufacturing of the above extremely efficiently.

In addition to the above procedure, the following procedure can be used to extract other information from the equation obtained in the above examination.

For example, from the viewpoint of device manufacturing workability, the value of R _S is set to a certain range, for example, 5, the maximum drive voltage V _OP of the device is 5.4 [V], and the gate insulating film material is SiO _2. In the case of (ε _I = 3.9), the thickness of the gate insulating film is 3 nm, and the maximum electric field strength E applied to the device is
_{OX (MAX)} is determined to be 6 [MV / cm]. At this time, the value of the maximum distribution voltage V _F (MAX) is calculated to be 3.6 [V]. Therefore, when the PV of the capacitor MFM is measured with the scan voltage of 3.6 [V], A suitable maximum polarization P _MAX is calculated as 10 [μC / cm ² ]. 7,
Referring to FIGS. 10 and 11, the ferroelectric material having the maximum polarization closest to this value is SBT. Therefore, it can be determined that the optimum ferroelectric material for driving the MFMIS type semiconductor element under this condition is, for example, SBT.

Further, as in the above example, when the value of R _S is limited to 5 and the degree of freedom of the drive voltage is recognized, the drive voltage can be determined. In this case, the value of P _MAX is calculated by the equation (17) from _{P MAX = R S · ε O} · ε I · E I (MAX). Subsequently, by performing a P-V measurement of the ferroelectric film, it can be a maximum polarization P _{MA X} determines the driving voltage V _F of the semiconductor element such that the same value was obtained by the above equation.

For example, when the gate insulating film material is SiO ₂ , the gate insulating film is set to 3 nm, the maximum electric field intensity E _{I (MAX)} applied to the gate insulating film is set to 6 [MV / cm], and R _S is set to 5, the maximum polarization P _MAX is 10.
It can be calculated as 4 [μC / cm ² ]. It can be judged that the material suitable for such characteristics is SBT, for example. Then S
By performing the P-V measurement of the capacitor having the BT film, the scan voltage V _{F at} which this maximum polarization P _MAX is obtained is found. Let this be the maximum distribution voltage V _{F (MAX),} and use the maximum allowable voltage V _{I (MAX) of the} gate insulating film calculated from E _{I (M AX)} to determine the maximum drive voltage V _OP of the MFMIS type semiconductor device as V
_It can be determined as _OP = VI _(MAX) + VF _(MAX) .

Not limited to these examples, equations (13) to (1
Of the design specifications such as the area ratio R _S , the element driving voltage V _OP , the maximum polarization P _MAX , the gate insulating film thickness t _I , and the relative dielectric constant ε _I of the gate insulating film material included in 7), Of 1
By fixing the design specifications other than the above, desired design specifications for obtaining a semiconductor element having excellent characteristics can be obtained.

On the other hand, as described earlier with reference to FIG. 13, the driving force of this element has a strong correlation with Pr / R _S. From this fact and the equation (17), it became clear that the larger the value of Pr / P _MAX of the ferroelectric material is, the higher the driving force of this element is.

FIG. 16 is a diagram showing the relationship between the applied voltage to the ferroelectric film and Pr / P _MAX when PLT is used as the material of the ferroelectric film in the present MFMIS type semiconductor device. Further, in the figure, the film thickness of the ferroelectric film is 200 n.
The influence when changing to m, 400 nm, and 800 nm is also shown. The data necessary for this figure can be obtained by changing the scan voltage and performing PV measurement of the ferroelectric capacitor.

From this FIG. 16, it was found that the larger the voltage applied to the ferroelectric film, the higher the value of Pr / P _MAX does not always become. That is, there is a point where the voltage applied to the ferroelectric substance is optimum, and even if a voltage higher than that is applied, the driving force of the present device is not improved, but is rather decreased. This is an extremely important finding from the viewpoint of not only simply lowering the driving voltage but also not wasting power when driving the device. further,
It was found that this optimum applied voltage has a correlation with the film thickness of the ferroelectric film, and shows a peak at a lower voltage as the film thickness of the ferroelectric film becomes thinner.

From the above findings, the distribution voltage to the ferroelectric film is such that the maximum value of Pr / P _MAX can be obtained for a certain thickness of the ferroelectric film and the voltage is as low as possible. I can decide. For example, the ferroelectric film is made of P with a thickness of 400 nm.
In the case of the LT film, a distribution voltage of about 4 [V] is a voltage at which the value of Pr / P _MAX can be stably set high on the low voltage side.

From the viewpoint of improving the efficiency of polarization of the ferroelectric substance, the design procedure for optimizing the present device will be described below.

As a gate insulating film material, SiO ₂ (ε _I =
3.9), the film thickness is 3 nm, E _{OX (MAX)} is 6
When determined as [MV / cm], the value of V _{I (MAX)} is 1.8.
[V] is calculated.

As described above, the thickness of the ferroelectric film is 40
When using 0 nm PLT, the optimum distribution voltage is about 4
[V].

That is, in this element, the drive voltage V
_By setting _OP to V _OP = 1.8 + 4.0 = 5.8 [V], a high driving force can be obtained with a small amount of electric power.

At this time, the optimum area ratio R _S is V
_It can be calculated according to the equation (17) by performing PV measurement with _{F (MAX) set} to 4 [V]. For example, in the semiconductor element of this embodiment, when PLT is used instead of SBT as the material of the ferroelectric film having a thickness of 400 nm, P _MAX is 2
Since the measured value is 2 [μC / cm ² ], the optimum R _S is 1
It becomes 0.6.

As described above, according to the semiconductor element designing method of this embodiment, the hysteresis of the ferroelectric film is measured, and the optimum value of the transistor Tr and the capacitor MFM is determined from the measured values of the maximum polarization P _MAX and the residual polarization Pr. It is possible to obtain a large area ratio R _SC . Furthermore, by making it possible to calculate the drain current from the transistor Tr at the time of holding, the transistor Tr and the capacitor M, which were very vague in the past, were
The accuracy of determining the area ratio with FM can be dramatically improved only by measuring the hysteresis of the ferroelectric capacitor.

Further, by using the method for designing a semiconductor element of this embodiment, a design guideline for an MFMIS type semiconductor element capable of obtaining as large a drain current as possible in a range where the gate insulating film does not cause dielectric breakdown is obtained. Therefore, the design efficiency of the device can be significantly improved. in addition,
This design method makes it possible to clarify optimum characteristics of the ferroelectric material and necessary evaluation items when designing the semiconductor device. That is, the semiconductor element designing method of the present embodiment is
It provides a very effective characterization criterion in the selection of the ferroelectric material or the film forming process.

Further, the semiconductor device of this embodiment has the capacitor MFM1 and the transistor T by the above-described design method.
This is an element in which the area ratio of r1 to the MIS capacitor portion and the PV characteristics of the ferroelectric film are combined under optimized conditions, and the highest holding drain current is obtained within the breakdown voltage range of the gate insulating film. Is designed to be Such a semiconductor element is used as a non-volatile switch for switching logic circuits in applications such as FPGA, and is expected to be used as a resistance variable element for realizing the synapse function of a neuron element in the future. There is.

The materials of the ferroelectric film of the semiconductor element of this embodiment are SBT, PLT, BIT given as examples.
Not limited to this, any ferroelectric substance having a polarization function can be used.

Further, the semiconductor element of this embodiment is compatible with both the maximum polarization magnitude and the drain current magnitude, and therefore can be used as a memory element having a large on / off difference during reading. .

The transistor used in the semiconductor device of this embodiment may be a field effect transistor having a structure in which the drain current is controlled by the gate electrode, in addition to the MOS transistor and the MIS transistor.

The material of the gate insulating film of the field effect transistor included in the semiconductor device of this embodiment is SiO _2.
However, it may be an insulator such as a silicon nitride film or a dielectric.

As the design procedure of the semiconductor device of this embodiment, the area ratio R _S or the maximum polarization is defined after the specifications such as the film thickness t _{I of} the gate insulating film and the relative dielectric constant ε _I of the gate insulating film material are defined. Although an example for obtaining the P _MAX Finally, for example, defines the area ratio R _S and the maximum polarization P _{MA X} above, be defined design conditions from another specification sequentially formula (12)
A semiconductor element can be easily designed by utilizing any one of (17) to (17).

Further, the mathematical formula described in this specification is MF
It is possible to deal with the case where the value changes due to the manufacturing conditions of the MIS type semiconductor element. For example, hydrogen generated in the process of forming TEOS when forming the second interlayer insulating film may change the ferroelectric characteristics. Even in this case,
By preparing a ferroelectric capacitor for evaluation having a structure similar to that of the present embodiment and evaluating the characteristics thereof, it is possible to optimize the element structure and the driving method in the same procedure as the design method of the present embodiment. As a result, the semiconductor element can be efficiently designed. That is, by using the concept of the present invention to design the optimum structure of the MFMIS type semiconductor device from the two characteristic values of the maximum polarization and the remanent polarization of the ferroelectric substance, the semiconductor element can be optimized even when the manufacturing conditions are changed. A semiconductor device having such a structure can be efficiently designed.

In this way, the semiconductor element efficiently designed by the method of the present embodiment has, for example, an excessively large design margin as compared with the conventional semiconductor element so as to prevent the gate insulating film from dielectric breakdown. Because there is no
The maximum driving force can be obtained under the set driving voltage.

[0129]

According to the semiconductor device of the present invention, when the residual polarization of the ferroelectric capacitor is Pr and the maximum polarization is P _MAX , the value of Pr / P _MAX becomes large and the field effect transistor Since the area ratio between the ferroelectric capacitor and the MIS capacitor portion of the field effect transistor is designed optimally so that the gate insulating film does not cause dielectric breakdown, the drain current with respect to the drive voltage can be increased.

[Brief description of drawings]

FIG. 1 is a top view of a semiconductor device according to an embodiment of the present invention.

FIG. 2 is a sectional view taken along the line III-III shown in FIG. 1 of the semiconductor device according to the embodiment of the present invention.

FIG. 3 is a cross-sectional view taken along line IV-IV shown in FIG. 1 of the semiconductor device according to the embodiment of the present invention.

4A to 4D are cross-sectional views showing a manufacturing process of a semiconductor device according to an embodiment of the present invention.

FIG. 5 is an equivalent circuit diagram showing a semiconductor device according to an embodiment of the present invention.

FIG. 6 is a projection view of the MIS transistor Tr and the capacitor MFM of the MFMIS type semiconductor element when viewed from above.

FIG. 7 is a diagram showing a voltage-polarization characteristic (P-V characteristic) of only a capacitor MFM used in an MFMIS type semiconductor device.

FIG. 8 is a diagram for explaining a correlation between a drive voltage and a drain current in an MFMIS type semiconductor element.

FIG. 9 is a diagram showing a relationship between an area ratio R _S at a holding point and a drain current in an MFMIS type semiconductor device provided with different ferroelectric films.

FIG. 10 is a diagram showing a P-V characteristic of a capacitor having a PLT layer.

FIG. 11 is a diagram showing a P-V characteristic of a capacitor having a BIT layer.

FIG. 12 is a diagram showing a correlation between a distribution voltage to a capacitor MIS and a charge amount induced in an intermediate electrode when a maximum drain current is obtained in an MFMIS type semiconductor device having various ferroelectric films. .

FIG. 13 is a diagram showing a relationship between polarization / R _S and a voltage distributed to a capacitor MFM in an MFMIS type semiconductor device having various ferroelectric films.

FIG. 14 is a diagram showing a correlation between a quasi-on resistance figure of merit β and characteristics of an MFMIS type semiconductor device.

FIG. 15 is a diagram showing an optimum area ratio R _S when the maximum applied electric field strength E _{OX (MAX)} is changed in the MFMIS type semiconductor device.

FIG. 16 is a diagram showing the relationship between the applied voltage to the ferroelectric film and Pr / P _MAX when PLT is used as the material of the ferroelectric film in the MFMIS type semiconductor device.

FIG. 17 is a cross-sectional view showing the structure of a conventional semiconductor device.

FIG. 18 is a graph showing the results of measuring the relative permittivity of a ferroelectric capacitor.

[Explanation of symbols]

1 Si substrate 3a drain region 3b Source area 5 Element isolation oxide film 7 Gate insulation film 9 Gate electrode 10 Control voltage supply unit 11 First interlayer insulating film 13a, 13b, 13c Plug wiring 14 Intermediate electrode 15a, 15b Pad part 16 Ferroelectric film 19 Upper electrode 21 Second interlayer insulating film 25a, 25b, 25c wiring

Continued front page    F-term (reference) 5F083 FR07 GA24 JA15 JA17 JA32                       JA35 JA36 JA37 JA38 JA40                       MA06 MA16 MA19 PR22 PR33                       PR36                 5F101 BA62 BB02 BD02 BF01 BH01                       BH03 BH09

Claims (4)

[Claims] 1. A control voltage supply unit, a substrate, a gate electrode provided above the substrate, a gate insulating film made of an insulator provided between the gate electrode and the substrate, and in the substrate. A field effect transistor having source / drain regions formed on both sides of the gate electrode, and an upper electrode, a lower electrode, and the upper electrode interposed between the control voltage supply unit and the gate electrode. A semiconductor element having a ferroelectric capacitor made of a ferroelectric film sandwiched between lower electrodes and capable of retaining information, wherein a driving voltage is V _OP [V], and the thickness of the gate insulating film is T _i
[M], the designed maximum electric field strength of the gate insulating film is E
_{When I (MAX)} [V / m], the absolute value | V _{F (MAX)} | of the maximum value of the distribution voltage V _F applied to the ferroelectric capacitor at the time of driving is V _OP − (t _I × E _{I (MAX)} ) ≦ | V _{F (MAX)} | ≦ V _OP − (t _I
A semiconductor element configured to have a voltage value within a range calculated by × E _{I (MAX)} ) +0.5. 2. The semiconductor device according to claim 1, wherein MIS comprising the substrate, gate insulating film and gate electrode
The area of the capacitor is S _I[Μm²], The above-mentioned ferroelectric capacity
Sita area is S_F[Μm²], Above the MIS capacitor
Area ratio R with ferroelectric capacitor_SR_S= S_I/ S_FWhen
Then, Remanent polarization Pr [μC / cm of the ferroelectric film]²] And above
Area ratio R_SRatio of Pr / R_SIs 1 [μC / cm²〕Above
A semiconductor device characterized by being present. 3. The semiconductor device according to claim 1, wherein the field effect transistor has the same configuration except the gate width, and the field driving transistor has the same current driving capability. When the dimension of the gate electrode of the field-effect transistor in the gate width direction is set to W _MOS [μm] smaller than the dimension of the field-effect transistor in the gate width direction W _F [μm], the gate width expansion ratio R _W is R _W = W _F / W _MOS , the remanent polarization of the ferroelectric film is Pr [μC / cm ² ], and the area ratio R _S is R
_S = _{S I} / _{S F,} when the _{β = Pr / R S, (} 0.25β-0.6) ≦ 1 / R W ≦ (0.25β-
A semiconductor device satisfying the relationship of (0.25). 4. The semiconductor element according to claim 1, wherein the designed maximum electric field strength is E _{I (MAX)} [V / m], and the set maximum electric field strength is applied to the gate insulating film. The maximum polarization induced in the ferroelectric film when an electric field of P _MAX [μC /
cm ² ], the dielectric constant of vacuum is ε _O [F / m], and the relative dielectric constant of the ferroelectric film is ε _I , R _S = P _MAX / (ε _O · ε _I · E _{I (MAX )} ) The relationship holds.