JP2003078010A - Semiconductor integrated circuit device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To increase layout flexibility of wiring on a fuse formation region of a semiconductor integrated circuit device and to reduce the surface area occupied by fuses and wiring. SOLUTION: Fuses F are formed by wiring of layers at the same level as or higher than signal wiring S, a guard ring G as a wall of a conductive laminated-layer film formed so as to surround the fuses F is formed therein with an opening OA to pass the signal wiring S therethrough. As a result, the layout flexibility of the signal wiring S can be increased. Further, the surface area occupied by the fuses F and signal wiring S can be reduced.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device, and more particularly to a technique effective when applied to a semiconductor integrated circuit device provided with a redundant circuit for repairing a defective memory cell by cutting a fuse.

[0002]

2. Description of the Related Art DRAM (Dynamic Random Access Memo)
ry) and a non-volatile memory (EEPROM: Electrically Erasable Programmable) that can be electrically written and erased.
A memory LSI such as a le read only memory) has a redundancy function for relieving a defect generated in a manufacturing process, thereby improving a manufacturing yield.

This is because a memory cell column or memory cell row (redundancy circuit) for redundancy relief is prepared in advance in the semiconductor integrated circuit device, and if a defective memory cell occurs in the memory array, such defect occurs. This is a defect relief function of performing a desired memory operation by inputting an address signal entering a memory cell to a redundancy relief memory cell column.

Switching between the defective memory cell and the memory cell for redundancy relief is performed by cutting a fuse connected to the address switching circuit. A current fusing method, a laser fusing method, or the like is used for blowing the fuse, but a laser fusing method is mainly used because it has a high degree of program freedom and is advantageous in terms of area efficiency.

[0005]

Such a fuse for defect relief is composed of a conductive film such as metal or polycrystalline silicon which constitutes a semiconductor element or wiring, and forms a memory cell or wiring, for example. It is formed during the process. Then, in the final step of forming these semiconductor elements and wirings forming the semiconductor integrated circuit, a so-called probe test is performed, and if a defective cell is found by this, the fuse is cut to remove the defective memory. An address corresponding to the cell is assigned to the redundant relief defective cell.

Here, in order to protect a circuit formed around the fuse, the fuse is surrounded by a guard ring every some number. The guard ring is a wall made of a laminated film of conductive films. This wall is a MISFET (Metal Insulator Semico) formed on a semiconductor substrate.
nductor Field Effect Transistor), etc.,
During the process of forming wires and plugs that connect wires,
It is formed by stacking conductive films constituting these.

On the other hand, a large number of wirings are formed on the semiconductor substrate to transmit signals necessary for driving the semiconductor integrated circuit.

However, since the above-mentioned fuse formation region is surrounded by the wall (guard ring) of the conductive film, the wiring is routed around the region, or the region surrounded by the guard ring is divided into small areas. It was necessary to pass wiring between the guard rings. As described above, the fuse forming region surrounded by the guard ring reduces the degree of freedom in wiring layout.

Further, when the area surrounded by the guard ring is divided into small parts, it is necessary to provide a certain amount of space between the fuse at the end and the guard ring, as will be described later in detail. Will increase.

An object of the present invention is to improve the degree of freedom in the layout of wiring on the fuse formation region of a semiconductor integrated circuit device.

Another object of the present invention is to reduce the area occupied by fuses and wirings in a semiconductor integrated circuit device.

The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0013]

Among the inventions disclosed in the present application, a brief description will be given to the outline of typical ones.
It is as follows.

The semiconductor integrated circuit device of the present invention comprises a plurality of semiconductor integrated circuit devices.
A wire extending in the first direction and extending from the second conductive film extends between fuses formed of the first conductive film extending in the first direction.

Further, the fuse is a wall made of a laminated film of conductive films and is surrounded by a wall having an opening, and the wiring is arranged so as to pass through the opening.

The conductive film forming this fuse is in the same layer as or above the conductive film forming the wiring.

A plurality of layers of wiring may be passed through the opening.

[0018]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described in detail below with reference to the drawings. Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiments, and the repetitive description thereof will be omitted.

FIG. 1 is a plan view of a main portion of a fuse forming region of a semiconductor integrated circuit device according to an embodiment of the present invention.

As shown in FIG. 1, the fuses F are arranged at regular intervals B in the X direction. This interval B corresponds to the diameter of the laser beam used when the fuse F is cut. As will be described later, this fuse is made of a conductive film such as polycrystalline silicon or metal forming a semiconductor element or wiring, and is formed during the process of forming the semiconductor element or wiring. The end of the fuse F is connected to the wiring M via the plug P.

The fuses F are surrounded by a guard ring G. The width of this guard ring G is A
And Further, an opening OP is formed in the center of each of the fuses F. This opening OP is a fuse F
A region where the insulating film covering the upper part is thin is shown. This is because if the insulating film covering the fuse is thick, the energy of the laser to be applied does not reach the fuse and the fuse cannot be cut, so the insulating film covering the fuse is etched to reduce its thickness. Is. As will be described later, the guard ring G is formed of a laminated film of conductive films such as polycrystalline silicon or metal forming semiconductor elements, wirings, plugs, etc., and has a wall shape. However, it has an opening OA as described later. In the present embodiment, since the same potential is supplied to the plurality of fuses F via the guard ring G, the fuses F and the guard ring G are connected.

Here, the distance between the end of the opening OP and the guard ring G is D. The distance between the end of the opening OP and the fuse F at the end is E. As described above, the fuse F at the end and the guard ring G need to be separated by a certain distance (D + E).

A signal wire S is formed between the plurality of fuses F. The signal wiring S also extends in the X direction. The distance between the signal wiring S and the fuse F adjacent thereto is B. The distance between the signal wirings S is C.

The signal wiring S passes through a region (opening) OA where the guard ring G is not formed. Also,
The conductive film forming the signal wiring S is in the same layer as or below the conductive film forming the fuse F.

Next, an example of the configuration of the fuse F, the guard ring G and the signal wiring S will be described. The left part of FIG. 2 shows a cross-sectional view of the DRAM memory cell formed in the memory cell formation region. Further, the central portion of FIG. 2 shows a cross-sectional view of the MISFET formed in the peripheral circuit formation region. The right part of FIG. 2 is
FIG. 2 is a cross-sectional view of a fuse formation region in the peripheral circuit formation region and corresponds to the A1-A1 cross section of FIG. 1.

As described above, the fuse and the guard ring are made of a conductive film such as polycrystalline silicon or metal that constitutes the semiconductor element or wiring, and are formed during the process of forming the semiconductor element or wiring. First, a process of forming a MISFET forming a DRAM memory cell and a peripheral circuit will be described with reference to the left part and the central part of FIG.

First, an element isolation groove is formed by etching a semiconductor substrate 1 made of p-type single crystal silicon having a specific resistance of, for example, about 1 to 10 Ωcm, and CVD (on the semiconductor substrate 1 including the inside of the groove is formed by CVD ( Chemical Vapor depos
ition) method to deposit a silicon oxide film, and the CMP (Chemical Mechanical Polishing) method is used to polish the silicon oxide film on the upper part of the groove to isolate the device 2.
To form.

Next, p-type impurities (boron) are ion-implanted into the semiconductor substrate 1, and then the impurities are diffused by heat treatment to form p-type wells 3 in the semiconductor substrate 1 in the memory cell formation region, and the periphery thereof. A p-type well 3 is formed in the semiconductor substrate 1 in the circuit formation region.

Next, the surface of the semiconductor substrate 1 (p-type well 3) is wet-cleaned and then thermally oxidized to form a gate oxide film 8.

Next, phosphorus (P) is formed on the gate oxide film 8.
Is deposited at a high concentration to deposit a low resistance polycrystalline silicon film, and then a WN (tungsten nitride) film and a W (tungsten) film are sequentially deposited on the low resistance polycrystalline silicon film, and a silicon nitride film 10 is further deposited on the WN (tungsten nitride) film. .

Next, the silicon nitride film 10 is dry-etched using a photoresist film (not shown) as a mask to leave the silicon nitride film 10 in the region where the gate electrode is to be formed. Is used as a mask to dry-etch the W film, the WN film, and the polycrystalline silicon film, so that the gate electrode 9 made of these films is formed in the memory cell formation region and the peripheral circuit formation region.
To form. The gate electrode 9 formed in the memory cell formation region functions as the word line WL.

Next, the p-type wells 3 on both sides of the gate electrode 9 are formed.
The n-type semiconductor region 13 is formed by implanting an n-type impurity (phosphorus) into.

Through the steps up to this point, a memory cell selecting MISFE configured in the memory cell forming region of an n-channel type is formed.
TQs are formed.

Next, after depositing the silicon nitride film 16 on the semiconductor substrate 1, the sidewall spacer SW is formed by anisotropically etching the silicon nitride film 16 in the peripheral circuit formation region.

Next, an n-type impurity (phosphorus or arsenic) is ion-implanted into the p-type well 3 in the peripheral circuit forming region to form the n ⁺ type semiconductor region 17 (source, drain).
To form.

Through the steps up to this point, L is formed in the peripheral circuit formation region.
An n-channel type MISFET Qn having a source and a drain having a DD (Lightly Doped Drain) structure is formed. The process of forming the p-channel type MISFETQp is different from that of the n-channel type MISFETQ except that the conductivity types of impurities are different.
The description is omitted because it is similar to the case of n.

Subsequently, after depositing the silicon oxide film 19 on the semiconductor substrate 1, the upper portion of the silicon oxide film 19 is subjected to C
The surface is flattened by polishing by the MP method.

Next, contact holes 20 and 21 are formed on the n-type semiconductor region 13 in the memory cell formation region,
The surface of the semiconductor substrate 1 (n-type semiconductor region 13) is exposed.

Next, an n-type impurity (phosphorus or arsenic) is ion-implanted into the p-type well 3 (n ⁻ type semiconductor region 13) in the memory cell formation region through the contact holes 20 and 21, thereby forming an n ⁺ type semiconductor region. Form 17.

Next, the plug 22 is formed inside the contact holes 20 and 21. For the plug 22, a low resistance polycrystalline silicon film doped with an n-type impurity such as phosphorus (P) is deposited on the silicon oxide film 19 including the insides of the contact holes 20 and 21 by a CVD method, and then this polycrystalline film is deposited. The silicon film is formed by etching back (or polishing by the CMP method) and leaving it only inside the contact holes 20 and 21.

Next, CVD is performed on the silicon oxide film 19.
After depositing the silicon oxide film 23 by a dry etching method, the silicon oxide film 23 in the peripheral circuit formation region and the silicon oxide film 19 thereunder are dry-etched by dry etching using a photoresist film (not shown) as a mask. A contact hole 2 is formed on the source and drain (n ⁺ type semiconductor region 17) of the n-channel type MISFET Qn.
4 is formed. In addition, the plug 22 in the memory cell formation region
A through hole 25 is formed on the upper part of.

Then, a W film is deposited on the silicon oxide film 23 including the insides of the contact hole 24 and the through hole 25 by the CVD method, and then the W film on the silicon oxide film 23 is polished by the CMP method. The plug 26 is formed by leaving this film only inside the contact hole 24 and the through hole 25. A thin WN film may be formed under the W film by the CVD method, and the plug 26 may be formed of two layers of the WN film and the W film.

Next, the bit line BL is formed on the plug 26 in the memory cell formation region, and the first layer wiring M1 is formed on the plug 26 in the peripheral circuit formation region. Bit line B
The L and the first layer wiring M1 are formed by, for example, depositing a W film on the silicon oxide film 23 including on the plug 26 and then dry etching the W film using the photoresist film as a mask. In addition, CVD is used as the lower layer of the W film
A thin WN film may be formed by the method, and the bit line BL and the first-layer wiring M1 may be composed of two layers of the WN film and the W film.

Next, the bit line BL and the first layer wiring M1
A silicon oxide film 34 is deposited on the upper part of the substrate by the CVD method.

Next, the silicon oxide film 34 in the memory cell formation region and the silicon oxide film 23 below it are dry-etched to form through holes 38. A low resistance polycrystalline silicon film doped with an n-type impurity such as phosphorus (P) is deposited on the silicon oxide film 34 including the inside of the through hole 38 by the CVD method, and then the polycrystalline silicon film is etched back. (Or polish by CMP method) and the plug 39 is formed in the through hole 38.

Next, a silicon nitride film 40 is deposited on the silicon oxide film 34, and then a silicon oxide film 41 is deposited on the silicon nitride film 40 by the CVD method. Then, silicon oxide in the memory cell formation region is formed. The film 42 and the silicon nitride film 40 are dry-etched to form a groove 42 on the plug 39.

Next, a low resistance polycrystalline silicon film doped with an n-type impurity such as phosphorus (P) is deposited on the upper part of the silicon oxide film 41 including the inside of the groove 42 by the CVD method.
A photoresist film or the like is embedded in the groove 42, and the polycrystalline silicon film on the silicon oxide film 41 is etched back to leave only the inner wall of the groove 42. As a result, the lower electrode 43 of the information storage capacitive element C is formed along the inner wall of the groove 42.

Next, a capacitor insulating film 44 made of a tantalum oxide film or the like and an upper electrode 45 made of a TiN film or the like are formed on the lower electrode 43. Through the steps up to this point, the DR including the memory cell selection MISFET Qs and the information storage capacitive element C connected in series to the DR
The AM memory cell is completed.

Then, a silicon oxide film 50 is deposited on the semiconductor substrate 1 by the CVD method to form the first peripheral circuit formation region.
The through holes 51 are formed by dry etching the silicon oxide films 50 and 41, the silicon nitride film 40, and the silicon oxide film 34 above the layer wiring M1.

Next, the plug 52 is formed inside the through hole 51. In this plug, after a W film is deposited on the silicon oxide film 50 including the inside of the through hole 51 by the CVD method, the W film on the silicon oxide film 50 is CMP-processed.
It is formed by polishing by a method. A thin WN film is formed under the W film by the CVD method to remove the WN film and the WN film.
The plug may be composed of two layers of the film.

Next, the second layer wiring M2 is formed on the plug 52 and the silicon oxide film 50. The second-layer wiring M2 is formed, for example, on the silicon oxide film 5 including on the plug 52.
After depositing an Al (aluminum) film on the upper part of 0, the Al film is formed by dry etching using the photoresist film as a mask.

Then, a silicon oxide film 53 is deposited on the second layer wiring M2 and the silicon oxide film 50, and the silicon oxide film 53 on the second layer wiring M2 is dry-etched to form the through holes 54. To form. Next, after depositing a W film on the silicon oxide film 53 including the inside of the through hole 54 by the CVD method, the W film on the silicon oxide film 53 is polished by the CMP method to form the plug 55.

Next, a third layer wiring M3 is formed on the plug 55 and the silicon oxide film 53. The third layer wiring M3 is formed similarly to the second layer wiring M2.

Next, a protective film 5 made of a laminated film of a silicon oxide film and a silicon nitride film is formed on the third layer wiring M3.
By forming 6, the DRAM of the present embodiment is almost completed.

In the manufacturing process of such a MISFET forming a DRAM memory cell and a peripheral circuit, for example, the fuse F is the third layer wiring M3 and the signal wiring S is the second wiring.
It can be formed by layer wiring. Also, guard ring G
To the plugs 26, 52, 55 and the wirings M1, M2, M
3 can be used. The structure of the fuse F and the guard ring G and the manufacturing method thereof in this case will be described with reference to the left part of FIG. 2, FIG. 3 and FIG.
The left part of this FIG. 3 shows the B1-B1 cross section of FIG. 1, the right part shows the C1-C1 cross section, and FIG. 4 shows D of FIG.
The 1-D1 cross section is shown.

As shown in the right part of FIG. 2, the guard ring G
Is the plugs 26, 52, 55 and the wirings M1, M2, M
3 is used. For example, the contact hole 24 in which the plug 26 is embedded is formed into a rectangular groove as shown in FIG. 5A, and the W film is embedded therein. The wiring M1 is also patterned into a rectangular shape as shown in FIG. A guard ring can be formed by stacking such rectangular patterns.
However, in the plugs 52 and 55 and the wiring M2, as shown in FIG. 5B, a region (opening OA) where no pattern is formed is provided. The size of the opening OA and the width of the pattern may be different in each layer.

As described above, by providing the opening OA in the wall of the conductive film forming the guard ring G, the signal wiring S composed of the second layer wiring can be arranged through the opening OA. Yes (see right part of FIG. 2 and right part of FIG. 3). In the present embodiment, since the substrate potential is supplied to the fuse F via the guard ring G, p ⁺ is provided in the semiconductor substrate below the guard ring G (plug 26).
A type semiconductor region 18 is provided. In addition, the signal wiring S
2 is formed by the second layer wiring M2, a third layer wiring M3 forming the guard ring G, which is not shown in FIG. 1, may be formed above the signal wiring S (see FIG. 2). See right).

As shown in the left part of FIG. 3 and FIG. 4, the fuse F is composed of the third layer wiring M3, and the end portion of the fuse F is connected to the second layer wiring M2 (through the plug 55 (P). M)
To an element or the like (not shown).

As described above, according to the present embodiment, since the guard ring G is provided with the opening OA and the signal wiring S is passed through, the degree of freedom in wiring layout is increased. Also,
The area occupied by the fuse and the signal wiring can be reduced.

That is, for example, as shown in FIG.
When the guard ring G is divided according to the layout of the signal wiring S, the fuse F at the end and the guard ring G must be separated by a certain distance (D + E). The formation area becomes large.

On the other hand, according to the present embodiment, as shown in FIG. 6B, [2 (A + C +
D + E-B)], the width of the region can be reduced. As a result, the area occupied by the fuse F and the signal wiring S can be reduced.

In the present embodiment, the guard ring G is connected to the plugs 26, 52 and 55 and the wirings M1 and M.
Although formed using 2, M3, other conductive films, for example, the conductive film forming the gate electrode 9, the plugs 22 and 39 or the lower electrode 43 and the upper electrode 45 forming the information storage capacitor C, and the like. Alternatively, the guard ring G may be formed by appropriately combining these films.

Further, in the present embodiment, the fuse F is formed by the third layer wiring M3 and the signal wiring S is formed by the second layer wiring M2, but the fuse F and the signal wiring S are formed by the wiring in the same layer. May be. In FIG. 7, the fuse F and the signal wiring S are shown as a third
A sectional view of a fuse formation region in the case where the fuse is formed by the layer wiring M3 is shown. This cross section corresponds to the A1-A1 cross section of FIG.

According to such a configuration, the fuse is formed by the wiring in the same layer as the signal wiring S, the opening OA is provided in the guard ring G, and the signal wiring S is made to pass therethrough. The degree of freedom in layout increases. Further, the area occupied by the fuse and the signal wiring can be reduced.

Further, although the second layer wiring M2 is the signal wiring S in the present embodiment, the first layer wiring M is further used.
1 may be used as the signal wiring S. FIG. 8 shows a cross-sectional view of the fuse formation region when the second layer wiring M2 and the first layer wiring M1 are used as the signal wiring S. This cross section is shown in Figure 1.
Corresponding to the A1-A1 cross section.

According to this mode, a plurality of wirings below the fuse can be used as signal wirings, and the occupied area can be further reduced. In addition,
The opening OA may be provided at a plurality of locations for each wiring.

Although the invention made by the present inventor has been specifically described based on the embodiments, the present invention is not limited to the above-mentioned embodiments, and various modifications can be made without departing from the scope of the invention. Needless to say.
In particular, although the DRAM memory cell is formed in the memory cell formation region in this embodiment, another memory such as an EEPROM may be formed.

[0068]

The effects obtained by the typical ones of the inventions disclosed by the present application will be briefly described as follows.
It is as follows.

Since the wiring is extended between the plurality of fuses, the degree of freedom in the layout of the wiring is increased. Also,
It is possible to reduce the area where fuses and wirings are formed.

Further, since the fuse is surrounded by a wall made of a laminated film of conductive films and having an opening, and the wiring is arranged so as to pass through the opening, the degree of freedom of the layout of the wiring is increased. Increase. Further, it is possible to reduce the area where fuses and wirings are formed.

[Brief description of drawings]

FIG. 1 is a plan view of a principal part of a substrate showing a semiconductor integrated circuit device according to an embodiment of the present invention.

FIG. 2 is a cross-sectional view of essential parts of a substrate showing a semiconductor integrated circuit device according to an embodiment of the present invention.

FIG. 3 is a main-portion cross-sectional view of a substrate showing a semiconductor integrated circuit device according to an embodiment of the present invention.

FIG. 4 is a cross-sectional view of essential parts of a substrate showing a semiconductor integrated circuit device according to an embodiment of the present invention.

5A and 5B are diagrams showing a pattern of a conductive film forming a guard ring of the semiconductor integrated circuit device according to the embodiment of the present invention.

6 (a) and 6 (b) are plan views of the essential part of the substrate showing the semiconductor integrated circuit device for explaining the effect of the embodiment of the present invention.

FIG. 7 is a main-portion cross-sectional view of a substrate showing a semiconductor integrated circuit device of another embodiment of the present invention.

FIG. 8 is a cross-sectional view of essential parts of a substrate showing a semiconductor integrated circuit device of another embodiment of the present invention.

[Explanation of symbols]

1 semiconductor substrate 2 element isolation 3 p-type well 8 gate oxide film 9 gate electrode 10 silicon nitride film 13 n-type semiconductor region 16 silicon nitride film 17 n ⁺ -type semiconductor region 18 p ⁺ -type semiconductor region 19 silicon oxide film 20, 21 contact Hole 22 Plug 23 Silicon oxide film 24 Contact hole 25 Through hole 26 Plug 34 Silicon oxide film 38 Through hole 39 Plug 40 Silicon nitride film 41 Silicon oxide film 42 Groove 43 Lower electrode 44 Capacitance insulating film 45 Upper electrode 50 Silicon oxide film 51 Through Hole 52 Plug 53 Silicon oxide film 54 Through hole 55 Plug 56 Protective film SW Side wall spacer BL Bit line WL Word line M Wiring M1 First layer wiring M2 Second layer wiring M3 Third layer wiring OP Opening P Plug C Information storage Capacitive element Qn n Channel type MISFET Qs for memory cell selection MISFET S signal line F Fuse G guard ring OA opening A~E interval

   ─────────────────────────────────────────────────── ─── Continued front page    F term (reference) 5F064 DD24 EE14 EE15 EE17 EE23                       FF02 FF27 FF30 FF32 FF42                 5F083 AD10 AD24 AD48 JA32 JA36                       JA39 JA40 MA05 MA06 MA17                       MA19 ZA10

Claims (5)

[Claims] 1. (a) A plurality of first members extending in a first direction
A semiconductor integrated circuit device having a fuse made of a conductive film of (1), and (b) a wiring made of a second conductive film, wherein the wiring extends in the first direction between the fuses. A semiconductor integrated circuit device characterized by: 2. (a) A plurality of first members extending in the first direction
(B) a wall made of a laminated film of a second conductive film and formed to surround the plurality of fuses, the wall having an opening, and (c) ) A wiring formed of a third conductive film, the wiring being arranged so as to pass through the opening, a semiconductor integrated circuit device. 3. The semiconductor integrated circuit device according to claim 2, wherein the first conductive film and the third conductive film are formed in the same layer. 4. The semiconductor integrated circuit device according to claim 2, wherein the first conductive film is formed in a layer above the third conductive film. 5. The semiconductor integrated circuit device further comprises: (d) another wiring made of a fourth conductive film, the wiring being arranged to pass through the opening, The semiconductor integrated circuit device according to claim 4, wherein the fourth conductive film is a layer lower than the third conductive film.