JP2003077890A - Method of manufacturing semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide technology for suppressing the fluctuation of a pattern size in a dry etching process and improving the yield of a semiconductor device. SOLUTION: The prescribed number of substrates 6 are etched, ozone is introduced into the chamber of a dry etching device 1, and the surface of an Al grounding wire 3 is oxidized. Thus, the cut of Al2 O3 is restored. Consequently, the adhesion of an Al product to the substrate 6 or the reaction of the Al product and etching gas due to the exposure of the Al grounding wire 3 is prevented, and the fluctuation of the pattern size is suppressed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device manufacturing technique, and more particularly to a technique effective when applied to a dry etching process for processing a material on a substrate into a desired pattern.

[0002]

2. Description of the Related Art MISFET (metal insulator field effect) made of a wiring made of a metal material or a conductive material.
A dry etching technique is used for forming a circuit pattern such as a gate electrode of a transistor. In particular,
Plasma etching technology, which uses gas and plasma to generate ions and neutral active species, can form patterns with less undercut by selecting conditions, which is essential for miniaturization of semiconductor devices. Technology.

For example, an ECR (electron cyclotron resonan) is a method in which an electromagnetic wave is introduced into a vacuum and free electrons are given energy by an electromagnetic field of the electromagnetic wave to generate plasma.
(CE: Electron Cyclotron Resonance) Plasma etching method is a MISFET with a gate length of about 0.1 to 0.12 μm.
It has been put to practical use for microfabrication of gate electrodes.

Incidentally, "Basics of Ultrafine Machining", published by The Nikkan Kogyo Shimbun, March 25, 1993, by Tachio Masaki, P74.
An example of the ECR type etching apparatus is described in FIG. 4.10 (b).

[0005]

[Problems to be Solved by the Invention] DRAM (dynamic ra
ndom access memory) or ASIC (application sp
In the ecific integrated circuit), the miniaturization of circuit patterns has advanced, and the allowable range of target dimension values has become narrower. Therefore, for example, the dimensional accuracy of the mask used in the lithography process is improved, and the dimensional accuracy of the pattern is improved in the lithography process and the dry etching process.

However, as a result of a study by the present inventor, dimensional variation within a lot or between lots due to variation in the chamber of the dry etching apparatus has become remarkable, and this dimensional variation causes a large variation in characteristics of semiconductor elements. It has become clear that the yield of semiconductor devices is reduced.

Particularly, in the ECR plasma etching apparatus, there is a problem of pattern dimensional variation which is considered to be caused by scraping of Al ₂ O ₃ (aluminum oxide) on the Al (aluminum) ground surface. That is, when the Al ground is exposed due to the scraping of Al ₂ O ₃ , the Al ground is scraped during the etching process to generate an Al (aluminum) product, which becomes a foreign matter and adheres to the substrate, or the Al product is an etching gas. It is considered that the composition of the gas changes in response to the above, and as a result, the dimensional variation of the pattern occurs.

An object of the present invention is to provide a technique capable of suppressing the variation of the pattern size in the dry etching process and improving the yield of semiconductor devices.

The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0010]

Among the inventions disclosed in the present application, a brief description will be given to the outline of typical ones.
It is as follows.

According to the present invention, when a material to be etched on a substrate is processed by using a dry etching apparatus provided with an Al earth whose surface is covered with Al ₂ O ₃ , an etching treatment is performed on a predetermined number of substrates. After that, ozone is introduced into the chamber of the dry etching apparatus, and Al ₂ O ₃ is attached to the surface of the Al ground at a predetermined temperature to prevent the Al ground from being exposed.

[0012]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described in detail below with reference to the drawings. In all the drawings for explaining the embodiments, members having the same function are designated by the same reference numerals, and the repeated description thereof will be omitted.

(Embodiment 1) A dry etching technique according to an embodiment of the present invention will be described with reference to the schematic view of the ECR plasma etching apparatus shown in FIG. 1 in the figure
Is a dry etching device, 2 is a magnetron, 3 is Al
Earth, 4 ozone generator, 5 electrode, 6 substrate, 7 electromagnetic coil, 8 quartz plate, 9 quartz shower plate,
Reference numeral 10 is a quartz inner cylinder, 11 is a discharge block, 12 is a ring gate, 13 is a susceptor, and 14 is an electrode lower cover.

The dry etching apparatus 1 is an apparatus which employs a system in which a magnetic field is applied in the axial direction of a room where plasma is generated and electric power is supplied from the magnetron 2 to generate electric discharge, and for example, several μm to 50 μm. Thickness of insulating material,
For example, an Al earth 3 whose surface is covered with Al ₂ O ₃ is provided. Further, an ozone generator 4 is attached to the dry etching apparatus 1, and for example, ozone can be generated by introducing high-frequency discharge after introducing oxygen gas.

First, a substrate 6 (for example, a wafer obtained by processing a single crystal such as silicon into a circular thin plate) placed on the electrode 5 is subjected to an etching process. A material to be etched is formed on the substrate 6, and the material to be etched is processed using, for example, a resist pattern as a mask.
In this case, Al ₂ O ₃ on the surface of Al earth 3 also has a slightly etched.

Next, a predetermined number of, for example, about 1000 substrates 6 are subjected to etching treatment, and then the surface of the Al ground 3 scraped by the etching treatment is oxidized to restore Al ₂ O ₃ . Deposition of Al ₂ O ₃ to Al ground 3, for example, as follows.

First, the temperature of the Al ground 3 is kept at room temperature (T ₁ ).
From the ozone generator 4 to a predetermined temperature (T ₂ ), ozone of a predetermined concentration is introduced into the chamber at a predetermined flow rate through a gas supply unit including a valve and a mass flow meter. Next, the surface of the Al ground 3 is oxidized to form Al ₂ having a thickness of, for example, several μm to 50 μm.
Precipitate O ₃ . After that, the introduction of ozone into the chamber is stopped, and the Al ground 3 is further lowered from the predetermined temperature (T ₂ ) to room temperature (T ₁ ).

[0018] After the Al ₂ O ₃ on the surface of Al ground 3 is repaired, etching of the substrate 6 is resumed. After that, a predetermined number of substrates, for example, about 1000 substrates 6 are etched, and Al on the surface of the Al ground 3 is processed.
_The process of repairing ₂ O ₃ is repeated.

FIG. 2 shows a patterned insulating film,
For example, using a silicon oxide film or a silicon nitride film as a mask
A polycrystalline silicon film with an ECR plasma etching system
Amount of dimensional shift when processing (= processing of polycrystalline silicon film)
Dimension-processing dimension of insulating film) and the number of processed substrates
It is a graph figure which shows. The solid line is A which is the first embodiment.
l Earth surface Al₂O₃Shift when repairing
The amount of dust is indicated by the dotted line, and the Al on the surface of Al ground₂O₃Repair
The dimensional shift amount when not performing is shown. In addition, Al ₂O₃Of the
Recovery is performed every time 1000 substrates are etched.
ing.

When the Al ₂ O ₃ on the surface of the Al ground is not repaired, a stable dimensional shift amount of about 6 nm can be obtained up to about 1000 processed sheets, but it suddenly increases when the processed number exceeds 1000 sheets. The amount of size shift fluctuates, and the amount of size shift becomes about -5 nm for about 2000 sheets. On the other hand, when Al ₂ O ₃ on the surface of Al earth is restored, even if the number of processed sheets reaches about 4000, it is always about 6 nm.
A stable dimensional shift amount is obtained, and by applying the first embodiment, Al on the Al ground surface is
It is possible to suppress the variation of the pattern dimension of the silicon polycrystalline film due to the shaving of ₂ O ₃ .

Next, the CMOS (co
An example of a method for manufacturing a complementary metal oxide semiconductor device will be described in the order of steps with reference to FIGS.

First, as shown in FIG. 3, a semiconductor substrate 21 made of, for example, p ⁻ type silicon single crystal is prepared, and an element isolation region 22 is formed on the main surface of the semiconductor substrate 21. Next, impurities are ion-implanted using the patterned photoresist film as a mask to form the p well 23 and the n well 24. Impurities having a p-type conductivity, for example, boron are ion-implanted into the p-well 23, and the n-well 24
An impurity exhibiting an n-type conductivity, for example, phosphorus is ion-implanted into. Thereafter, impurities for controlling the threshold value of the MISFET may be ion-implanted into each well region.

Next, a silicon oxide film 25a to be a gate insulating film is formed by, for example, a thermal oxidation method or a thermal CVD method, and then a silicon polycrystalline film 26a to be a gate electrode and a silicon oxide film 27a to be a cap insulating film are formed. Then, a laminated film is formed by sequentially depositing by, for example, the CVD method.
Then, a patterned photoresist film 28 is formed on this laminated film.

Next, as shown in FIG. 4, the silicon oxide film 27a is etched using the photoresist film 28 as a mask to form a cap insulating film 27. Then, after removing the photoresist film 28, the silicon polycrystalline film 26a is processed by an ECR plasma etching apparatus using the cap insulating film 27 as a mask to form the gate electrode 26 on the gate insulating film 25.

The above ECR plasma etching apparatus is the dry etching apparatus 1 to which the ozone generator 4 shown in FIG. 1 is attached, and repairs Al ₂ O ₃ on the surface of the Al ground 3 which is shaved by the etching process. It has the functions that can be done. As mentioned above, for example, about 100
Every time about 0 semiconductor substrates 21 are etched, the surface of the Al ground 3 is oxidized by ozone introduced into the chamber of the dry etching apparatus 1 to several μm.
Al ₂ O ₃ having a thickness of about 50 μm can be deposited. As a result, variations in the pattern size of the gate electrode 26 can be suppressed, and variations in characteristics of the CMOS device can be reduced.

Next, as shown in FIG.
After depositing a silicon oxide film thereon by, for example, a CVD method, the silicon oxide film is anisotropically etched to form sidewall spacers 29 on the sidewalls of the gate electrode 26. Then, using the patterned photoresist film as a mask, an n-type impurity in the p-well 23,
For example, phosphorus or arsenic is ion-implanted, and p-well 23
N-type semiconductor regions 30 are formed on both sides of the upper gate electrode 26. The n-type semiconductor region 30 is formed in self-alignment with the gate electrode 26 and the sidewall spacer 29, and functions as the source and drain of the n-channel MISFET.

Similarly, by using the patterned photoresist film as a mask, p-type impurities such as boron fluoride are ion-implanted into the n-well 24, and the p-type semiconductor regions 31 are formed on both sides of the gate electrode 26 on the n-well 24. Form.
The p-type semiconductor region 31 is formed in self-alignment with the gate electrode 26 and the sidewall spacer 29, and p
It functions as the source and drain of the channel MISFET.

Next, as shown in FIG. 6, the semiconductor substrate 21
After the silicon oxide film 32 is formed on the silicon oxide film 32, the silicon oxide film 32 is removed by, for example, CMP (chemical mechanical po
The surface is flattened by polishing with the lishing) method.
The silicon oxide film 32 is formed of, for example, TEOS (tetra ethy
ortho silicate: Si (OC ₂ H ₅ )) and TEO deposited by plasma CVD using ozone as source gas
It is composed of an S oxide film.

Next, the silicon oxide film 3 is formed by etching using the patterned photoresist film as a mask.
The connection hole 33 is formed in 2. The connection hole 33 is formed in a necessary portion such as on the n-type semiconductor region 30 or the p-type semiconductor region 31.

Further, a titanium nitride film is formed on the entire surface of the semiconductor substrate 21 including the inside of the connection hole 33 by, for example, a CVD method, and a tungsten film filling the connection hole 33 is further formed.
For example, it is formed by the CVD method. After that, the titanium nitride film and the tungsten film in the region other than the connection hole 33 are removed by, for example, the CMP method to remove the plug 3 inside the connection hole 33.
4 is formed.

Then, a metal film is formed on the entire surface of the semiconductor substrate 21,
For example, after forming a tungsten film or an aluminum film, the metal film is processed by etching using the patterned photoresist film as a mask to form the wiring 35 of the first wiring layer. The metal film can be formed by a CVD method or a sputtering method.

Next, as shown in FIG. 7, after forming an insulating film that covers the wiring 35, for example, a silicon oxide film, the insulating film is polished by, for example, the CMP method to form an interlayer whose surface is flattened. The insulating film 36 is formed. Then, the contact hole 3 is formed in a predetermined region of the interlayer insulating film 36 by etching using the patterned photoresist film as a mask.
Form 7.

Next, a barrier metal layer is formed on the entire surface of the semiconductor substrate 21 including the inside of the connection hole 37, and the connection hole 3 is formed.
Then, a copper film for burying 7 is formed. The barrier metal layer is, for example, titanium nitride, tantalum, tantalum nitride, or the like, and is formed by, for example, the CVD method or the sputtering method. The copper film functions as a main conductor layer and can be formed by, for example, a plating method.
Before forming the copper film by the plating method, a thin copper film can be formed as a seed layer by, for example, the CVD method or the sputtering method. Then, the copper film and the barrier metal layer in regions other than the connection holes 37 are removed by, for example, the CMP method to remove the connection holes 3
A plug 38 is formed inside 7.

Next, as shown in FIG. 8, the interlayer insulating film 36 is formed.
Then, a stopper insulating film 39 is formed on the plug 38, and an insulating film 40 for forming wiring is further formed. The stopper insulating film 39 is, for example, a silicon nitride film, and the insulating film 40 is used.
Is a silicon oxide film, for example. Next, a wiring groove 41 is formed in a predetermined region of the stopper insulating film 39 and the insulating film 40 by etching using the patterned photoresist film as a mask.

Next, a barrier metal layer 42 is formed on the entire surface of the semiconductor substrate 21 including the inside of the wiring groove 41, and a copper film filling the wiring groove 41 is formed. Barrier metal layer 42
Is titanium nitride, tantalum, tantalum nitride, or the like, and is formed by, for example, the CVD method or the sputtering method.
The copper film functions as a main conductor layer and can be formed by, for example, a plating method. Before forming the copper film by the plating method, for example, CV
A thin copper film can be formed as a seed layer by the D method or the sputtering method. After that, the copper film and the barrier metal layer 42 in the region other than the wiring groove 41 are removed by, for example, the CMP method to form the wiring 43 of the second wiring layer inside the wiring groove 41.

After that, after forming the upper wiring,
By covering the entire surface of the semiconductor substrate 21 with the passivation film, the CMOS device is almost completed.

In the manufacturing process of the CMOS device according to the first embodiment, the case where the present invention is applied to the ECR plasma etching apparatus used for processing the silicon polycrystalline film 26a forming the gate electrode 26 has been described. The present invention can be applied to any ECR plasma etching apparatus used in processes such as etching of a silicon oxide film, a tungsten film or an aluminum film.

In the first embodiment, the Al ground 3 is used.
The frequency of repairing Al ₂ O ₃ on the surface of the substrate was set according to the number of processed substrates. For example, the change in the gas composition in the chamber was monitored, and when the gas composition reached a predetermined value, A
l ₂ O ₃ may be repaired.

As described above, according to the first embodiment, E
Al of A grounded in CR plasma etching equipment
Since it is possible to prevent exposure due to abrasion of l ₂ O ₃ ,
It is possible to prevent the deposition of the product on the substrate or the reaction between the Al product and the etching gas. As a result, it is possible to suppress variations in pattern dimensions and reduce variations in characteristics of semiconductor elements.

(Second Embodiment) FIG. 9 is a schematic view showing an ECR plasma etching apparatus according to another embodiment of the present invention.

Similar to the dry etching apparatus 1 shown in the first embodiment, the dry etching apparatus 44 applies a magnetic field in the axial direction of the room where plasma is generated, and the magnetron 2 is used.
This is an ECR plasma etching apparatus that employs a method of causing a discharge from the ground, but the ground 45 is made of tungsten or silicon. By forming the ground 45 from tungsten or silicon as described above, the ground 45 is less likely to be scraped during the etching process of the material to be etched, or the material does not change even if it is scraped, so that the variation of the pattern dimension can be suppressed. it can.

Although the invention made by the present inventor has been specifically described based on the embodiments of the present invention, the present invention is not limited to the above-mentioned embodiments, and various modifications can be made without departing from the scope of the invention. It goes without saying that it can be changed.

For example, in the above-described embodiment, the case where the invention is applied to the ECR plasma etching apparatus has been described, but the invention can be applied to any dry etching apparatus provided with Al ground.

[0044]

The effects obtained by the typical ones of the inventions disclosed in the present application will be briefly described as follows.

In the dry etching process, since it is possible to suppress the variation of the pattern dimension due to the abrasion of Al ₂ O _{3 on} the surface of the Al ground, it is possible to reduce the characteristic variation of the semiconductor element and improve the yield of the semiconductor device. You can

[Brief description of drawings]

FIG. 1 is a schematic diagram of an ECR plasma etching apparatus that is an embodiment of the present invention.

FIG. 2 is a graph showing a relationship between a dimension shift amount and the number of processed substrates.

FIG. 3 is a fragmentary cross-sectional view of a semiconductor substrate showing a method for manufacturing a CMOS device according to an embodiment of the present invention.

FIG. 4 is a fragmentary cross-sectional view of a semiconductor substrate showing a method for manufacturing a CMOS device which is an embodiment of the present invention.

FIG. 5 is a fragmentary cross-sectional view of a semiconductor substrate showing a method for manufacturing a CMOS device according to an embodiment of the present invention.

FIG. 6 is a fragmentary cross-sectional view of a semiconductor substrate showing a method for manufacturing a CMOS device according to an embodiment of the present invention.

FIG. 7 is a fragmentary cross-sectional view of a semiconductor substrate showing a method for manufacturing a CMOS device according to an embodiment of the present invention.

FIG. 8 is a fragmentary cross-sectional view of a semiconductor substrate showing a method for manufacturing a CMOS device according to an embodiment of the present invention.

FIG. 9 is a schematic view of an ECR plasma etching apparatus which is another embodiment of the present invention.

[Explanation of symbols]

1 Dry etching equipment 2 magnetron 3 Al ground 4 Ozone generator 5 electrodes 6 substrate 7 electromagnetic coil 8 Quartz plate 9 Quartz shower plate 10 Quartz inner cylinder 11 discharge block 12 ring gate 13 Susceptor 14 Electrode lower cover 21 Semiconductor substrate 22 Element isolation region 23 p-well 24 n-well 25 Gate insulation film 25a Silicon oxide film 26 Gate electrode 26a Silicon polycrystalline film 27 Cap insulation film 27a Silicon oxide film 28 Photoresist film 29 Sidewall spacer 30 n-type semiconductor region 31 p-type semiconductor region 32 Silicon oxide film 33 Connection hole 34 plug 35 wiring 36 Interlayer insulation film 37 Connection hole 38 plugs 39 Stopper insulation film 40 insulating film 41 Wiring groove 42 Barrier metal layer 43 wiring 44 Dry etching system 45 Earth

   ─────────────────────────────────────────────────── ─── Continued front page    (72) Inventor Shinichi Suzuki             5-20-1 Kamimizuhonmachi, Kodaira-shi, Tokyo Stock             Ceremony Company within Hitachi Semiconductor Group F-term (reference) 5F004 AA01 AA16 BA14 BB29 BC07                       DA27 DB03 DB09 DB10

Claims (5)

[Claims] 1. A method of manufacturing a semiconductor device in which a material to be etched on a substrate is processed by using a dry etching apparatus equipped with a ground made of aluminum, wherein the earth is formed after etching a predetermined number of substrates. A method for manufacturing a semiconductor device, characterized in that aluminum oxide is attached to the surface of the semiconductor device. 2. A method of manufacturing a semiconductor device in which a material to be etched on a substrate is processed by using a dry etching apparatus having a ground made of aluminum, wherein a gas composition in a chamber of the dry etching apparatus is a predetermined gas. A method of manufacturing a semiconductor device, wherein aluminum oxide is adhered to the surface of the ground when the composition is reached. 3. A method of manufacturing a semiconductor device, which comprises processing a material to be etched on a substrate by using a dry etching device having a ground made of tungsten or silicon. 4. A method of manufacturing a semiconductor device in which a material to be etched on a substrate is processed by using a dry etching apparatus provided with a ground made of aluminum, wherein the dry treatment is performed after etching a predetermined number of substrates. A method of manufacturing a semiconductor device, wherein ozone is introduced into a chamber of an etching apparatus, and aluminum oxide is attached to a surface of the earth at a predetermined temperature. 5. A method of manufacturing a semiconductor device in which a material to be etched on a substrate is processed by using a dry etching apparatus having a ground made of aluminum, wherein a gas composition in a chamber of the dry etching apparatus is a predetermined gas. When the composition is reached, ozone is introduced into the chamber, and aluminum oxide is attached to the surface of the earth at a predetermined temperature.