JP2003076602A - Memory control method and memory control circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To solve such problems on a synchronous high-speed memory that the setup time for write data is liable to run short and sometimes causes difficulty in no-wait operation. SOLUTION: This memory control circuit 1 has a memory input control circuit 4, a latch control circuit 3, a latch junction circuit 50, and a read data selection circuit 5. The latch function circuit 50 latches a write command, write data and an addresses under the control of the latch control circuit 3 and delays a write cycle being viewed from a memory 2 by one clock component. In this process, the write data can be made sufficiently ready. When there is read access to a memory address where write is not completed, the read data selection circuit 5 selects and outputs the write data latched by the latch function circuit 50.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory control circuit,
In particular, it relates to a circuit for controlling a memory whose read and write operations are controlled in synchronization with a clock.

[0002]

2. Description of the Related Art One of the points of timing design for controlling a memory that operates in synchronization with a clock is to secure setup and hold times of addresses and write data with respect to the clock. In particular, the condition regarding the setup time becomes stricter as the clock becomes faster, and this timing often determines the whole operation performance. In the following, write data will be taken as an example for consideration of setup time.

In general, in order to increase the setup time, a method is known in which the propagation path of the write data is set to be the shortest to reduce the propagation delay, or the clock that determines the timing of fetching is somewhat delayed to secure a margin. . The semiconductor memory device described in Japanese Patent Application Laid-Open No. 9-91956 includes means for generating an internal clock from an input clock, a state setting circuit and a switch controlled by its output signal, and an input signal such as a command and the like. One of the signals passed through the delay circuit is selected by switching the switch and latched by the internal clock. This is intended to satisfy one or both of the setup and hold times.

[0004]

According to this semiconductor memory device, the setup time or the hold time can be finely adjusted according to the situation. However, since the adjustment is delicate, it is necessary to build the delay circuit and the internal clock generating means described above in the semiconductor memory device, that is, the memory itself, which results in a special circuit configuration.

However, the design values relating to the setup time of write data to the memory and the access time of read data to the memory become apparent after a considerable amount of design of the system in which the memory is incorporated, and the adjustment circuit is incorporated in the memory in advance. That is not always the case. In some cases, the presence of such a circuit in the memory induces an increase in cost or an increase in delay of any signal propagation path, and the effect corresponding to the problem may not be obtained.

The present invention has been made in view of such a background, and an object thereof is a memory that does not impose a burden on the design of the memory, is easy to be flexible and can be adjusted posteriorly, and has little difficulty in fine timing adjustment. It is to provide a control circuit.

[0007]

A memory control circuit according to an aspect of the present invention is a circuit which is connected to a memory which operates in synchronization with a clock to control the memory. Includes signal lines to behave like memory. Therefore, this control circuit can be called a "deemed memory", and such an expression will be used hereinafter as appropriate. This control circuit has an address input port, a write data input port, a read data output port, an address latch circuit, a write data latch circuit, and a read data selection circuit.

In this structure, a read cycle corresponding to the read operation is generated for the memory in the same clock cycle as the read cycle corresponding to the read operation for the considered memory. Further, when a write operation to the assumed memory occurs, an address input from the address port corresponding to the write operation is temporarily held in the address latch circuit and the write data inputtable port corresponding to the write operation can be input. The write data input from the write data latch circuit is temporarily held in the write data latch circuit, and the write cycle corresponding to the write operation to the memory is a natural number multiple of one clock cycle with respect to the write operation to the deemed memory. Delay.

On the other hand, the read data selection circuit selects one of the read data from the output of the memory and the data held by the write data latch circuit for each data field in the read operation to the deemed memory, and the read data selection circuit. Read data is output from the port that can output data.

"Selecting one of the data fields" includes the case of selecting one of all fields from the output of the memory and the data held by the write data latch circuit. With this configuration, it is possible to correctly output the read data even when a read operation for an address whose writing to the memory is not completed occurs.

The memory control circuit of the present invention may operate in synchronization with a clock in which an edge occurs intentionally at least at one of the rising edge and the falling edge of the clock without delay. “Intentionally without delay” means that no delay with the intention of increasing the setup time is given. The "intentionally without delay" example is simply a propagation delay.

The memory control circuit of the present invention may operate in synchronization with a clock input to the memory, which is not intentionally delayed. This means that it operates in synchronization with a clock that is an inverted clock of the clock input to the memory and has no intentional delay.

It is desirable that the memory control circuit of the present invention acts so as to relax the setup time of at least one of write data and address for the memory.

The read data selection circuit has a comparator for comparing the address corresponding to the read cycle currently in progress with the address held in the address latch circuit, and the condition is that both match. As one
The selection may be made. With this configuration, it is possible to determine whether or not a read operation has occurred with respect to an address for which writing to the memory has not been completed, and the above selection can be performed using the result of the determination as one of the conditions.

According to an aspect of the present invention, a byte write command input port and a byte write command latch circuit are further provided, and when a write operation to the assumed memory occurs, the byte write command input port corresponding to the write operation is input from the byte write command input port. The byte write command input is temporarily stored in the byte write latch circuit. The read data selection circuit makes the selection by using the value held by the byte write command latch circuit as one of the conditions. In this case, it is desirable that the memory control circuit acts so as to relax the setup time of the byte write command for the memory.

In any of the above cases, the data field may be in units of bytes. In the present invention,
The write data inputtable port and the read data outputtable port may be separate ports. Alternatively, they may be common and bidirectional ports.

Yet another aspect of the present invention relates to a method of controlling a memory that operates in synchronization with a clock. In this method, an address and data related to a write operation for the memory are latched by the clock and delayed and then input to the memory, and when the access cycle of the write operation for the memory is viewed from the memory, the clock A state in which the setup time of at least one of the address and the data is increased by creating a state that occurs with a delay of a natural number times the cycle of the above, and a defect may occur in the operation of the memory due to the delay in the access cycle. Is detected and the avoidance processing of the defect is performed outside the memory without depending on the insertion of the wait, thereby maintaining the consistency of the operation of the memory.

It should be noted that any combination of the above constituent elements, and the expression of the present invention converted between a method, a device, a system, a computer program, a recording medium and the like are also effective as an aspect of the present invention.

[0019]

FIG. 1 shows a state in which a memory control circuit 1 according to an embodiment is connected to a memory 2. The outline of the function of the memory control circuit 1 is to secure the setup time of the write data and the byte write signal to the memory 2 by delaying the write operation to the memory 2 by the latch circuit. However, since the writing of the write data to the memory 2 is delayed, access to data which has not been written to the memory 2 may occur in the subsequent read cycle in some cases. Therefore, the read data selection circuit 5 selects either the data held in the latch circuit or the data read from the memory 2 and outputs it to a data request source such as a processor (hereinafter simply referred to as a processor).

Therefore, the read data selection circuit 5 compares the read address corresponding to the current read cycle with the address corresponding to the uncompleted write operation, and when they match, for example, the uncompleted write operation. If all byte write signals corresponding to are active, the latched data is output instead of the memory 2. In this embodiment, the write data latch 9 holds the write data corresponding to the write cycle that precedes the read cycle and is closest to the read cycle. The write data held in the write data latch 9 in the read cycle is held unchanged during the next clock cycle.

The signal names and symbols used in this embodiment will be defined below. All commands and other control signals are active high. CLK10: This is a clock that determines the operation of the memory 2, and the memory 2 operates in synchronization with the rising edge of this clock. The memory control circuit 1 also operates in synchronization with the same edge as a whole. However, from FIG. 2 onward, the clock input to flip-flops and the like is omitted for the sake of simplicity. RST11: Initializes the flip-flop of the memory control circuit 1. This signal is also omitted in the figure. WE12: Write command issued from the processor or the like. Normally, it is directly input to the memory 2, but in the present embodiment, the memory control circuit 1 receives it. BW13: A 4-bit byte write signal that specifies which byte of 4-byte data is to be written to the memory 2. RE14: Read command issued from the processor or the like. ADDR15: Address issued from the processor or the like. WDATA16: Write data output from a processor or the like. RDATA17: Read data output for read access by a processor or the like. HLDWE18: Write command held by the latch operation. Hereinafter, in the present specification, "held"
Is effectively equivalent to being "delayed." HLDBW19: Byte write signal held by the latch operation. HLDADDR20: Address held by the latch operation. HLDWDATA21: Write data held by the latch operation. MEMWE22: Write command to be input to the memory 2. MEMWB23: Byte write signal input to the memory 2. MEMRE24: Read command input to the memory 2. MEMADDR25: Address to be input to the memory 2.
This bit number depends on the specifications of the memory 2, but is generally smaller than the bit number of the logical address of the processor or the like. MEMWDATA26: Write data to be input to the memory 2. MEMRDATA27: Read data output from the memory 2.

The configuration will be described using the above notation. Figure 1
, The memory control circuit 1 uses CLK10, RST1
1, WE12, BW13, RE14, ADDR15, W
Input DATA16 from the processor and other circuits, and
The EMRDATA 27 is input from the memory 2. The memory control circuit 1 outputs RDATA17 to the processor or the like.

The memory control circuit 1 has a memory input control circuit 4, a latch control circuit 3, a latch function circuit 50, and a read data selection circuit 5. The memory input control circuit 4 mainly generates a signal to be input to the memory 2. The latch function circuit 50 includes a circuit for latching various signals for that purpose. The latch control circuit 3 controls the latch circuit. The read data selection circuit 5 selects either the data output from the memory 2 or the latched data in the read cycle and outputs the selected data to the processor or the like.

FIG. 2 shows the detailed configurations of the latch control circuit 3 and the latch function circuit 50. Hereinafter, in the present embodiment, a D flip-flop is used as a latch circuit, but naturally, this may be a through latch type, and there are various other configuration methods. Hereinafter, such latch circuits are collectively referred to simply as "latch". The latch function circuit 50 is an HLDW.
E18, HLDBW19, HLDADDR20, HLD
A write command latch 6, a byte write signal latch 7, an address latch 8, which generate WDATA 21, respectively.
It has a write data latch 9. Actually, the write command latch 6 has 1 bit, the byte write signal latch 7 has 4 bits, the address latch 8 and the write data latch 9
Are, for example, 11-bit and 32-bit configurations, respectively.

The latch control circuit 3 is an HLDWE logic circuit 300 which generates an input signal of the write command latch 6.
The WE delay circuit 308 and the first selector 302 that generate the input signal of the byte write signal latch 7, the second selector 304 that generates the input signal of the address latch 8, and the third selector that generates the input signal of the write data latch 9. It has a selector 306. The HLDWE logic circuit 300 is a combinational circuit and receives WE12 and MEMWE22.
After WE12 becomes active, the output of HLDWE logic circuit 300 will be high as long as WE12 is active. Even if WE12 becomes inactive, ME
The output remains high as long as MWE 22 is low.

The WE delay circuit 308 delays the WE 12 by one clock. The output is input to the first selector 302, where one of the HLDBW 19 and BW 13 is selected and output. When the WE delay signal 310 that is the output of the WE delay circuit 308 is high, the input side of the first selector 302 marked with “1”, that is, the BW 13 is selected and output. When the WE delay signal 310 is low, the input side with "0", that is, the HLDBW 19, is selected and output. In the following, which input side of the selector is selected is indicated by "1" and "0" in the figure, and will not be described in detail.

The second selector 304 outputs one of HLDDRDDR 20 and ADDR 15 according to the state of WE 12. The third selector 306 outputs the WE delay signal 3
According to the state of 10, HLDWDATA21 or W
One of DATA16 is output.

FIG. 3 shows a detailed structure of the memory input control circuit 4. The memory input control circuit 4 is a MEMWE logic circuit 40.
0 and selector 402. MEMWE logic circuit 400
Outputs MEMWE22 high only when HLDWE18 is high and RE14 is low. Therefore, FIG.
As will be described later, the MEMWE logic circuit 400 has a function of executing writing of write data to the memory 2 after waiting for a break in the read cycle. The selector 402 is RE
According to the state of 14, HLDDRDDR20 or AD
One of DR15 is selected and output as MEMADDR25. The selector 402 has a multi-bit configuration. MEM
BW23 and MEMWDATA26 are HLDB respectively
It is a signal that is logically the same as W19 and HLDWDATA21.

FIG. 4 shows a detailed configuration of the read data selection circuit 5. The read data selection circuit 5 uses CLK10, RST
11, MEMRDATA27, ADDR15, HLDW
E18, HLDBW19, HLDADDR20, HLD
Enter WDATA21. The first selector 500 in the figure is MEM according to the output of the first AND 502.
RDATA27 bits 7-0 and HLDWDATA
One of the bits 7-0 of 21 is selected and output as the bit 7-0 of RDATA17. One input of the first AND 502 is bit 0 of the HLDBW 19, and the other input is the output of the fifth AND 524. One input of the fifth AND 524 is the HLDWE 18, and the other input is the output 530 of the comparator 522. Comparator 522 is H
The outputs of LDDRDDR 20 and ADDR delay circuit 520 are compared, and if they match, the output 530 goes high. AD
The DR delay circuit 520 delays the ADDR 15 by one clock and outputs it.

The second selector 504 is connected to the second AND 5
Bit 15 of MEMRDATA27 depending on the output of 06
One of -8 and bit 15-8 of HLDWDATA21 is selected and output as bit 15-8 of RDATA17. One input of the second AND 506 is HLDBW
Bit 1 of 19, the other input is the output of the fifth AND 524.

The third selector 508 is the third AND 5
Bit 23 of MEMRDATA27 depending on the output of 10
-16 and bits 23-16 of HLDWDATA21
Is selected and output as bits 23-16 of RDATA17. One input of the third AND 510 is HL
Bit 2 of DBW19, the other input is the fifth AND 52
4 output.

The fourth selector 512 includes a fourth AND 5
Bit 31 of MEMRDATA 27 depending on the output of 14
-24 and bits 31-24 of HLDWDATA21
One of them is selected and output as bits 31-24 of RDATA17. One input of the fourth AND 514 is HL
Bit 3 of DBW19, the other input is the fifth AND 52
4 output.

FIG. 5 is a timing chart showing the write operation specifications of the memory 2. The signal names in the figure correspond to the pins of the memory 2 and are described in the memory 2 of FIG. That is, these signals are directly visible from the memory 2. For example, "WE" in FIG.
In WE12 which is output from the processor in
It corresponds to EMWE22. Hereinafter, the same caution is required for other signals.

In FIG. 5, "C1", "C2" and the like indicate cycles determined for each cycle of the clock. Also (1)
(2), etc. are for cycle C1, C2, etc., respectively.
This is the timing when the memory 2 refers to each signal. The memory 2 samples a write command, a read command and an address at the start timing of each cycle, while sampling a byte write signal and write data at the end timing of the cycle.

On the other hand, FIG. 6 is a timing chart showing the read operation specifications of the memory 2. Memory 2 as in FIG.
Samples the write command, read command, and address at the start timing of each cycle, and outputs the read data in time for the end timing of the cycle. The timing charts of FIG. 5 and FIG. 6 are prerequisites for configuring the memory control circuit 1 of the present embodiment.

FIGS. 7 to 9 show the operation of the above configuration for some representative cycles. [Cycle C3] In FIG. 7, a signal having a meaning in cycle C3 is shaded to emphasize its timing. WE1
2 and ADDR15, the cycle C3 is a write cycle to the address 0x3FF, and the write data is "0" as shown in WDATA16 of the cycle C3.
xABCDECDE ”. This data is latched and stored in HLDWDATA21 and MEMWDATA26.
As shown in, the data is being input to the memory 2 during the cycle C4. On the other hand, the write command WE12 is latched, becomes high during the cycle C3 as in the MEMWE22, and is sampled from the memory 2 at the end timing of the cycle C3. As a result, the data “0xABCDECDE” is written to the address of the memory 2 at the end timing of the next cycle C4. This state is shown in the row "0x3FF" in the figure. "0x0" in the figure
00, “0x345” and “0x3FF” respectively indicate the contents of the memory address. Note that the cycle C4 is the same write cycle, and the content of the address 0x000 becomes “0x8765465” at the end timing of the cycle C5.
4 ”has been confirmed.

[Cycle C5] In FIG. 8, signals having meaning in cycle C5 are shaded to emphasize their timing. As shown in WE12 and ADDR15, the cycle C5 is a write cycle to the address 0x345, and the write data is "0xFEDCBDCB" as shown in WDATA16 of the cycle C5. This data is latched and stored in HLDWDATA21 and MEMWD
As shown in the ATA 26, the data is input to the memory 2 in the cycles C6 to C9. This is three cycles C
This is because the read cycle enters C6, C7, and C8, and the write operation waits. Upon completion of these three read cycles, RE14 is low at the start timing of cycle C9, MEMWE22 is high at the same timing, and data "0xFE" is reached at the end timing of cycle C9.
DCBDCB ”is written to the memory 2.

[Cycle C6] In FIG. 9, a signal having a meaning in cycle C6 is shaded to emphasize its timing. As shown in WE12 and ADDR15, the cycle C6 is a read cycle to the address 0x3FF. The output 530 of the comparator 522 goes low because the closest write cycle before this cycle was to another address 0x345. Memory 2
Is an access time satisfying the specifications of FIG.
Correct data “0xABCDE CDE” like A27
Is output to the RDA via the read data selection circuit 5.
Appears at TA17 and is sampled by the processor or the like at the end timing of cycle C6. This read operation is
The same applies to the next cycle C7.

The present invention has been described above based on the embodiments. In the present embodiment, it is possible to secure a sufficient margin even in the circuit configuration in which it is difficult to secure the setup time of the write data and the byte write signal for the memory 2. Further, since the read of the delayed write data can be realized by the latch, it is not necessary to wait for the access to the memory 2. Furthermore, the design becomes easy because the timing of the clock itself is not adjusted.
This is because, in general, timing design is extremely difficult when skew occurs in a plurality of high-frequency clocks. Moreover, in the present embodiment, since it is not necessary to provide a special circuit inside the memory 2, the memory 2 can be designed easily and versatilely.

It should be understood by those skilled in the art that the present embodiment is an exemplification, and that various modifications can be made to the respective constituent elements and respective processing timings, and that such modifications are also within the scope of the present invention. By the way. For example, memory 2
5 is not limited to the specifications shown in FIGS. 5 and 6, and it is sufficient that the memory control circuit 1 according to the embodiment has a margin in operation timing.

[0041]

According to the present invention, there is a margin in the control timing of the memory, which facilitates the design.

[Brief description of drawings]

FIG. 1 is a configuration diagram showing a memory control circuit according to an embodiment together with a memory.

FIG. 2 is a circuit diagram of a latch control circuit and a latch function circuit in a memory control circuit.

FIG. 3 is a circuit diagram of a memory input control circuit in the memory control circuit.

FIG. 4 is a circuit diagram of a read data selection circuit in the memory control circuit.

FIG. 5 is a timing diagram of a write cycle of a memory to be controlled.

FIG. 6 is a timing diagram of a read cycle of a memory to be controlled.

FIG. 7 is a timing diagram in which a memory is controlled by a memory control circuit.

FIG. 8 is a timing diagram in which a memory is controlled by a memory control circuit.

FIG. 9 is a timing diagram in which a memory is controlled by a memory control circuit.

[Explanation of symbols]

1 memory control circuit, 3 latch control circuit, 4 memory input control circuit, 5 read data selection circuit, 6
Write command latch, 7 byte write signal latch, 8 address latch, 9 write data latch, 50 latch function circuit, 500 selector,
504 selector, 508 selector, 512 selector, 520 ADDR delay circuit, 522 comparator.

Claims (11)

[Claims] 1. A circuit for controlling the memory, which is connected to a memory that operates in synchronization with a clock, wherein the control circuit includes a signal line for externally acting like the memory. When we call it a deemed memory,
The control circuit has an address input port, a write data input port, a read data output port, an address latch circuit, a write data latch circuit, and a read data selection circuit. In the same clock cycle as the read cycle corresponding to the read operation, the read cycle corresponding to the read operation is generated in the memory, and when the write operation to the deemed memory is generated, the address port corresponding to the write operation is generated. Temporarily holds the address input from the address latch circuit,
Further, write data input from the port capable of inputting write data corresponding to the write operation is temporarily held in the write data latch circuit, and a write cycle corresponding to the write operation for the memory is performed for the deemed memory. The write operation is delayed by a natural number multiple of one clock cycle, and the read data selection circuit outputs the data from the output of the memory and the data held by the write data latch circuit in the read operation to the deemed memory. A memory control circuit, wherein either one is selected for each field and read data is output from a port capable of outputting the read data. 2. The memory according to claim 1, wherein the memory control circuit operates in synchronization with a clock in which an edge is intentionally generated without delay at one of the rising edge and the falling edge of the clock. Control circuit. 3. The memory control circuit according to claim 1, wherein the memory control circuit operates in synchronization with the clock having no intentional delay. 4. The memory control circuit according to claim 1, wherein the memory control circuit acts to relax a setup time of at least one of write data and an address for the memory. 5. The read data selection circuit includes a comparator that compares an address corresponding to a read cycle currently in progress with an address held in the address latch circuit, and confirms that both match. The memory control circuit according to claim 1, wherein the selection is performed as one of the conditions. 6. A byte write command input port and a byte write command latch circuit are further provided, and when a write operation to the assumed memory occurs, a byte write command from the byte write command input port corresponding to the write operation. The input is temporarily held in the byte write latch circuit, and the read data selection circuit performs the selection by using a value held by the byte write command latch circuit as one of conditions. A memory control circuit according to any one of 1. 7. The memory control circuit according to claim 1, wherein the memory control circuit operates so as to relax a setup time of a byte write command for the memory. 8. The memory control circuit according to claim 1, wherein the data field has a unit of byte. 9. A port capable of inputting the write data,
9. The memory control circuit according to claim 1, wherein the ports capable of outputting the read data are separate ports. 10. The port capable of inputting write data and the port capable of outputting read data are common,
9. A bidirectional port, characterized in that it is a bidirectional port.
A memory control circuit according to any one of 1. 11. A method for controlling a memory which operates in synchronization with a clock, wherein an address and data related to a write operation for the memory are latched by the clock and delayed, and then input to the memory, To increase the setup time of at least one of the address and the data by creating a state in which the access cycle of the write operation with respect to the memory is delayed by a natural multiple of the cycle of the clock when viewed from the memory. The consistency of the operation of the memory is detected by detecting the state in which the operation of the memory may be defective due to the delay of the cycle and taking the avoidance processing of the defect outside the memory without inserting the wait. A method for controlling a memory, characterized in that: